a1aeaf22c2a20b208652c84feee1daa65b553550
[reactos.git] / reactos / ntoskrnl / include / internal / amd64 / mm.h
1 /*
2 * Lowlevel memory managment definitions
3 */
4
5 #pragma once
6
7 /* Helper macros */
8 #define PAGE_MASK(x) ((x)&(~0xfff))
9 #define PAE_PAGE_MASK(x) ((x)&(~0xfffLL))
10
11 /* Memory layout base addresses */
12 #define HYPER_SPACE 0xFFFFF70000000000ULL
13 #define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL
14 #define MI_SESSION_SPACE_MINIMUM (PVOID)0xFFFFF90000000000ULL
15 #define MI_SESSION_VIEW_END (PVOID)0xFFFFF97FFF000000ULL
16 #define MI_SESSION_SPACE_END (PVOID)0xFFFFF98000000000ULL
17 #define MI_SYSTEM_PTE_START (PVOID)0xFFFFFAA000000000ULL
18 #define MI_PAGED_POOL_START (PVOID)0xFFFFFA8000000000ULL
19 #define MI_NON_PAGED_SYSTEM_START_MIN 0xFFFFFAA000000000ULL
20 #define MI_PFN_DATABASE (PVOID)0xFFFFFAC000000000ULL
21 #define MI_NONPAGED_POOL_END (PVOID)0xFFFFFAE000000000ULL
22 #define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
23 #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
24 #define MI_SYSTEM_CACHE_WS_START (PVOID)0xFFFFF78000001000ULL // CHECKME
25
26 /* Memory sizes */
27 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
28 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT)
29 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT)
30 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
31 #define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
32 #define MI_MAX_FREE_PAGE_LISTS 4
33 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024)
34 #define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024)
35 #define MI_SESSION_POOL_SIZE (16 * 1024 * 1024)
36 #define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024)
37 #define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024)
38 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
39 MI_SESSION_POOL_SIZE + \
40 MI_SESSION_IMAGE_SIZE + \
41 MI_SESSION_WORKING_SET_SIZE)
42 #define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024)
43 #define MI_NUMBER_SYSTEM_PTES 22000
44
45 #define MI_MIN_SECONDARY_COLORS 8
46 #define MI_SECONDARY_COLORS 64
47 #define MI_MAX_SECONDARY_COLORS 1024
48
49 #define MM_HIGHEST_VAD_ADDRESS \
50 (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
51
52 PULONG64
53 FORCEINLINE
54 MmGetPageDirectory(VOID)
55 {
56 return (PULONG64)__readcr3();
57 }
58
59 PMMPTE
60 FORCEINLINE
61 MiAddressToPxe(PVOID Address)
62 {
63 ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
64 Offset &= PXI_MASK << 3;
65 return (PMMPTE)(PXE_BASE + Offset);
66 }
67
68 PMMPTE
69 FORCEINLINE
70 MiAddressToPpe(PVOID Address)
71 {
72 ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
73 Offset &= 0x3FFFF << 3;
74 return (PMMPTE)(PPE_BASE + Offset);
75 }
76
77 PMMPTE
78 FORCEINLINE
79 _MiAddressToPde(PVOID Address)
80 {
81 ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
82 Offset &= 0x7FFFFFF << 3;
83 return (PMMPTE)(PDE_BASE + Offset);
84 }
85 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
86
87 PMMPTE
88 FORCEINLINE
89 _MiAddressToPte(PVOID Address)
90 {
91 ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
92 Offset &= 0xFFFFFFFFFULL << 3;
93 return (PMMPTE)(PTE_BASE + Offset);
94 }
95 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
96
97 /* Convert a PTE into a corresponding address */
98 PVOID
99 FORCEINLINE
100 MiPteToAddress(PMMPTE Pte)
101 {
102 /* Use signed math */
103 LONG64 Temp = (LONG64)Pte;
104 Temp <<= 25;
105 Temp >>= 16;
106 return (PVOID)Temp;
107 }
108
109 BOOLEAN
110 FORCEINLINE
111 MiIsPdeForAddressValid(PVOID Address)
112 {
113 return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
114 (MiAddressToPpe(Address)->u.Hard.Valid) &&
115 (MiAddressToPde(Address)->u.Hard.Valid));
116 }
117
118 #define ADDR_TO_PAGE_TABLE(v) (((ULONG_PTR)(v)) / (512 * PAGE_SIZE))
119 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
120 #define ADDR_TO_PTE_OFFSET(v) ((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE)
121
122 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
123
124 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
125 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
126 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
127 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
128
129 /* We don't use these hacks */
130 VOID
131 FORCEINLINE
132 MmUpdatePageDir(PEPROCESS Process, PVOID Address, ULONG Size)
133 {
134 /* Nothing to do */
135 }
136
137 VOID
138 FORCEINLINE
139 MmInitGlobalKernelPageDirectory(VOID)
140 {
141 /* Nothing to do */
142 }
143
144 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
145 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
146
147 /* Easy accessing PFN in PTE */
148 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
149
150 // FIXME, only copied from x86
151 #define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
152 #define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
153 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
154 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
155 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
156 #if !defined(CONFIG_SMP)
157 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
158 #else
159 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
160 #endif
161 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
162 #define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
163 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
164 #if !defined(CONFIG_SMP)
165 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
166 #else
167 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
168 #endif
169
170 // FIXME!!!
171 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
172 ((x) / (4*1024*1024))
173
174 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
175 ((((x)) % (4*1024*1024)) / (4*1024))
176
177 #define NR_SECTION_PAGE_TABLES 1024
178 #define NR_SECTION_PAGE_ENTRIES 1024
179
180 //#define TEB_BASE 0x7FFDE000
181
182 #define MI_HYPERSPACE_PTES (256 - 1)
183 #define MI_ZERO_PTES (32)
184 #define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
185 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
186 MI_HYPERSPACE_PTES * PAGE_SIZE)
187 #define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
188 PAGE_SIZE)
189
190 /* On x86, these two are the same */
191 #define MMPDE MMPTE
192 #define PMMPDE PMMPTE
193
194 /*
195 * FIXME - different architectures have different cache line sizes...
196 */
197 #define MM_CACHE_LINE_SIZE 32
198