reactos/ntoskrnl/include/internal/amd64/mm.h

   1 /*
   2  * Lowlevel memory managment definitions
   3  */
   4
   5 #ifndef __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H
   6 #define __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H
   7
   8 /* Helper macros */
   9 #define PAGE_MASK(x)            ((x)&(~0xfff))
  10 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  11
  12 /* Memory layout base addresses */
  13 #define HYPER_SPACE                            0xFFFFF70000000000ULL
  14 #define HYPER_SPACE_END                        0xFFFFF77FFFFFFFFFULL
  15 #define MI_SESSION_VIEW_END             (PVOID)0xFFFFF97FFF000000ULL
  16 #define MI_SESSION_SPACE_END            (PVOID)0xFFFFF98000000000ULL
  17 #define MI_SYSTEM_PTE_START             (PVOID)0xFFFFFAA000000000ULL
  18 #define MI_PAGED_POOL_START             (PVOID)0xFFFFFA8000000000ULL
  19 #define MI_NON_PAGED_SYSTEM_START_MIN          0xFFFFFAA000000000ULL
  20 #define MI_NONPAGED_POOL_END            (PVOID)0xFFFFFAE000000000ULL
  21 #define MI_DEBUG_MAPPING                (PVOID)0xFFFFFFFF80000000ULL // FIXME
  22 #define MI_HIGHEST_SYSTEM_ADDRESS       (PVOID)0xFFFFFFFFFFFFFFFFULL
  23
  24
  25 #define MI_NUMBER_SYSTEM_PTES 22000
  26
  27 PULONG64
  28 FORCEINLINE
  29 MmGetPageDirectory(VOID)
  30 {
  31     return (PULONG64)__readcr3();
  32 }
  33
  34 PMMPTE
  35 FORCEINLINE
  36 MiAddressToPxe(PVOID Address)
  37 {
  38     ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
  39     Offset &= PXI_MASK << 3;
  40     return (PMMPTE)(PXE_BASE + Offset);
  41 }
  42
  43 PMMPTE
  44 FORCEINLINE
  45 MiAddressToPpe(PVOID Address)
  46 {
  47     ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
  48     Offset &= 0x3FFFF << 3;
  49     return (PMMPTE)(PPE_BASE + Offset);
  50 }
  51
  52 PMMPTE
  53 FORCEINLINE
  54 MiAddressToPde(PVOID Address)
  55 {
  56     ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
  57     Offset &= 0x7FFFFFF << 3;
  58     return (PMMPTE)(PDE_BASE + Offset);
  59 }
  60
  61 PMMPTE
  62 FORCEINLINE
  63 MiAddressToPte(PVOID Address)
  64 {
  65     ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
  66     Offset &= 0xFFFFFFFFFULL << 3;
  67     return (PMMPTE)(PTE_BASE + Offset);
  68 }
  69
  70 /* Convert a PTE into a corresponding address */
  71 PVOID
  72 FORCEINLINE
  73 MiPteToAddress(PMMPTE Pte)
  74 {
  75     /* Use signed math */
  76     LONG64 Temp = (LONG64)Pte;
  77     Temp <<= 25;
  78     Temp >>= 16;
  79     return (PVOID)Temp;
  80 }
  81
  82 //#define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
  83 //#define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
  84 //#define ADDR_TO_PTE_OFFSET(v)  ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
  85
  86 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
  87 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
  88 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
  89 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
  90
  91 /* We don't use these hacks */
  92 VOID
  93 FORCEINLINE
  94 MmUpdatePageDir(PEPROCESS Process, PVOID Address, ULONG Size)
  95 {
  96     /* Nothing to do */
  97 }
  98
  99 VOID
 100 FORCEINLINE
 101 MmInitGlobalKernelPageDirectory(VOID)
 102 {
 103     /* Nothing to do */
 104 }
 105
 106
 107 /// MIARM.H
 108
 109 /* Easy accessing PFN in PTE */
 110 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 111
 112 // FIXME, only copied from x86
 113 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
 114 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
 115 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
 116 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
 117 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
 118 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
 119 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
 120 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
 121 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 122 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 123
 124
 125 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
 126 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)
 127 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST          ((32*1024*1024) >> PAGE_SHIFT)
 128 #define MI_MAX_INIT_NONPAGED_POOL_SIZE         (128ULL * 1024 * 1024 * 1024)
 129 #define MI_MAX_NONPAGED_POOL_SIZE              (128ULL * 1024 * 1024 * 1024)
 130 #define MI_MAX_FREE_PAGE_LISTS                 4
 131
 132 #define MI_MIN_INIT_PAGED_POOLSIZE             (32 * 1024 * 1024)
 133
 134 #define MI_SESSION_VIEW_SIZE                   (20 * 1024 * 1024)
 135 #define MI_SESSION_POOL_SIZE                   (16 * 1024 * 1024)
 136 #define MI_SESSION_IMAGE_SIZE                  (8 * 1024 * 1024)
 137 #define MI_SESSION_WORKING_SET_SIZE            (4 * 1024 * 1024)
 138 #define MI_SESSION_SIZE                        (MI_SESSION_VIEW_SIZE + \
 139                                                 MI_SESSION_POOL_SIZE + \
 140                                                 MI_SESSION_IMAGE_SIZE + \
 141                                                 MI_SESSION_WORKING_SET_SIZE)
 142
 143 #define MI_SYSTEM_VIEW_SIZE                    (16 * 1024 * 1024)
 144
 145
 146 #define MM_HIGHEST_VAD_ADDRESS \
 147     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
 148
 149
 150 //
 151 // FIXFIX: These should go in ex.h after the pool merge
 152 //
 153 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / sizeof(LIST_ENTRY))
 154 #define BASE_POOL_TYPE_MASK 1
 155 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + sizeof(LIST_ENTRY)))
 156
 157 #endif /* __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H */