reactos/ntoskrnl/include/internal/amd64/mm.h

   1 /*
   2  * Lowlevel memory managment definitions
   3  */
   4
   5 #ifndef __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H
   6 #define __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H
   7
   8 /* Helper macros */
   9 #define PAGE_MASK(x)            ((x)&(~0xfff))
  10 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  11
  12 /* Memory layout base addresses */
  13 #define HYPER_SPACE                            0xFFFFF70000000000ULL
  14 #define HYPER_SPACE_END                        0xFFFFF77FFFFFFFFFULL
  15 #define MI_SESSION_SPACE_MINIMUM        (PVOID)0xFFFFF90000000000ULL
  16 #define MI_SESSION_VIEW_END             (PVOID)0xFFFFF97FFF000000ULL
  17 #define MI_SESSION_SPACE_END            (PVOID)0xFFFFF98000000000ULL
  18 #define MI_SYSTEM_PTE_START             (PVOID)0xFFFFFAA000000000ULL
  19 #define MI_PAGED_POOL_START             (PVOID)0xFFFFFA8000000000ULL
  20 #define MI_NON_PAGED_SYSTEM_START_MIN          0xFFFFFAA000000000ULL
  21 #define MI_PFN_DATABASE                 (PVOID)0xFFFFFAC000000000ULL
  22 #define MI_NONPAGED_POOL_END            (PVOID)0xFFFFFAE000000000ULL
  23 #define MI_DEBUG_MAPPING                (PVOID)0xFFFFFFFF80000000ULL // FIXME
  24 #define MI_HIGHEST_SYSTEM_ADDRESS       (PVOID)0xFFFFFFFFFFFFFFFFULL
  25
  26
  27 #define MI_NUMBER_SYSTEM_PTES 22000
  28
  29 PULONG64
  30 FORCEINLINE
  31 MmGetPageDirectory(VOID)
  32 {
  33     return (PULONG64)__readcr3();
  34 }
  35
  36 PMMPTE
  37 FORCEINLINE
  38 MiAddressToPxe(PVOID Address)
  39 {
  40     ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
  41     Offset &= PXI_MASK << 3;
  42     return (PMMPTE)(PXE_BASE + Offset);
  43 }
  44
  45 PMMPTE
  46 FORCEINLINE
  47 MiAddressToPpe(PVOID Address)
  48 {
  49     ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
  50     Offset &= 0x3FFFF << 3;
  51     return (PMMPTE)(PPE_BASE + Offset);
  52 }
  53
  54 PMMPTE
  55 FORCEINLINE
  56 MiAddressToPde(PVOID Address)
  57 {
  58     ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
  59     Offset &= 0x7FFFFFF << 3;
  60     return (PMMPTE)(PDE_BASE + Offset);
  61 }
  62
  63 PMMPTE
  64 FORCEINLINE
  65 MiAddressToPte(PVOID Address)
  66 {
  67     ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
  68     Offset &= 0xFFFFFFFFFULL << 3;
  69     return (PMMPTE)(PTE_BASE + Offset);
  70 }
  71
  72 /* Convert a PTE into a corresponding address */
  73 PVOID
  74 FORCEINLINE
  75 MiPteToAddress(PMMPTE Pte)
  76 {
  77     /* Use signed math */
  78     LONG64 Temp = (LONG64)Pte;
  79     Temp <<= 25;
  80     Temp >>= 16;
  81     return (PVOID)Temp;
  82 }
  83
  84 BOOLEAN
  85 FORCEINLINE
  86 MiIsPdeForAddressValid(PVOID Address)
  87 {
  88     return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
  89             (MiAddressToPpe(Address)->u.Hard.Valid) &&
  90             (MiAddressToPde(Address)->u.Hard.Valid));
  91 }
  92
  93 //#define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
  94 //#define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
  95 //#define ADDR_TO_PTE_OFFSET(v)  ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
  96
  97 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
  98 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
  99 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
 100 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
 101
 102 /* We don't use these hacks */
 103 VOID
 104 FORCEINLINE
 105 MmUpdatePageDir(PEPROCESS Process, PVOID Address, ULONG Size)
 106 {
 107     /* Nothing to do */
 108 }
 109
 110 VOID
 111 FORCEINLINE
 112 MmInitGlobalKernelPageDirectory(VOID)
 113 {
 114     /* Nothing to do */
 115 }
 116
 117 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
 118 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
 119
 120 /// MIARM.H
 121
 122 /* Easy accessing PFN in PTE */
 123 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 124
 125 // FIXME, only copied from x86
 126 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
 127 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
 128 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
 129 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
 130 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
 131 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
 132 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
 133 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
 134 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 135 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 136
 137
 138 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
 139 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)
 140 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST          ((32*1024*1024) >> PAGE_SHIFT)
 141 #define MI_MAX_INIT_NONPAGED_POOL_SIZE         (128ULL * 1024 * 1024 * 1024)
 142 #define MI_MAX_NONPAGED_POOL_SIZE              (128ULL * 1024 * 1024 * 1024)
 143 #define MI_MAX_FREE_PAGE_LISTS                 4
 144
 145 #define MI_MIN_INIT_PAGED_POOLSIZE             (32 * 1024 * 1024)
 146
 147 #define MI_SESSION_VIEW_SIZE                   (20 * 1024 * 1024)
 148 #define MI_SESSION_POOL_SIZE                   (16 * 1024 * 1024)
 149 #define MI_SESSION_IMAGE_SIZE                  (8 * 1024 * 1024)
 150 #define MI_SESSION_WORKING_SET_SIZE            (4 * 1024 * 1024)
 151 #define MI_SESSION_SIZE                        (MI_SESSION_VIEW_SIZE + \
 152                                                 MI_SESSION_POOL_SIZE + \
 153                                                 MI_SESSION_IMAGE_SIZE + \
 154                                                 MI_SESSION_WORKING_SET_SIZE)
 155
 156 #define MI_SYSTEM_VIEW_SIZE                    (16 * 1024 * 1024)
 157
 158
 159 #define MM_HIGHEST_VAD_ADDRESS \
 160     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
 161
 162
 163 //
 164 // FIXFIX: These should go in ex.h after the pool merge
 165 //
 166 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / sizeof(LIST_ENTRY))
 167 #define BASE_POOL_TYPE_MASK 1
 168 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + sizeof(LIST_ENTRY)))
 169
 170 #endif /* __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H */