reactos/ntoskrnl/include/internal/arm/mm.h

   1 #pragma once
   2
   3 #define PDE_SHIFT 20
   4
   5 //
   6 // Number of bits corresponding to the area that a coarse page table entry represents (4KB)
   7 //
   8 #define PTE_SHIFT 12
   9 #define PTE_SIZE (1 << PTE_SHIFT)
  10
  11 //
  12 // Number of bits corresponding to the area that a coarse page table occupies (1KB)
  13 //
  14 #define CPT_SHIFT 10
  15 #define CPT_SIZE  (1 << CPT_SHIFT)
  16
  17 //
  18 // Base Addresses
  19 //
  20 #define PTE_BASE    0xC0000000
  21 #define PTE_TOP     0xC03FFFFF
  22 #define PDE_BASE    0xC0400000
  23 #define HYPER_SPACE 0xC0500000
  24
  25 #if 0
  26 typedef struct _HARDWARE_PDE_ARMV6
  27 {
  28     ULONG Valid:1;     // Only for small pages
  29     ULONG LargePage:1; // Note, if large then Valid = 0
  30     ULONG Buffered:1;
  31     ULONG Cached:1;
  32     ULONG NoExecute:1;
  33     ULONG Domain:4;
  34     ULONG Ecc:1;
  35     ULONG PageFrameNumber:22;
  36 } HARDWARE_PDE_ARMV6, *PHARDWARE_PDE_ARMV6;
  37
  38 typedef struct _HARDWARE_LARGE_PTE_ARMV6
  39 {
  40     ULONG Valid:1;     // Only for small pages
  41     ULONG LargePage:1; // Note, if large then Valid = 0
  42     ULONG Buffered:1;
  43     ULONG Cached:1;
  44     ULONG NoExecute:1;
  45     ULONG Domain:4;
  46     ULONG Ecc:1;
  47     ULONG Accessed:1;
  48     ULONG Owner:1;
  49     ULONG CacheAttributes:3;
  50     ULONG ReadOnly:1;
  51     ULONG Shared:1;
  52     ULONG NonGlobal:1;
  53     ULONG SuperLagePage:1;
  54     ULONG Reserved:1;
  55     ULONG PageFrameNumber:12;
  56 } HARDWARE_LARGE_PTE_ARMV6, *PHARDWARE_LARGE_PTE_ARMV6;
  57
  58 typedef struct _HARDWARE_PTE_ARMV6
  59 {
  60     ULONG NoExecute:1;
  61     ULONG Valid:1;
  62     ULONG Buffered:1;
  63     ULONG Cached:1;
  64     ULONG Accessed:1;
  65     ULONG Owner:1;
  66     ULONG CacheAttributes:3;
  67     ULONG ReadOnly:1;
  68     ULONG Shared:1;
  69     ULONG NonGlobal:1;
  70     ULONG PageFrameNumber:20;
  71 } HARDWARE_PTE_ARMV6, *PHARDWARE_PTE_ARMV6;
  72
  73 C_ASSERT(sizeof(HARDWARE_PDE_ARMV6) == sizeof(ULONG));
  74 C_ASSERT(sizeof(HARDWARE_LARGE_PTE_ARMV6) == sizeof(ULONG));
  75 C_ASSERT(sizeof(HARDWARE_PTE_ARMV6) == sizeof(ULONG));
  76 #endif
  77
  78 /* For FreeLDR */
  79 typedef struct _PAGE_TABLE_ARM
  80 {
  81     HARDWARE_PTE_ARMV6 Pte[1024];
  82 } PAGE_TABLE_ARM, *PPAGE_TABLE_ARM;
  83
  84 typedef struct _PAGE_DIRECTORY_ARM
  85 {
  86     union
  87     {
  88         HARDWARE_PDE_ARMV6 Pde[4096];
  89         HARDWARE_LARGE_PTE_ARMV6 Pte[4096];
  90     };
  91 } PAGE_DIRECTORY_ARM, *PPAGE_DIRECTORY_ARM;
  92
  93 C_ASSERT(sizeof(PAGE_TABLE_ARM) == PAGE_SIZE);
  94 C_ASSERT(sizeof(PAGE_DIRECTORY_ARM) == (4 * PAGE_SIZE));
  95
  96 typedef enum _ARM_DOMAIN
  97 {
  98     FaultDomain,
  99     ClientDomain,
 100     InvalidDomain,
 101     ManagerDomain
 102 } ARM_DOMAIN;
 103
 104 struct _EPROCESS;
 105 PULONG MmGetPageDirectory(VOID);
 106
 107 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.NonGlobal = 1)
 108 #define MI_MAKE_DIRTY_PAGE(x)
 109 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 110 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.ReadOnly = 0)
 111 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.Cached = 0)
 112 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.Buffered = 0)
 113 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.Buffered = 1)
 114 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.ReadOnly == 0)
 115 #define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE
 116 #define MI_IS_PAGE_DIRTY(x)        TRUE
 117
 118 /* Easy accessing PFN in PTE */
 119 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 120
 121 #define NR_SECTION_PAGE_TABLES              1024
 122 #define NR_SECTION_PAGE_ENTRIES             256
 123
 124 /* See PDR definition */
 125 #define MI_HYPERSPACE_PTES                  (256 - 1)
 126 #define MI_ZERO_PTES                        (32)
 127 #define MI_MAPPING_RANGE_START              ((ULONG)HYPER_SPACE)
 128 #define MI_MAPPING_RANGE_END                (MI_MAPPING_RANGE_START + \
 129                                              MI_HYPERSPACE_PTES * PAGE_SIZE)
 130 #define MI_ZERO_PTE                         (PMMPTE)(MI_MAPPING_RANGE_END + \
 131                                              PAGE_SIZE)
 132
 133 /* Retrives the PDE entry for the given VA */
 134 #define MiGetPdeAddress(x) ((PMMPDE)(PDE_BASE + (((ULONG)(x) >> 20) << 2)))
 135 #define MiAddressToPde(x)  MiGetPdeAddress(x)
 136
 137 /* Retrieves the PTE entry for the given VA */
 138 #define MiGetPteAddress(x) ((PMMPTE)(PTE_BASE + (((ULONG)(x) >> 12) << 2)))
 139 #define MiAddressToPte(x)  MiGetPteAddress(x)
 140
 141 /* Retrives the PDE offset for the given VA */
 142 #define MiGetPdeOffset(x) (((ULONG)(x)) >> 20)
 143
 144 /* Convert a PTE into a corresponding address */
 145 #define MiPteToAddress(x) ((PVOID)((ULONG)(x) << 10))
 146 #define MiPdeToAddress(x) ((PVOID)((ULONG)(x) << 18))
 147
 148 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
 149     ((x) / (4*1024*1024))
 150
 151 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
 152     ((((x)) % (4*1024*1024)) / (4*1024))
 153
 154 #define MM_CACHE_LINE_SIZE 64