reactos/ntoskrnl/include/internal/arm/mm.h

   1 #pragma once
   2
   3 //
   4 // Number of bits corresponding to the area that a PDE entry represents (1MB)
   5 //
   6 #define PDE_SHIFT 20
   7 #define PDE_SIZE  (1 << PDE_SHIFT)
   8
   9 //
  10 // Number of bits corresponding to the area that a coarse page table entry represents (4KB)
  11 //
  12 #define PTE_SHIFT 12
  13 #define PTE_SIZE (1 << PTE_SHIFT)
  14
  15 //
  16 // Number of bits corresponding to the area that a coarse page table occupies (1KB)
  17 //
  18 #define CPT_SHIFT 10
  19 #define CPT_SIZE  (1 << CPT_SHIFT)
  20
  21 //
  22 // Base Addresses
  23 //
  24 #define PTE_BASE    0xC0000000
  25 #define PTE_TOP     0xC03FFFFF
  26 #define PDE_BASE    0xC0400000
  27 #define HYPER_SPACE 0xC0500000
  28
  29 #if 0
  30 typedef struct _HARDWARE_PDE_ARMV6
  31 {
  32     ULONG Valid:1;     // Only for small pages
  33     ULONG LargePage:1; // Note, if large then Valid = 0
  34     ULONG Buffered:1;
  35     ULONG Cached:1;
  36     ULONG NoExecute:1;
  37     ULONG Domain:4;
  38     ULONG Ecc:1;
  39     ULONG PageFrameNumber:22;
  40 } HARDWARE_PDE_ARMV6, *PHARDWARE_PDE_ARMV6;
  41
  42 typedef struct _HARDWARE_LARGE_PTE_ARMV6
  43 {
  44     ULONG Valid:1;     // Only for small pages
  45     ULONG LargePage:1; // Note, if large then Valid = 0
  46     ULONG Buffered:1;
  47     ULONG Cached:1;
  48     ULONG NoExecute:1;
  49     ULONG Domain:4;
  50     ULONG Ecc:1;
  51     ULONG Accessed:1;
  52     ULONG Owner:1;
  53     ULONG CacheAttributes:3;
  54     ULONG ReadOnly:1;
  55     ULONG Shared:1;
  56     ULONG NonGlobal:1;
  57     ULONG SuperLagePage:1;
  58     ULONG Reserved:1;
  59     ULONG PageFrameNumber:12;
  60 } HARDWARE_LARGE_PTE_ARMV6, *PHARDWARE_LARGE_PTE_ARMV6;
  61
  62 typedef struct _HARDWARE_PTE_ARMV6
  63 {
  64     ULONG NoExecute:1;
  65     ULONG Valid:1;
  66     ULONG Buffered:1;
  67     ULONG Cached:1;
  68     ULONG Accessed:1;
  69     ULONG Owner:1;
  70     ULONG CacheAttributes:3;
  71     ULONG ReadOnly:1;
  72     ULONG Shared:1;
  73     ULONG NonGlobal:1;
  74     ULONG PageFrameNumber:20;
  75 } HARDWARE_PTE_ARMV6, *PHARDWARE_PTE_ARMV6;
  76
  77 C_ASSERT(sizeof(HARDWARE_PDE_ARMV6) == sizeof(ULONG));
  78 C_ASSERT(sizeof(HARDWARE_LARGE_PTE_ARMV6) == sizeof(ULONG));
  79 C_ASSERT(sizeof(HARDWARE_PTE_ARMV6) == sizeof(ULONG));
  80 #endif
  81
  82 /* For FreeLDR */
  83 typedef struct _PAGE_TABLE_ARM
  84 {
  85     HARDWARE_PTE_ARMV6 Pte[1024];
  86 } PAGE_TABLE_ARM, *PPAGE_TABLE_ARM;
  87
  88 typedef struct _PAGE_DIRECTORY_ARM
  89 {
  90     union
  91     {
  92         HARDWARE_PDE_ARMV6 Pde[4096];
  93         HARDWARE_LARGE_PTE_ARMV6 Pte[4096];
  94     };
  95 } PAGE_DIRECTORY_ARM, *PPAGE_DIRECTORY_ARM;
  96
  97 C_ASSERT(sizeof(PAGE_TABLE_ARM) == PAGE_SIZE);
  98 C_ASSERT(sizeof(PAGE_DIRECTORY_ARM) == (4 * PAGE_SIZE));
  99
 100 typedef enum _ARM_DOMAIN
 101 {
 102     FaultDomain,
 103     ClientDomain,
 104     InvalidDomain,
 105     ManagerDomain
 106 } ARM_DOMAIN;
 107
 108 struct _EPROCESS;
 109 PULONG MmGetPageDirectory(VOID);
 110
 111 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.NonGlobal = 1)
 112 #define MI_MAKE_DIRTY_PAGE(x)
 113 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 114 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.ReadOnly = 0)
 115 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.Cached = 0)
 116 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.Buffered = 0)
 117 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.Buffered = 1)
 118 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.ReadOnly == 0)
 119 #define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE
 120 #define MI_IS_PAGE_DIRTY(x)        TRUE
 121
 122 /* Easy accessing PFN in PTE */
 123 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 124
 125 #define NR_SECTION_PAGE_TABLES              1024
 126 #define NR_SECTION_PAGE_ENTRIES             256
 127
 128 /* See PDR definition */
 129 #define MI_HYPERSPACE_PTES                  (256 - 1)
 130 #define MI_ZERO_PTES                        (32)
 131 #define MI_MAPPING_RANGE_START              ((ULONG)HYPER_SPACE)
 132 #define MI_MAPPING_RANGE_END                (MI_MAPPING_RANGE_START + \
 133                                              MI_HYPERSPACE_PTES * PAGE_SIZE)
 134 #define MI_ZERO_PTE                         (PMMPTE)(MI_MAPPING_RANGE_END + \
 135                                              PAGE_SIZE)
 136
 137 /* Retrives the PDE entry for the given VA */
 138 #define MiGetPdeAddress(x) ((PMMPDE)(PDE_BASE + (((ULONG)(x) >> 20) << 2)))
 139 #define MiAddressToPde(x)  MiGetPdeAddress(x)
 140
 141 /* Retrieves the PTE entry for the given VA */
 142 #define MiGetPteAddress(x) ((PMMPTE)(PTE_BASE + (((ULONG)(x) >> 12) << 2)))
 143 #define MiAddressToPte(x)  MiGetPteAddress(x)
 144
 145 /* Retrives the PDE offset for the given VA */
 146 #define MiGetPdeOffset(x) (((ULONG)(x)) >> 20)
 147
 148 /* Convert a PTE into a corresponding address */
 149 #define MiPteToAddress(x) ((PVOID)((ULONG)(x) << 10))
 150 #define MiPdeToAddress(x) ((PVOID)((ULONG)(x) << 18))
 151
 152 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
 153     ((x) / (4*1024*1024))
 154
 155 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
 156     ((((x)) % (4*1024*1024)) / (4*1024))
 157
 158 #define MM_CACHE_LINE_SIZE 64