reactos/ntoskrnl/include/internal/arm/mm.h

   1 #ifndef __NTOSKRNL_INCLUDE_INTERNAL_ARM_MM_H
   2 #define __NTOSKRNL_INCLUDE_INTERNAL_ARM_MM_H
   3
   4 //
   5 // Number of bits corresponding to the area that a PDE entry represents (1MB)
   6 //
   7 #define PDE_SHIFT 20
   8 #define PDE_SIZE  (1 << PDE_SHIFT)
   9
  10 //
  11 // Number of bits corresponding to the area that a coarse page table entry represents (4KB)
  12 //
  13 #define PTE_SHIFT 12
  14 #define PTE_SIZE (1 << PTE_SHIFT)
  15
  16 //
  17 // Number of bits corresponding to the area that a coarse page table occupies (1KB)
  18 //
  19 #define CPT_SHIFT 10
  20 #define CPT_SIZE  (1 << CPT_SHIFT)
  21
  22 //
  23 // Base Addresses
  24 //
  25 #define PTE_BASE    0xC0000000
  26 #define PTE_TOP     0xC03FFFFF
  27 #define PDE_BASE    0xC0400000
  28 #define HYPER_SPACE 0xC0404000
  29
  30 #if 0
  31 typedef struct _HARDWARE_PDE_ARMV6
  32 {
  33     ULONG Valid:1;     // Only for small pages
  34     ULONG LargePage:1; // Note, if large then Valid = 0
  35     ULONG Buffered:1;
  36     ULONG Cached:1;
  37     ULONG NoExecute:1;
  38     ULONG Domain:4;
  39     ULONG Ecc:1;
  40     ULONG PageFrameNumber:22;
  41 } HARDWARE_PDE_ARMV6, *PHARDWARE_PDE_ARMV6;
  42
  43 typedef struct _HARDWARE_LARGE_PTE_ARMV6
  44 {
  45     ULONG Valid:1;     // Only for small pages
  46     ULONG LargePage:1; // Note, if large then Valid = 0
  47     ULONG Buffered:1;
  48     ULONG Cached:1;
  49     ULONG NoExecute:1;
  50     ULONG Domain:4;
  51     ULONG Ecc:1;
  52     ULONG Accessed:1;
  53     ULONG Owner:1;
  54     ULONG CacheAttributes:3;
  55     ULONG ReadOnly:1;
  56     ULONG Shared:1;
  57     ULONG NonGlobal:1;
  58     ULONG SuperLagePage:1;
  59     ULONG Reserved:1;
  60     ULONG PageFrameNumber:12;
  61 } HARDWARE_LARGE_PTE_ARMV6, *PHARDWARE_LARGE_PTE_ARMV6;
  62
  63 typedef struct _HARDWARE_PTE_ARMV6
  64 {
  65     ULONG NoExecute:1;
  66     ULONG Valid:1;
  67     ULONG Buffered:1;
  68     ULONG Cached:1;
  69     ULONG Accessed:1;
  70     ULONG Owner:1;
  71     ULONG CacheAttributes:3;
  72     ULONG ReadOnly:1;
  73     ULONG Shared:1;
  74     ULONG NonGlobal:1;
  75     ULONG PageFrameNumber:20;
  76 } HARDWARE_PTE_ARMV6, *PHARDWARE_PTE_ARMV6;
  77
  78 C_ASSERT(sizeof(HARDWARE_PDE_ARMV6) == sizeof(ULONG));
  79 C_ASSERT(sizeof(HARDWARE_LARGE_PTE_ARMV6) == sizeof(ULONG));
  80 C_ASSERT(sizeof(HARDWARE_PTE_ARMV6) == sizeof(ULONG));
  81 #endif
  82
  83 /* For FreeLDR */
  84 typedef struct _PAGE_TABLE_ARM
  85 {
  86     HARDWARE_PTE_ARMV6 Pte[1024];
  87 } PAGE_TABLE_ARM, *PPAGE_TABLE_ARM;
  88
  89 typedef struct _PAGE_DIRECTORY_ARM
  90 {
  91     union
  92     {
  93         HARDWARE_PDE_ARMV6 Pde[4096];
  94         HARDWARE_LARGE_PTE_ARMV6 Pte[4096];
  95     };
  96 } PAGE_DIRECTORY_ARM, *PPAGE_DIRECTORY_ARM;
  97
  98 C_ASSERT(sizeof(PAGE_TABLE_ARM) == PAGE_SIZE);
  99 C_ASSERT(sizeof(PAGE_DIRECTORY_ARM) == (4 * PAGE_SIZE));
 100
 101 typedef enum _ARM_DOMAIN
 102 {
 103     FaultDomain,
 104     ClientDomain,
 105     InvalidDomain,
 106     ManagerDomain
 107 } ARM_DOMAIN;
 108
 109 struct _EPROCESS;
 110 PULONG MmGetPageDirectory(VOID);
 111
 112 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.NonGlobal = 1)
 113 #define MI_MAKE_DIRTY_PAGE(x)
 114 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 115 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.ReadOnly = 0)
 116 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.Cached = 0)
 117 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.Buffered = 0)
 118 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.Buffered = 1)
 119 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.ReadOnly == 0)
 120 #define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE
 121 #define MI_IS_PAGE_DIRTY(x)        TRUE
 122
 123 /* Easy accessing PFN in PTE */
 124 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 125
 126
 127 #if 1
 128
 129 //
 130 // FIXFIX: This is all wrong now!!!
 131 //
 132
 133 //
 134 // Take 0x80812345 and extract:
 135 // PTE_BASE[0x808][0x12]
 136 //
 137 #define MiGetPteAddress(x)         \
 138     (PMMPTE)(PTE_BASE + \
 139              (((ULONG)(x) >> 20) << 12) + \
 140              ((((ULONG)(x) >> 12) & 0xFF) << 2))
 141
 142 #define MiGetPdeAddress(x)         \
 143     (PMMPDE_HARDWARE)(PDE_BASE + \
 144              (((ULONG)(x) >> 20) << 2))
 145
 146 #define MiGetPdeOffset(x) (((ULONG)(x)) >> 22)
 147
 148 //
 149 // FIXME: THESE ARE WRONG ATM.
 150 //
 151 #define MiAddressToPde(x) \
 152 ((PMMPTE)(((((ULONG)(x)) >> 22) << 2) + PDE_BASE))
 153 #define MiAddressToPte(x) \
 154 ((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PTE_BASE))
 155 #define MiAddressToPteOffset(x) \
 156 ((((ULONG)(x)) << 10) >> 22)
 157
 158
 159 //
 160 // Convert a PTE into a corresponding address
 161 //
 162 #define MiPteToAddress(PTE) ((PVOID)((ULONG)(PTE) << 10))
 163
 164 #define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
 165 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
 166 #define ADDR_TO_PTE_OFFSET(v)  ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
 167
 168 //
 169 // FIXFIX: This is all wrong now!!!
 170 //
 171 typedef union _ARM_PTE
 172 {
 173     union
 174     {
 175         struct
 176         {
 177             ULONG Type:2;
 178             ULONG Unused:30;
 179         } Fault;
 180         struct
 181         {
 182             ULONG Type:2;
 183             ULONG Ignored:2;
 184             ULONG Reserved:1;
 185             ULONG Domain:4;
 186             ULONG Ignored1:1;
 187             ULONG BaseAddress:22;
 188         } Coarse;
 189         struct
 190         {
 191             ULONG Type:2;
 192             ULONG Buffered:1;
 193             ULONG Cached:1;
 194             ULONG Reserved:1;
 195             ULONG Domain:4;
 196             ULONG Ignored:1;
 197             ULONG Access:2;
 198             ULONG Ignored1:8;
 199             ULONG BaseAddress:12;
 200         } Section;
 201         struct
 202         {
 203             ULONG Type:2;
 204             ULONG Reserved:3;
 205             ULONG Domain:4;
 206             ULONG Ignored:3;
 207             ULONG BaseAddress:20;
 208         } Fine;
 209     } L1;
 210     union
 211     {
 212         struct
 213         {
 214             ULONG Type:2;
 215             ULONG Unused:30;
 216         } Fault;
 217         struct
 218         {
 219             ULONG Type:2;
 220             ULONG Buffered:1;
 221             ULONG Cached:1;
 222             ULONG Access0:2;
 223             ULONG Access1:2;
 224             ULONG Access2:2;
 225             ULONG Access3:2;
 226             ULONG Ignored:4;
 227             ULONG BaseAddress:16;
 228         } Large;
 229         struct
 230         {
 231             ULONG Type:2;
 232             ULONG Buffered:1;
 233             ULONG Cached:1;
 234             ULONG Access0:2;
 235             ULONG Access1:2;
 236             ULONG Access2:2;
 237             ULONG Access3:2;
 238             ULONG BaseAddress:20;
 239         } Small;
 240         struct
 241         {
 242             ULONG Type:2;
 243             ULONG Buffered:1;
 244             ULONG Cached:1;
 245             ULONG Access0:2;
 246             ULONG Ignored:4;
 247             ULONG BaseAddress:22;
 248         } Tiny;
 249     } L2;
 250     ULONG AsUlong;
 251 } ARM_PTE, *PARM_PTE;
 252
 253 typedef struct _ARM_TRANSLATION_TABLE
 254 {
 255     ARM_PTE Pte[4096];
 256 } ARM_TRANSLATION_TABLE, *PARM_TRANSLATION_TABLE;
 257
 258 typedef struct _ARM_COARSE_PAGE_TABLE
 259 {
 260     ARM_PTE Pte[256];
 261     ULONG Padding[768];
 262 } ARM_COARSE_PAGE_TABLE, *PARM_COARSE_PAGE_TABLE;
 263
 264 typedef enum _ARM_L1_PTE_TYPE
 265 {
 266     FaultPte,
 267     CoarsePte,
 268     SectionPte,
 269     FinePte
 270 } ARM_L1_PTE_TYPE;
 271
 272 typedef enum _ARM_L2_PTE_TYPE
 273 {
 274     LargePte = 1,
 275     SmallPte,
 276     TinyPte
 277 } ARM_L2_PTE_TYPE;
 278
 279 typedef enum _ARM_PTE_ACCESS
 280 {
 281     FaultAccess,
 282     SupervisorAccess,
 283     SharedAccess,
 284     UserAccess
 285 } ARM_PTE_ACCESS;
 286
 287 #endif
 288
 289 #endif