1 #ifndef __NTOSKRNL_INCLUDE_INTERNAL_ARM_MM_H
2 #define __NTOSKRNL_INCLUDE_INTERNAL_ARM_MM_H
5 // Number of bits corresponding to the area that a PDE entry represents (1MB)
8 #define PDE_SIZE (1 << PDE_SHIFT)
11 // Number of bits corresponding to the area that a coarse page table entry represents (4KB)
14 #define PTE_SIZE (1 << PTE_SHIFT)
17 // Number of bits corresponding to the area that a coarse page table occupies (1KB)
20 #define CPT_SIZE (1 << CPT_SHIFT)
25 #define PTE_BASE 0xC0000000
26 #define PTE_TOP 0xC03FFFFF
27 #define PDE_BASE 0xC0400000
28 #define HYPER_SPACE 0xC0404000
31 typedef struct _HARDWARE_PDE_ARMV6
33 ULONG Valid
:1; // Only for small pages
34 ULONG LargePage
:1; // Note, if large then Valid = 0
40 ULONG PageFrameNumber
:22;
41 } HARDWARE_PDE_ARMV6
, *PHARDWARE_PDE_ARMV6
;
43 typedef struct _HARDWARE_LARGE_PTE_ARMV6
45 ULONG Valid
:1; // Only for small pages
46 ULONG LargePage
:1; // Note, if large then Valid = 0
54 ULONG CacheAttributes
:3;
58 ULONG SuperLagePage
:1;
60 ULONG PageFrameNumber
:12;
61 } HARDWARE_LARGE_PTE_ARMV6
, *PHARDWARE_LARGE_PTE_ARMV6
;
63 typedef struct _HARDWARE_PTE_ARMV6
71 ULONG CacheAttributes
:3;
75 ULONG PageFrameNumber
:20;
76 } HARDWARE_PTE_ARMV6
, *PHARDWARE_PTE_ARMV6
;
78 C_ASSERT(sizeof(HARDWARE_PDE_ARMV6
) == sizeof(ULONG
));
79 C_ASSERT(sizeof(HARDWARE_LARGE_PTE_ARMV6
) == sizeof(ULONG
));
80 C_ASSERT(sizeof(HARDWARE_PTE_ARMV6
) == sizeof(ULONG
));
84 typedef struct _PAGE_TABLE_ARM
86 HARDWARE_PTE_ARMV6 Pte
[1024];
87 } PAGE_TABLE_ARM
, *PPAGE_TABLE_ARM
;
89 typedef struct _PAGE_DIRECTORY_ARM
93 HARDWARE_PDE_ARMV6 Pde
[4096];
94 HARDWARE_LARGE_PTE_ARMV6 Pte
[4096];
96 } PAGE_DIRECTORY_ARM
, *PPAGE_DIRECTORY_ARM
;
98 C_ASSERT(sizeof(PAGE_TABLE_ARM
) == PAGE_SIZE
);
99 C_ASSERT(sizeof(PAGE_DIRECTORY_ARM
) == (4 * PAGE_SIZE
));
101 typedef enum _ARM_DOMAIN
110 PULONG
MmGetPageDirectory(VOID
);
112 #define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.NonGlobal = 1)
113 #define MI_MAKE_DIRTY_PAGE(x)
114 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
115 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.ReadOnly = 0)
116 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.Cached = 0)
117 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.Buffered = 0)
118 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.Buffered = 1)
119 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.ReadOnly == 0)
120 #define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE
121 #define MI_IS_PAGE_DIRTY(x) TRUE
123 /* Easy accessing PFN in PTE */
124 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
130 // FIXFIX: This is all wrong now!!!
134 // Take 0x80812345 and extract:
135 // PTE_BASE[0x808][0x12]
137 #define MiGetPteAddress(x) \
138 (PMMPTE)(PTE_BASE + \
139 (((ULONG)(x) >> 20) << 12) + \
140 ((((ULONG)(x) >> 12) & 0xFF) << 2))
142 #define MiGetPdeAddress(x) \
143 (PMMPDE_HARDWARE)(PDE_BASE + \
144 (((ULONG)(x) >> 20) << 2))
146 #define MiGetPdeOffset(x) (((ULONG)(x)) >> 22)
149 // FIXME: THESE ARE WRONG ATM.
151 #define MiAddressToPde(x) \
152 ((PMMPTE)(((((ULONG)(x)) >> 22) << 2) + PDE_BASE))
153 #define MiAddressToPte(x) \
154 ((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PTE_BASE))
155 #define MiAddressToPteOffset(x) \
156 ((((ULONG)(x)) << 10) >> 22)
160 // Convert a PTE into a corresponding address
162 #define MiPteToAddress(PTE) ((PVOID)((ULONG)(PTE) << 10))
164 #define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
165 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
166 #define ADDR_TO_PTE_OFFSET(v) ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
169 // FIXFIX: This is all wrong now!!!
171 typedef union _ARM_PTE
187 ULONG BaseAddress
:22;
199 ULONG BaseAddress
:12;
207 ULONG BaseAddress
:20;
227 ULONG BaseAddress
:16;
238 ULONG BaseAddress
:20;
247 ULONG BaseAddress
:22;
251 } ARM_PTE
, *PARM_PTE
;
253 typedef struct _ARM_TRANSLATION_TABLE
256 } ARM_TRANSLATION_TABLE
, *PARM_TRANSLATION_TABLE
;
258 typedef struct _ARM_COARSE_PAGE_TABLE
262 } ARM_COARSE_PAGE_TABLE
, *PARM_COARSE_PAGE_TABLE
;
264 typedef enum _ARM_L1_PTE_TYPE
272 typedef enum _ARM_L2_PTE_TYPE
279 typedef enum _ARM_PTE_ACCESS