2 * Lowlevel memory managment definitions
8 PULONG
MmGetPageDirectory(VOID
);
10 #define PAGE_MASK(x) ((x)&(~0xfff))
11 #define PAE_PAGE_MASK(x) ((x)&(~0xfffLL))
13 /* Base addresses of PTE and PDE */
14 #define PAGETABLE_MAP (0xc0000000)
15 #define PAGEDIRECTORY_MAP (0xc0000000 + (PAGETABLE_MAP / (1024)))
17 #define PTE_BASE 0xC0000000
18 #define PDE_BASE 0xC0300000
19 #define PTE_TOP 0xC03FFFFF
20 #define HYPER_SPACE 0xC0400000
22 /* Converting address to a corresponding PDE or PTE entry */
23 #define MiAddressToPde(x) \
24 ((PMMPTE)(((((ULONG)(x)) >> 22) << 2) + PAGEDIRECTORY_MAP))
25 #define MiAddressToPte(x) \
26 ((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PAGETABLE_MAP))
27 #define MiAddressToPteOffset(x) \
28 ((((ULONG)(x)) << 10) >> 22)
31 // Convert a PTE into a corresponding address
33 #define MiPteToAddress(PTE) ((PVOID)((ULONG)(PTE) << 10))
35 #define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
36 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
37 #define ADDR_TO_PTE_OFFSET(v) ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
39 /* Easy accessing PFN in PTE */
40 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
42 #define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
43 #define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
44 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
45 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
46 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
47 #if !defined(CONFIG_SMP)
48 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
50 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
52 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
53 #define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
54 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
55 #if !defined(CONFIG_SMP)
56 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
58 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
61 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
64 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
65 ((((x)) % (4*1024*1024)) / (4*1024))
67 #define NR_SECTION_PAGE_TABLES 1024
68 #define NR_SECTION_PAGE_ENTRIES 1024
70 #define TEB_BASE 0x7FFDE000
72 #define MI_HYPERSPACE_PTES (256 - 1)
73 #define MI_ZERO_PTES (32)
74 #define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
75 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
76 MI_HYPERSPACE_PTES * PAGE_SIZE)
77 #define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
80 /* On x86, these two are the same */
85 * FIXME - different architectures have different cache line sizes...
87 #define MM_CACHE_LINE_SIZE 32