reactos/ntoskrnl/include/internal/i386/mm.h

   1 /*
   2  * Lowlevel memory managment definitions
   3  */
   4
   5 #pragma once
   6
   7 struct _EPROCESS;
   8 PULONG MmGetPageDirectory(VOID);
   9
  10 #ifdef _PAE_
  11 #define _MI_PAGING_LEVELS 3
  12 #else
  13 #define _MI_PAGING_LEVELS 2
  14 #endif
  15
  16 #define PAGE_MASK(x)            ((x)&(~0xfff))
  17 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  18
  19 /* Base addresses of PTE and PDE */
  20 #define PAGETABLE_MAP       (0xc0000000)
  21 #define PAGEDIRECTORY_MAP   (0xc0000000 + (PAGETABLE_MAP / (1024)))
  22
  23 /* FIXME: These are different for PAE */
  24 #define PTE_BASE    0xC0000000
  25 #define PDE_BASE    0xC0300000
  26 #define PDE_TOP     0xC0300FFF
  27 #define PTE_TOP     0xC03FFFFF
  28 #define HYPER_SPACE 0xC0400000
  29
  30 /* Converting address to a corresponding PDE or PTE entry */
  31 #define MiAddressToPde(x) \
  32     ((PMMPTE)(((((ULONG)(x)) >> 22) << 2) + PAGEDIRECTORY_MAP))
  33 #define MiAddressToPte(x) \
  34     ((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PAGETABLE_MAP))
  35 #define MiAddressToPteOffset(x) \
  36     ((((ULONG)(x)) << 10) >> 22)
  37
  38 //
  39 // Convert a PTE into a corresponding address
  40 //
  41 #define MiPteToAddress(PTE) ((PVOID)((ULONG)(PTE) << 10))
  42 #define MiPdeToAddress(PDE) ((PVOID)((ULONG)(PDE) << 10))
  43
  44 #define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
  45 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
  46 #define ADDR_TO_PTE_OFFSET(v)  ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
  47
  48 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
  49
  50 /* Easy accessing PFN in PTE */
  51 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
  52
  53 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
  54 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
  55 #define MI_MAKE_ACCESSED_PAGE(x)   ((x)->u.Hard.Accessed = 1)
  56 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
  57 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
  58 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
  59 #define MI_IS_PAGE_LARGE(x)        ((x)->u.Hard.LargePage == 1)
  60 #if !defined(CONFIG_SMP)
  61 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
  62 #else
  63 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Writable == 1)
  64 #endif
  65 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
  66 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
  67 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
  68 #if !defined(CONFIG_SMP)
  69 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
  70 #else
  71 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Writable = 1)
  72 #endif
  73
  74 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
  75     ((x) / (4*1024*1024))
  76
  77 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
  78     ((((x)) % (4*1024*1024)) / (4*1024))
  79
  80 #define NR_SECTION_PAGE_TABLES              1024
  81 #define NR_SECTION_PAGE_ENTRIES             1024
  82
  83 #define TEB_BASE                            0x7FFDE000
  84
  85 #define MI_HYPERSPACE_PTES                  (256 - 1)
  86 #define MI_ZERO_PTES                        (32)
  87 #define MI_MAPPING_RANGE_START              (ULONG)HYPER_SPACE
  88 #define MI_MAPPING_RANGE_END                (MI_MAPPING_RANGE_START + \
  89                                                       MI_HYPERSPACE_PTES * PAGE_SIZE)
  90 #define MI_DUMMY_PTE                        (PMMPTE)(MI_MAPPING_RANGE_END + \
  91                                                       PAGE_SIZE)
  92 #define MI_VAD_BITMAP                       (PMMPTE)(MI_DUMMY_PTE + \
  93                                                       PAGE_SIZE)
  94 #define MI_WORKING_SET_LIST                 (PMMPTE)(MI_VAD_BITMAP + \
  95                                                       PAGE_SIZE)
  96
  97 /* On x86, these two are the same */
  98 #define MMPDE MMPTE
  99 #define PMMPDE PMMPTE
 100
 101 /*
 102 * FIXME - different architectures have different cache line sizes...
 103 */
 104 #define MM_CACHE_LINE_SIZE                  32