2 * PROJECT: ReactOS Kernel
3 * LICENSE: GPL - See COPYING in the top level directory
4 * FILE: ntoskrnl/ke/i386/cpu.c
5 * PURPOSE: Routines for CPU-level support
6 * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
9 /* INCLUDES *****************************************************************/
15 /* GLOBALS *******************************************************************/
20 /* The TSS to use for Double Fault Traps (INT 0x9) */
21 UCHAR KiDoubleFaultTSS
[KTSS_IO_MAPS
];
23 /* The TSS to use for NMI Fault Traps (INT 0x2) */
24 UCHAR KiNMITSS
[KTSS_IO_MAPS
];
27 KGDTENTRY KiBootGdt
[256] =
29 {0x0000, 0x0000, {{0x00, 0x00, 0x00, 0x00}}}, /* KGDT_NULL */
30 {0xffff, 0x0000, {{0x00, 0x9b, 0xcf, 0x00}}}, /* KGDT_R0_CODE */
31 {0xffff, 0x0000, {{0x00, 0x93, 0xcf, 0x00}}}, /* KGDT_R0_DATA */
32 {0xffff, 0x0000, {{0x00, 0xfb, 0xcf, 0x00}}}, /* KGDT_R3_CODE */
33 {0xffff, 0x0000, {{0x00, 0xf3, 0xcf, 0x00}}}, /* KGDT_R3_DATA*/
34 {0x0000, 0x0000, {{0x00, 0x00, 0x00, 0x00}}}, /* KGDT_TSS */
35 {0x0001, 0xf000, {{0xdf, 0x93, 0xc0, 0xff}}}, /* KGDT_R0_PCR */
36 {0x0fff, 0x0000, {{0x00, 0xf3, 0x40, 0x00}}}, /* KGDT_R3_TEB */
37 {0x0000, 0x0000, {{0x00, 0x00, 0x00, 0x00}}}, /* KGDT_UNUSED */
38 {0x0000, 0x0000, {{0x00, 0x00, 0x00, 0x00}}}, /* KGDT_LDT */
39 {0x0000, 0x0000, {{0x00, 0x00, 0x00, 0x00}}}, /* KGDT_DF_TSS */
40 {0x0000, 0x0000, {{0x00, 0x00, 0x00, 0x00}}} /* KGDT_NMI_TSS */
44 KDESCRIPTOR KiGdtDescriptor
= {0, sizeof(KiBootGdt
) - 1, (ULONG
)KiBootGdt
};
46 /* CPU Features and Flags */
49 ULONG KeProcessorArchitecture
;
50 ULONG KeProcessorLevel
;
51 ULONG KeProcessorRevision
;
53 ULONG KiFastSystemCallDisable
= 1;
54 ULONG KeI386NpxPresent
= 0;
55 ULONG KiMXCsrMask
= 0;
56 ULONG MxcsrFeatureMask
= 0;
57 ULONG KeI386XMMIPresent
= 0;
58 ULONG KeI386FxsrPresent
= 0;
59 ULONG KeI386MachineType
;
60 ULONG Ke386Pae
= FALSE
;
61 ULONG Ke386NoExecute
= FALSE
;
62 ULONG KeLargestCacheLine
= 0x40;
63 ULONG KeDcacheFlushCount
= 0;
64 ULONG KeIcacheFlushCount
= 0;
65 ULONG KiDmaIoCoherency
= 0;
66 CHAR KeNumberProcessors
;
67 KAFFINITY KeActiveProcessors
= 1;
68 BOOLEAN KiI386PentiumLockErrataPresent
;
69 BOOLEAN KiSMTProcessorsPresent
;
76 volatile LONG KiTbFlushTimeStamp
;
79 static const CHAR CmpIntelID
[] = "GenuineIntel";
80 static const CHAR CmpAmdID
[] = "AuthenticAMD";
81 static const CHAR CmpCyrixID
[] = "CyrixInstead";
82 static const CHAR CmpTransmetaID
[] = "GenuineTMx86";
83 static const CHAR CmpCentaurID
[] = "CentaurHauls";
84 static const CHAR CmpRiseID
[] = "RiseRiseRise";
86 /* SUPPORT ROUTINES FOR MSVC COMPATIBILITY ***********************************/
90 CPUID(OUT ULONG CpuInfo
[4],
93 Ki386Cpuid(InfoType
, &CpuInfo
[0], &CpuInfo
[1], &CpuInfo
[2], &CpuInfo
[3]);
97 WRMSR(IN ULONG Register
,
100 LARGE_INTEGER LargeVal
;
101 LargeVal
.QuadPart
= Value
;
102 Ke386Wrmsr(Register
, LargeVal
.HighPart
, LargeVal
.LowPart
);
106 RDMSR(IN ULONG Register
)
108 LARGE_INTEGER LargeVal
= {{0, 0}};
109 Ke386Rdmsr(Register
, LargeVal
.HighPart
, LargeVal
.LowPart
);
110 return LargeVal
.QuadPart
;
113 /* FUNCTIONS *****************************************************************/
117 KiSetProcessorType(VOID
)
119 ULONG EFlags
= 0, NewEFlags
;
121 ULONG Stepping
, Type
;
123 /* Start by assuming no CPUID data */
124 KeGetCurrentPrcb()->CpuID
= 0;
127 Ke386SaveFlags(EFlags
);
129 /* XOR out the ID bit and update EFlags */
130 NewEFlags
= EFlags
^ EFLAGS_ID
;
131 Ke386RestoreFlags(NewEFlags
);
133 /* Get them back and see if they were modified */
134 Ke386SaveFlags(NewEFlags
);
135 if (NewEFlags
!= EFlags
)
137 /* The modification worked, so CPUID exists. Set the ID Bit again. */
139 Ke386RestoreFlags(EFlags
);
141 /* Peform CPUID 0 to see if CPUID 1 is supported */
149 * Get the Stepping and Type. The stepping contains both the
150 * Model and the Step, while the Type contains the returned Type.
151 * We ignore the family.
153 * For the stepping, we convert this: zzzzzzxy into this: x0y
155 Stepping
= Reg
[0] & 0xF0;
157 Stepping
+= (Reg
[0] & 0xFF);
159 Type
= Reg
[0] & 0xF00;
162 /* Save them in the PRCB */
163 KeGetCurrentPrcb()->CpuID
= TRUE
;
164 KeGetCurrentPrcb()->CpuType
= (UCHAR
)Type
;
165 KeGetCurrentPrcb()->CpuStep
= (USHORT
)Stepping
;
169 DPRINT1("CPUID Support lacking\n");
174 DPRINT1("CPUID Support lacking\n");
178 Ke386RestoreFlags(EFlags
);
185 PKPRCB Prcb
= KeGetCurrentPrcb();
189 /* Assume no Vendor ID and fail if no CPUID Support. */
190 Prcb
->VendorString
[0] = 0;
191 if (!Prcb
->CpuID
) return 0;
193 /* Get the Vendor ID and null-terminate it */
197 /* Re-arrange vendor string */
199 Vendor
[2] = Vendor
[3];
202 /* Copy it to the PRCB and null-terminate it again */
203 RtlCopyMemory(Prcb
->VendorString
,
205 sizeof(Prcb
->VendorString
) - sizeof(CHAR
));
206 Prcb
->VendorString
[sizeof(Prcb
->VendorString
) - sizeof(CHAR
)] = ANSI_NULL
;
208 /* Now check the CPU Type */
209 if (!strcmp((PCHAR
)Prcb
->VendorString
, CmpIntelID
))
213 else if (!strcmp((PCHAR
)Prcb
->VendorString
, CmpAmdID
))
217 else if (!strcmp((PCHAR
)Prcb
->VendorString
, CmpCyrixID
))
219 DPRINT1("Cyrix CPU support not fully tested!\n");
222 else if (!strcmp((PCHAR
)Prcb
->VendorString
, CmpTransmetaID
))
224 DPRINT1("Transmeta CPU support not fully tested!\n");
225 return CPU_TRANSMETA
;
227 else if (!strcmp((PCHAR
)Prcb
->VendorString
, CmpCentaurID
))
229 DPRINT1("Centaur CPU support not fully tested!\n");
232 else if (!strcmp((PCHAR
)Prcb
->VendorString
, CmpRiseID
))
234 DPRINT1("Rise CPU support not fully tested!\n");
244 KiGetFeatureBits(VOID
)
246 PKPRCB Prcb
= KeGetCurrentPrcb();
248 ULONG FeatureBits
= KF_WORKING_PTE
;
250 BOOLEAN ExtendedCPUID
= TRUE
;
251 ULONG CpuFeatures
= 0;
253 /* Get the Vendor ID */
254 Vendor
= KiGetCpuVendor();
256 /* Make sure we got a valid vendor ID at least. */
257 if (!Vendor
) return FeatureBits
;
259 /* Get the CPUID Info. Features are in Reg[3]. */
262 /* Set the initial APIC ID */
263 Prcb
->InitialApicId
= (UCHAR
)(Reg
[1] >> 24);
269 /* Check if it's a P6 */
270 if (Prcb
->CpuType
== 6)
272 /* Perform the special sequence to get the MicroCode Signature */
275 Prcb
->UpdateSignature
.QuadPart
= RDMSR(0x8B);
277 else if (Prcb
->CpuType
== 5)
279 /* On P5, enable workaround for the LOCK errata. */
280 KiI386PentiumLockErrataPresent
= TRUE
;
283 /* Check for broken P6 with bad SMP PTE implementation */
284 if (((Reg
[0] & 0x0FF0) == 0x0610 && (Reg
[0] & 0x000F) <= 0x9) ||
285 ((Reg
[0] & 0x0FF0) == 0x0630 && (Reg
[0] & 0x000F) <= 0x4))
287 /* Remove support for correct PTE support. */
288 FeatureBits
&= ~KF_WORKING_PTE
;
291 /* Check if the CPU is too old to support SYSENTER */
292 if ((Prcb
->CpuType
< 6) ||
293 ((Prcb
->CpuType
== 6) && (Prcb
->CpuStep
< 0x0303)))
299 /* Set the current features */
300 CpuFeatures
= Reg
[3];
307 /* Check if this is a K5 or K6. (family 5) */
308 if ((Reg
[0] & 0x0F00) == 0x0500)
310 /* Get the Model Number */
311 switch (Reg
[0] & 0x00F0)
313 /* Model 1: K5 - 5k86 (initial models) */
316 /* Check if this is Step 0 or 1. They don't support PGE */
317 if ((Reg
[0] & 0x000F) > 0x03) break;
319 /* Model 0: K5 - SSA5 */
322 /* Model 0 doesn't support PGE at all. */
329 /* K6-2, Step 8 and over have support for MTRR. */
330 if ((Reg
[0] & 0x000F) >= 0x8) FeatureBits
|= KF_AMDK6MTRR
;
334 Model D: K6-2+, K6-III+ */
338 FeatureBits
|= KF_AMDK6MTRR
;
342 else if((Reg
[0] & 0x0F00) < 0x0500)
344 /* Families below 5 don't support PGE, PSE or CMOV at all */
345 Reg
[3] &= ~(0x08 | 0x2000 | 0x8000);
347 /* They also don't support advanced CPUID functions. */
348 ExtendedCPUID
= FALSE
;
351 /* Set the current features */
352 CpuFeatures
= Reg
[3];
362 /* Enable CMPXCHG8B if the family (>= 5), model and stepping (>= 4.2) support it */
363 if ((Reg
[0] & 0x0FFF) >= 0x0542)
365 WRMSR(0x80860004, RDMSR(0x80860004) | 0x0100);
366 FeatureBits
|= KF_CMPXCHG8B
;
371 /* Centaur, IDT, Rise and VIA CPUs */
374 /* These CPUs don't report the presence of CMPXCHG8B through CPUID.
375 However, this feature exists and operates properly without any additional steps. */
376 FeatureBits
|= KF_CMPXCHG8B
;
381 /* Convert all CPUID Feature bits into our format */
382 if (CpuFeatures
& 0x00000002) FeatureBits
|= KF_V86_VIS
| KF_CR4
;
383 if (CpuFeatures
& 0x00000008) FeatureBits
|= KF_LARGE_PAGE
| KF_CR4
;
384 if (CpuFeatures
& 0x00000010) FeatureBits
|= KF_RDTSC
;
385 if (CpuFeatures
& 0x00000100) FeatureBits
|= KF_CMPXCHG8B
;
386 if (CpuFeatures
& 0x00000800) FeatureBits
|= KF_FAST_SYSCALL
;
387 if (CpuFeatures
& 0x00001000) FeatureBits
|= KF_MTRR
;
388 if (CpuFeatures
& 0x00002000) FeatureBits
|= KF_GLOBAL_PAGE
| KF_CR4
;
389 if (CpuFeatures
& 0x00008000) FeatureBits
|= KF_CMOV
;
390 if (CpuFeatures
& 0x00010000) FeatureBits
|= KF_PAT
;
391 if (CpuFeatures
& 0x00200000) FeatureBits
|= KF_DTS
;
392 if (CpuFeatures
& 0x00800000) FeatureBits
|= KF_MMX
;
393 if (CpuFeatures
& 0x01000000) FeatureBits
|= KF_FXSR
;
394 if (CpuFeatures
& 0x02000000) FeatureBits
|= KF_XMMI
;
395 if (CpuFeatures
& 0x04000000) FeatureBits
|= KF_XMMI64
;
397 /* Check if the CPU has hyper-threading */
398 if (CpuFeatures
& 0x10000000)
400 /* Set the number of logical CPUs */
401 Prcb
->LogicalProcessorsPerPhysicalProcessor
= (UCHAR
)(Reg
[1] >> 16);
402 if (Prcb
->LogicalProcessorsPerPhysicalProcessor
> 1)
404 /* We're on dual-core */
405 KiSMTProcessorsPresent
= TRUE
;
410 /* We only have a single CPU */
411 Prcb
->LogicalProcessorsPerPhysicalProcessor
= 1;
414 /* Check if CPUID 0x80000000 is supported */
418 CPUID(Reg
, 0x80000000);
419 if ((Reg
[0] & 0xffffff00) == 0x80000000)
421 /* Check if CPUID 0x80000001 is supported */
422 if (Reg
[0] >= 0x80000001)
424 /* Check which extended features are available. */
425 CPUID(Reg
, 0x80000001);
427 /* Check if NX-bit is supported */
428 if (Reg
[3] & 0x00100000) FeatureBits
|= KF_NX_BIT
;
430 /* Now handle each features for each CPU Vendor */
435 if (Reg
[3] & 0x80000000) FeatureBits
|= KF_3DNOW
;
442 /* Return the Feature Bits */
448 KiGetCacheInformation(VOID
)
450 PKIPCR Pcr
= (PKIPCR
)KeGetPcr();
453 ULONG CacheRequests
= 0, i
;
454 ULONG CurrentRegister
;
456 BOOLEAN FirstPass
= TRUE
;
458 /* Set default L2 size */
459 Pcr
->SecondLevelCacheSize
= 0;
461 /* Get the Vendor ID and make sure we support CPUID */
462 Vendor
= KiGetCpuVendor();
465 /* Check the Vendor ID */
468 /* Handle Intel case */
471 /*Check if we support CPUID 2 */
475 /* We need to loop for the number of times CPUID will tell us to */
478 /* Do the CPUID call */
481 /* Check if it was the first call */
485 * The number of times to loop is the first byte. Read
486 * it and then destroy it so we don't get confused.
488 CacheRequests
= Data
[0] & 0xFF;
489 Data
[0] &= 0xFFFFFF00;
491 /* Don't go over this again */
495 /* Loop all 4 registers */
496 for (i
= 0; i
< 4; i
++)
498 /* Get the current register */
499 CurrentRegister
= Data
[i
];
502 * If the upper bit is set, then this register should
505 if (CurrentRegister
& 0x80000000) continue;
507 /* Keep looping for every byte inside this register */
508 while (CurrentRegister
)
510 /* Read a byte, skip a byte. */
511 RegisterByte
= (UCHAR
)(CurrentRegister
& 0xFF);
512 CurrentRegister
>>= 8;
513 if (!RegisterByte
) continue;
516 * Valid values are from 0x40 (0 bytes) to 0x49
517 * (32MB), or from 0x80 to 0x89 (same size but
520 if (((RegisterByte
> 0x40) &&
521 (RegisterByte
<= 0x49)) ||
522 ((RegisterByte
> 0x80) &&
523 (RegisterByte
<= 0x89)))
525 /* Mask out only the first nibble */
526 RegisterByte
&= 0x0F;
528 /* Set the L2 Cache Size */
529 Pcr
->SecondLevelCacheSize
= 0x10000 <<
534 } while (--CacheRequests
);
540 /* Check if we support CPUID 0x80000006 */
541 CPUID(Data
, 0x80000000);
544 /* Get 2nd level cache and tlb size */
545 CPUID(Data
, 0x80000006);
547 /* Set the L2 Cache Size */
548 Pcr
->SecondLevelCacheSize
= (Data
[2] & 0xFFFF0000) >> 6;
560 /* Save current CR0 */
563 /* If this is a 486, enable Write-Protection */
564 if (KeGetCurrentPrcb()->CpuType
> 3) Cr0
|= CR0_WP
;
572 KiInitializeTSS2(IN PKTSS Tss
,
573 IN PKGDTENTRY TssEntry OPTIONAL
)
577 /* Make sure the GDT Entry is valid */
581 TssEntry
->LimitLow
= sizeof(KTSS
) - 1;
582 TssEntry
->HighWord
.Bits
.LimitHi
= 0;
585 /* Now clear the I/O Map */
586 RtlFillMemory(Tss
->IoMaps
[0].IoMap
, 8096, -1);
588 /* Initialize Interrupt Direction Maps */
589 p
= (PUCHAR
)(Tss
->IoMaps
[0].DirectionMap
);
590 RtlZeroMemory(p
, 32);
592 /* Add DPMI support for interrupts */
597 /* Initialize the default Interrupt Direction Map */
598 p
= Tss
->IntDirectionMap
;
599 RtlZeroMemory(Tss
->IntDirectionMap
, 32);
601 /* Add DPMI support */
609 KiInitializeTSS(IN PKTSS Tss
)
611 /* Set an invalid map base */
612 Tss
->IoMapBase
= KiComputeIopmOffset(IO_ACCESS_MAP_NONE
);
614 /* Disable traps during Task Switches */
617 /* Set LDT and Ring 0 SS */
619 Tss
->Ss0
= KGDT_R0_DATA
;
624 Ki386InitializeTss(IN PKTSS Tss
,
628 PKGDTENTRY TssEntry
, TaskGateEntry
;
630 /* Initialize the boot TSS. */
631 TssEntry
= &Gdt
[KGDT_TSS
/ sizeof(KGDTENTRY
)];
632 TssEntry
->HighWord
.Bits
.Type
= I386_TSS
;
633 TssEntry
->HighWord
.Bits
.Pres
= 1;
634 TssEntry
->HighWord
.Bits
.Dpl
= 0;
635 KiInitializeTSS2(Tss
, TssEntry
);
636 KiInitializeTSS(Tss
);
638 /* Load the task register */
639 Ke386SetTr(KGDT_TSS
);
641 /* Setup the Task Gate for Double Fault Traps */
642 TaskGateEntry
= (PKGDTENTRY
)&Idt
[8];
643 TaskGateEntry
->HighWord
.Bits
.Type
= I386_TASK_GATE
;
644 TaskGateEntry
->HighWord
.Bits
.Pres
= 1;
645 TaskGateEntry
->HighWord
.Bits
.Dpl
= 0;
646 ((PKIDTENTRY
)TaskGateEntry
)->Selector
= KGDT_DF_TSS
;
648 /* Initialize the TSS used for handling double faults. */
649 Tss
= (PKTSS
)KiDoubleFaultTSS
;
650 KiInitializeTSS(Tss
);
651 Tss
->CR3
= __readcr3();
652 Tss
->Esp0
= PtrToUlong(KiDoubleFaultStack
);
653 Tss
->Eip
= PtrToUlong(KiTrap8
);
654 Tss
->Cs
= KGDT_R0_CODE
;
655 Tss
->Fs
= KGDT_R0_PCR
;
656 Tss
->Ss
= Ke386GetSs();
657 Tss
->Es
= KGDT_R3_DATA
| RPL_MASK
;
658 Tss
->Ds
= KGDT_R3_DATA
| RPL_MASK
;
660 /* Setup the Double Trap TSS entry in the GDT */
661 TssEntry
= &Gdt
[KGDT_DF_TSS
/ sizeof(KGDTENTRY
)];
662 TssEntry
->HighWord
.Bits
.Type
= I386_TSS
;
663 TssEntry
->HighWord
.Bits
.Pres
= 1;
664 TssEntry
->HighWord
.Bits
.Dpl
= 0;
665 TssEntry
->BaseLow
= (USHORT
)((ULONG_PTR
)Tss
& 0xFFFF);
666 TssEntry
->HighWord
.Bytes
.BaseMid
= (UCHAR
)((ULONG_PTR
)Tss
>> 16);
667 TssEntry
->HighWord
.Bytes
.BaseHi
= (UCHAR
)((ULONG_PTR
)Tss
>> 24);
668 TssEntry
->LimitLow
= KTSS_IO_MAPS
;
670 /* Now setup the NMI Task Gate */
671 TaskGateEntry
= (PKGDTENTRY
)&Idt
[2];
672 TaskGateEntry
->HighWord
.Bits
.Type
= I386_TASK_GATE
;
673 TaskGateEntry
->HighWord
.Bits
.Pres
= 1;
674 TaskGateEntry
->HighWord
.Bits
.Dpl
= 0;
675 ((PKIDTENTRY
)TaskGateEntry
)->Selector
= KGDT_NMI_TSS
;
677 /* Initialize the actual TSS */
678 Tss
= (PKTSS
)KiNMITSS
;
679 KiInitializeTSS(Tss
);
680 Tss
->CR3
= __readcr3();
681 Tss
->Esp0
= PtrToUlong(KiDoubleFaultStack
);
682 Tss
->Eip
= PtrToUlong(KiTrap2
);
683 Tss
->Cs
= KGDT_R0_CODE
;
684 Tss
->Fs
= KGDT_R0_PCR
;
685 Tss
->Ss
= Ke386GetSs();
686 Tss
->Es
= KGDT_R3_DATA
| RPL_MASK
;
687 Tss
->Ds
= KGDT_R3_DATA
| RPL_MASK
;
689 /* And its associated TSS Entry */
690 TssEntry
= &Gdt
[KGDT_NMI_TSS
/ sizeof(KGDTENTRY
)];
691 TssEntry
->HighWord
.Bits
.Type
= I386_TSS
;
692 TssEntry
->HighWord
.Bits
.Pres
= 1;
693 TssEntry
->HighWord
.Bits
.Dpl
= 0;
694 TssEntry
->BaseLow
= (USHORT
)((ULONG_PTR
)Tss
& 0xFFFF);
695 TssEntry
->HighWord
.Bytes
.BaseMid
= (UCHAR
)((ULONG_PTR
)Tss
>> 16);
696 TssEntry
->HighWord
.Bytes
.BaseHi
= (UCHAR
)((ULONG_PTR
)Tss
>> 24);
697 TssEntry
->LimitLow
= KTSS_IO_MAPS
;
702 KeFlushCurrentTb(VOID
)
704 /* Flush the TLB by resetting CR3 */
705 __writecr3(__readcr3());
710 KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState
)
712 /* Restore the CR registers */
713 __writecr0(ProcessorState
->SpecialRegisters
.Cr0
);
714 Ke386SetCr2(ProcessorState
->SpecialRegisters
.Cr2
);
715 __writecr3(ProcessorState
->SpecialRegisters
.Cr3
);
716 if (KeFeatureBits
& KF_CR4
) __writecr4(ProcessorState
->SpecialRegisters
.Cr4
);
719 // Restore the DR registers
721 Ke386SetDr0(ProcessorState
->SpecialRegisters
.KernelDr0
);
722 Ke386SetDr1(ProcessorState
->SpecialRegisters
.KernelDr1
);
723 Ke386SetDr2(ProcessorState
->SpecialRegisters
.KernelDr2
);
724 Ke386SetDr3(ProcessorState
->SpecialRegisters
.KernelDr3
);
725 Ke386SetDr6(ProcessorState
->SpecialRegisters
.KernelDr6
);
726 Ke386SetDr7(ProcessorState
->SpecialRegisters
.KernelDr7
);
729 // Restore GDT, IDT, LDT and TSS
731 Ke386SetGlobalDescriptorTable(*(PKDESCRIPTOR
)&ProcessorState
->SpecialRegisters
.Gdtr
.Limit
);
732 Ke386SetInterruptDescriptorTable(*(PKDESCRIPTOR
)&ProcessorState
->SpecialRegisters
.Idtr
.Limit
);
733 Ke386SetTr(ProcessorState
->SpecialRegisters
.Tr
);
734 Ke386SetLocalDescriptorTable(ProcessorState
->SpecialRegisters
.Ldtr
);
739 KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState
)
741 /* Save the CR registers */
742 ProcessorState
->SpecialRegisters
.Cr0
= __readcr0();
743 ProcessorState
->SpecialRegisters
.Cr2
= __readcr2();
744 ProcessorState
->SpecialRegisters
.Cr3
= __readcr3();
745 ProcessorState
->SpecialRegisters
.Cr4
= (KeFeatureBits
& KF_CR4
) ?
748 /* Save the DR registers */
749 ProcessorState
->SpecialRegisters
.KernelDr0
= Ke386GetDr0();
750 ProcessorState
->SpecialRegisters
.KernelDr1
= Ke386GetDr1();
751 ProcessorState
->SpecialRegisters
.KernelDr2
= Ke386GetDr2();
752 ProcessorState
->SpecialRegisters
.KernelDr3
= Ke386GetDr3();
753 ProcessorState
->SpecialRegisters
.KernelDr6
= Ke386GetDr6();
754 ProcessorState
->SpecialRegisters
.KernelDr7
= Ke386GetDr7();
757 /* Save GDT, IDT, LDT and TSS */
758 Ke386GetGlobalDescriptorTable(*(PKDESCRIPTOR
)&ProcessorState
->SpecialRegisters
.Gdtr
.Limit
);
759 Ke386GetInterruptDescriptorTable(*(PKDESCRIPTOR
)&ProcessorState
->SpecialRegisters
.Idtr
.Limit
);
760 Ke386GetTr(ProcessorState
->SpecialRegisters
.Tr
);
761 Ke386GetLocalDescriptorTable(ProcessorState
->SpecialRegisters
.Ldtr
);
766 KiInitializeMachineType(VOID
)
768 /* Set the Machine Type we got from NTLDR */
769 KeI386MachineType
= KeLoaderBlock
->u
.I386
.MachineType
& 0x000FF;
774 KiLoadFastSyscallMachineSpecificRegisters(IN ULONG_PTR Context
)
777 Ke386Wrmsr(0x174, KGDT_R0_CODE
, 0);
778 Ke386Wrmsr(0x175, (ULONG
)KeGetCurrentPrcb()->DpcStack
, 0);
781 Ke386Wrmsr(0x176, (ULONG
)KiFastCallEntry
, 0);
787 KiRestoreFastSyscallReturnState(VOID
)
789 /* FIXME: NT has support for SYSCALL, IA64-SYSENTER, etc. */
791 /* Check if the CPU Supports fast system call */
792 if (KeFeatureBits
& KF_FAST_SYSCALL
)
794 /* Do an IPI to enable it */
795 KeIpiGenericCall(KiLoadFastSyscallMachineSpecificRegisters
, 0);
801 Ki386EnableDE(IN ULONG_PTR Context
)
804 __writecr4(__readcr4() | CR4_DE
);
810 Ki386EnableFxsr(IN ULONG_PTR Context
)
813 __writecr4(__readcr4() | CR4_FXSR
);
819 Ki386EnableXMMIExceptions(IN ULONG_PTR Context
)
823 /* Get the IDT Entry for Interrupt 19 */
824 IdtEntry
= &((PKIPCR
)KeGetPcr())->IDT
[19];
827 IdtEntry
->Selector
= KGDT_R0_CODE
;
828 IdtEntry
->Offset
= ((ULONG_PTR
)KiTrap19
& 0xFFFF);
829 IdtEntry
->ExtendedOffset
= ((ULONG_PTR
)KiTrap19
>> 16) & 0xFFFF;
830 ((PKIDT_ACCESS
)&IdtEntry
->Access
)->Dpl
= 0;
831 ((PKIDT_ACCESS
)&IdtEntry
->Access
)->Present
= 1;
832 ((PKIDT_ACCESS
)&IdtEntry
->Access
)->SegmentType
= I386_INTERRUPT_GATE
;
834 /* Enable XMMI exceptions */
835 __writecr4(__readcr4() | CR4_XMMEXCPT
);
841 KiI386PentiumLockErrataFixup(VOID
)
843 KDESCRIPTOR IdtDescriptor
= { 0, 0, 0 };
844 PKIDTENTRY NewIdt
, NewIdt2
;
846 /* Allocate memory for a new IDT */
847 NewIdt
= ExAllocatePool(NonPagedPool
, 2 * PAGE_SIZE
);
849 /* Put everything after the first 7 entries on a new page */
850 NewIdt2
= (PVOID
)((ULONG_PTR
)NewIdt
+ PAGE_SIZE
- (7 * sizeof(KIDTENTRY
)));
852 /* Disable interrupts */
855 /* Get the current IDT and copy it */
856 Ke386GetInterruptDescriptorTable(*(PKDESCRIPTOR
)&IdtDescriptor
.Limit
);
857 RtlCopyMemory(NewIdt2
,
858 (PVOID
)IdtDescriptor
.Base
,
859 IdtDescriptor
.Limit
+ 1);
860 IdtDescriptor
.Base
= (ULONG
)NewIdt2
;
862 /* Set the new IDT */
863 Ke386SetInterruptDescriptorTable(*(PKDESCRIPTOR
)&IdtDescriptor
.Limit
);
864 ((PKIPCR
)KeGetPcr())->IDT
= NewIdt2
;
866 /* Restore interrupts */
869 /* Set the first 7 entries as read-only to produce a fault */
870 MmSetPageProtect(NULL
, NewIdt
, PAGE_READONLY
);
875 KeFreezeExecution(IN PKTRAP_FRAME TrapFrame
,
876 IN PKEXCEPTION_FRAME ExceptionFrame
)
880 /* Disable interrupts and get previous state */
881 Ke386SaveFlags(Flags
);
882 //Flags = __getcallerseflags();
885 /* Save freeze flag */
888 /* Save the old IRQL */
889 KiOldIrql
= KeGetCurrentIrql();
891 /* Return whether interrupts were enabled */
892 return (Flags
& EFLAGS_INTERRUPT_MASK
) ? TRUE
: FALSE
;
897 KeThawExecution(IN BOOLEAN Enable
)
899 /* Cleanup CPU caches */
902 /* Re-enable interrupts */
903 if (Enable
) _enable();
908 KeInvalidateAllCaches(VOID
)
910 /* Only supported on Pentium Pro and higher */
911 if (KeI386CpuType
< 6) return FALSE
;
913 /* Invalidate all caches */
920 KeZeroPages(IN PVOID Address
,
923 /* Not using XMMI in this routine */
924 RtlZeroMemory(Address
, Size
);
927 /* PUBLIC FUNCTIONS **********************************************************/
934 KeSaveFloatingPointState(OUT PKFLOATING_SAVE Save
)
936 PFNSAVE_FORMAT FpState
;
937 ASSERT(KeGetCurrentIrql() == DISPATCH_LEVEL
);
938 DPRINT1("%s is not really implemented\n", __FUNCTION__
);
940 /* check if we are doing software emulation */
941 if (!KeI386NpxPresent
) return STATUS_ILLEGAL_FLOAT_CONTEXT
;
943 FpState
= ExAllocatePool(NonPagedPool
, sizeof (FNSAVE_FORMAT
));
944 if (!FpState
) return STATUS_INSUFFICIENT_RESOURCES
;
946 *((PVOID
*) Save
) = FpState
;
948 asm volatile("fnsave %0\n\t" : "=m" (*FpState
));
956 KeGetCurrentThread()->DispatcherHeader
.NpxIrql
= KeGetCurrentIrql();
957 return STATUS_SUCCESS
;
965 KeRestoreFloatingPointState(IN PKFLOATING_SAVE Save
)
967 PFNSAVE_FORMAT FpState
= *((PVOID
*) Save
);
968 ASSERT(KeGetCurrentThread()->DispatcherHeader
.NpxIrql
== KeGetCurrentIrql());
969 DPRINT1("%s is not really implemented\n", __FUNCTION__
);
972 asm volatile("fnclex\n\t");
973 asm volatile("frstor %0\n\t" : "=m" (*FpState
));
983 return STATUS_SUCCESS
;
991 KeGetRecommendedSharedDataAlignment(VOID
)
993 /* Return the global variable */
994 return KeLargestCacheLine
;
999 KiFlushTargetEntireTb(IN PKIPI_CONTEXT PacketContext
,
1004 /* Signal this packet as done */
1005 KiIpiSignalPacketDone(PacketContext
);
1007 /* Flush the TB for the Current CPU */
1016 KeFlushEntireTb(IN BOOLEAN Invalid
,
1017 IN BOOLEAN AllProcessors
)
1021 KAFFINITY TargetAffinity
;
1022 PKPRCB Prcb
= KeGetCurrentPrcb();
1025 /* Raise the IRQL for the TB Flush */
1026 OldIrql
= KeRaiseIrqlToSynchLevel();
1029 /* FIXME: Use KiTbFlushTimeStamp to synchronize TB flush */
1031 /* Get the current processor affinity, and exclude ourselves */
1032 TargetAffinity
= KeActiveProcessors
;
1033 TargetAffinity
&= ~Prcb
->SetMember
;
1035 /* Make sure this is MP */
1038 /* Send an IPI TB flush to the other processors */
1039 KiIpiSendPacket(TargetAffinity
,
1040 KiFlushTargetEntireTb
,
1047 /* Flush the TB for the Current CPU, and update the flush stamp */
1051 /* If this is MP, wait for the other processors to finish */
1055 ASSERT(Prcb
== (volatile PKPRCB
)KeGetCurrentPrcb());
1058 ASSERTMSG("Not yet implemented\n", FALSE
);
1062 /* Update the flush stamp and return to original IRQL */
1063 InterlockedExchangeAdd(&KiTbFlushTimeStamp
, 1);
1064 KeLowerIrql(OldIrql
);
1072 KeSetDmaIoCoherency(IN ULONG Coherency
)
1074 /* Save the coherency globally */
1075 KiDmaIoCoherency
= Coherency
;
1083 KeQueryActiveProcessors(VOID
)
1087 /* Simply return the number of active processors */
1088 return KeActiveProcessors
;
1096 KeSaveStateForHibernate(IN PKPROCESSOR_STATE State
)
1098 /* Capture the context */
1099 RtlCaptureContext(&State
->ContextFrame
);
1101 /* Capture the control state */
1102 KiSaveProcessorControlState(State
);