2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/iosup.c
5 * PURPOSE: ARM Memory Manager I/O Mapping Functionality
6 * PROGRAMMERS: ReactOS Portable Systems Group
9 /* INCLUDES *******************************************************************/
15 #line 15 "ARMĀ³::IOSUP"
16 #define MODULE_INVOLVED_IN_ARM3
17 #include "../ARM3/miarm.h"
19 /* GLOBALS ********************************************************************/
22 // Each architecture has its own caching attributes for both I/O and Physical
25 // This describes the attributes for the x86 architecture. It eventually needs
26 // to go in the appropriate i386 directory.
28 MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes
[2][MmMaximumCacheType
] =
33 {MiNonCached
,MiCached
,MiWriteCombined
,MiCached
,MiNonCached
,MiWriteCombined
},
38 {MiNonCached
,MiCached
,MiWriteCombined
,MiCached
,MiNonCached
,MiWriteCombined
},
41 /* PUBLIC FUNCTIONS ***********************************************************/
48 MmMapIoSpace(IN PHYSICAL_ADDRESS PhysicalAddress
,
49 IN ULONG NumberOfBytes
,
50 IN MEMORY_CACHING_TYPE CacheType
)
53 PFN_TYPE Pfn
, PageCount
;
58 MI_PFN_CACHE_ATTRIBUTE CacheAttribute
;
62 // Must be called with a non-zero count
64 ASSERT(NumberOfBytes
!= 0);
67 // Make sure the upper bits are 0 if this system
68 // can't describe more than 4 GB of physical memory.
69 // FIXME: This doesn't respect PAE, but we currently don't
70 // define a PAE build flag since there is no such build.
72 #if !defined(_M_AMD64)
73 ASSERT(PhysicalAddress
.HighPart
== 0);
77 // Normalize and validate the caching attributes
80 if (CacheType
>= MmMaximumCacheType
) return NULL
;
83 // Calculate page count
85 PageCount
= ADDRESS_AND_SIZE_TO_SPAN_PAGES(PhysicalAddress
.LowPart
,
89 // Compute the PFN and check if it's a known I/O mapping
90 // Also translate the cache attribute
92 Pfn
= (PFN_NUMBER
)(PhysicalAddress
.QuadPart
>> PAGE_SHIFT
);
93 IsIoMapping
= (Pfn
> MmHighestPhysicalPage
) ? TRUE
: FALSE
;
94 if (!IsIoMapping
) Pfn1
= MiGetPfnEntry(Pfn
);
95 CacheAttribute
= MiPlatformCacheAttributes
[IsIoMapping
][CacheType
];
98 // Now allocate system PTEs for the mapping, and get the VA
100 PointerPte
= MiReserveSystemPtes(PageCount
, SystemPteSpace
);
101 if (!PointerPte
) return NULL
;
102 BaseAddress
= MiPteToAddress(PointerPte
);
105 // Check if this is uncached
107 if (CacheAttribute
!= MiCached
)
112 KeFlushEntireTb(TRUE
, TRUE
);
113 KeInvalidateAllCaches();
117 // Now compute the VA offset
119 BaseAddress
= (PVOID
)((ULONG_PTR
)BaseAddress
+
120 BYTE_OFFSET(PhysicalAddress
.LowPart
));
123 // Get the template and configure caching
125 TempPte
= HyperTemplatePte
;
126 switch (CacheAttribute
)
133 MI_PAGE_DISABLE_CACHE(&TempPte
);
134 MI_PAGE_WRITE_THROUGH(&TempPte
);
144 case MiWriteCombined
:
147 // We don't support write combining yet
155 // Should never happen
162 // Sanity check and re-flush
164 Pfn
= (PFN_NUMBER
)(PhysicalAddress
.QuadPart
>> PAGE_SHIFT
);
165 ASSERT((Pfn1
== MiGetPfnEntry(Pfn
)) || (Pfn1
== NULL
));
166 KeFlushEntireTb(TRUE
, TRUE
);
167 KeInvalidateAllCaches();
175 // Start out with nothing
177 ASSERT(PointerPte
->u
.Hard
.Valid
== 0);
182 TempPte
.u
.Hard
.PageFrameNumber
= Pfn
++;
183 *PointerPte
++ = TempPte
;
184 } while (--PageCount
);
197 MmUnmapIoSpace(IN PVOID BaseAddress
,
198 IN SIZE_T NumberOfBytes
)
200 PFN_NUMBER PageCount
, Pfn
;
206 ASSERT(NumberOfBytes
!= 0);
209 // Get the page count
211 PageCount
= ADDRESS_AND_SIZE_TO_SPAN_PAGES(BaseAddress
, NumberOfBytes
);
214 // Get the PTE and PFN
216 PointerPte
= MiAddressToPte(BaseAddress
);
217 Pfn
= PFN_FROM_PTE(PointerPte
);
220 // Is this an I/O mapping?
222 if (Pfn
> MmHighestPhysicalPage
)
227 RtlZeroMemory(PointerPte
, PageCount
* sizeof(MMPTE
));
232 KeFlushEntireTb(TRUE
, TRUE
);
238 MiReleaseSystemPtes(PointerPte
, PageCount
, 0);
246 MmMapVideoDisplay(IN PHYSICAL_ADDRESS PhysicalAddress
,
247 IN SIZE_T NumberOfBytes
,
248 IN MEMORY_CACHING_TYPE CacheType
)
253 // Call the real function
255 return MmMapIoSpace(PhysicalAddress
, NumberOfBytes
, CacheType
);
263 MmUnmapVideoDisplay(IN PVOID BaseAddress
,
264 IN SIZE_T NumberOfBytes
)
267 // Call the real function
269 MmUnmapIoSpace(BaseAddress
, NumberOfBytes
);