08a8ba261d009415149b17a91eac7213489584d0
[reactos.git] / reactos / ntoskrnl / mm / ARM3 / iosup.c
1 /*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/iosup.c
5 * PURPOSE: ARM Memory Manager I/O Mapping Functionality
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9 /* INCLUDES *******************************************************************/
10
11 #include <ntoskrnl.h>
12 #define NDEBUG
13 #include <debug.h>
14
15 #define MODULE_INVOLVED_IN_ARM3
16 #include <mm/ARM3/miarm.h>
17
18 /* GLOBALS ********************************************************************/
19
20 //
21 // Each architecture has its own caching attributes for both I/O and Physical
22 // memory mappings.
23 //
24 // This describes the attributes for the x86 architecture. It eventually needs
25 // to go in the appropriate i386 directory.
26 //
27 MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType] =
28 {
29 //
30 // RAM
31 //
32 {MiNonCached,MiCached,MiWriteCombined,MiCached,MiNonCached,MiWriteCombined},
33
34 //
35 // Device Memory
36 //
37 {MiNonCached,MiCached,MiWriteCombined,MiCached,MiNonCached,MiWriteCombined},
38 };
39
40 /* PUBLIC FUNCTIONS ***********************************************************/
41
42 /*
43 * @implemented
44 */
45 PVOID
46 NTAPI
47 MmMapIoSpace(IN PHYSICAL_ADDRESS PhysicalAddress,
48 IN SIZE_T NumberOfBytes,
49 IN MEMORY_CACHING_TYPE CacheType)
50 {
51
52 PFN_NUMBER Pfn;
53 PFN_COUNT PageCount;
54 PMMPTE PointerPte;
55 PVOID BaseAddress;
56 MMPTE TempPte;
57 PMMPFN Pfn1 = NULL;
58 MI_PFN_CACHE_ATTRIBUTE CacheAttribute;
59 BOOLEAN IsIoMapping;
60
61 //
62 // Must be called with a non-zero count
63 //
64 ASSERT(NumberOfBytes != 0);
65
66 //
67 // Make sure the upper bits are 0 if this system
68 // can't describe more than 4 GB of physical memory.
69 // FIXME: This doesn't respect PAE, but we currently don't
70 // define a PAE build flag since there is no such build.
71 //
72 #if !defined(_M_AMD64)
73 ASSERT(PhysicalAddress.HighPart == 0);
74 #endif
75
76 //
77 // Normalize and validate the caching attributes
78 //
79 CacheType &= 0xFF;
80 if (CacheType >= MmMaximumCacheType) return NULL;
81
82 //
83 // Calculate page count
84 //
85 PageCount = ADDRESS_AND_SIZE_TO_SPAN_PAGES(PhysicalAddress.LowPart,
86 NumberOfBytes);
87
88 //
89 // Compute the PFN and check if it's a known I/O mapping
90 // Also translate the cache attribute
91 //
92 Pfn = (PFN_NUMBER)(PhysicalAddress.QuadPart >> PAGE_SHIFT);
93 Pfn1 = MiGetPfnEntry(Pfn);
94 IsIoMapping = (Pfn1 == NULL) ? TRUE : FALSE;
95 CacheAttribute = MiPlatformCacheAttributes[IsIoMapping][CacheType];
96
97 //
98 // Now allocate system PTEs for the mapping, and get the VA
99 //
100 PointerPte = MiReserveSystemPtes(PageCount, SystemPteSpace);
101 if (!PointerPte) return NULL;
102 BaseAddress = MiPteToAddress(PointerPte);
103
104 //
105 // Check if this is uncached
106 //
107 if (CacheAttribute != MiCached)
108 {
109 //
110 // Flush all caches
111 //
112 KeFlushEntireTb(TRUE, TRUE);
113 KeInvalidateAllCaches();
114 }
115
116 //
117 // Now compute the VA offset
118 //
119 BaseAddress = (PVOID)((ULONG_PTR)BaseAddress +
120 BYTE_OFFSET(PhysicalAddress.LowPart));
121
122 //
123 // Get the template and configure caching
124 //
125 TempPte = ValidKernelPte;
126 switch (CacheAttribute)
127 {
128 case MiNonCached:
129
130 //
131 // Disable the cache
132 //
133 MI_PAGE_DISABLE_CACHE(&TempPte);
134 MI_PAGE_WRITE_THROUGH(&TempPte);
135 break;
136
137 case MiCached:
138
139 //
140 // Leave defaults
141 //
142 break;
143
144 case MiWriteCombined:
145
146 //
147 // We don't support write combining yet
148 //
149 ASSERT(FALSE);
150 break;
151
152 default:
153
154 //
155 // Should never happen
156 //
157 ASSERT(FALSE);
158 break;
159 }
160
161 //
162 // Sanity check and re-flush
163 //
164 Pfn = (PFN_NUMBER)(PhysicalAddress.QuadPart >> PAGE_SHIFT);
165 ASSERT((Pfn1 == MiGetPfnEntry(Pfn)) || (Pfn1 == NULL));
166 KeFlushEntireTb(TRUE, TRUE);
167 KeInvalidateAllCaches();
168
169 //
170 // Do the mapping
171 //
172 do
173 {
174 //
175 // Write the PFN
176 //
177 TempPte.u.Hard.PageFrameNumber = Pfn++;
178 MI_WRITE_VALID_PTE(PointerPte++, TempPte);
179 } while (--PageCount);
180
181 //
182 // We're done!
183 //
184 return BaseAddress;
185 }
186
187 /*
188 * @implemented
189 */
190 VOID
191 NTAPI
192 MmUnmapIoSpace(IN PVOID BaseAddress,
193 IN SIZE_T NumberOfBytes)
194 {
195 PFN_NUMBER Pfn;
196 PFN_COUNT PageCount;
197 PMMPTE PointerPte;
198
199 //
200 // Sanity check
201 //
202 ASSERT(NumberOfBytes != 0);
203
204 //
205 // Get the page count
206 //
207 PageCount = ADDRESS_AND_SIZE_TO_SPAN_PAGES(BaseAddress, NumberOfBytes);
208
209 //
210 // Get the PTE and PFN
211 //
212 PointerPte = MiAddressToPte(BaseAddress);
213 Pfn = PFN_FROM_PTE(PointerPte);
214
215 //
216 // Is this an I/O mapping?
217 //
218 if (!MiGetPfnEntry(Pfn))
219 {
220 //
221 // Destroy the PTE
222 //
223 RtlZeroMemory(PointerPte, PageCount * sizeof(MMPTE));
224
225 //
226 // Blow the TLB
227 //
228 KeFlushEntireTb(TRUE, TRUE);
229 }
230
231 //
232 // Release the PTEs
233 //
234 MiReleaseSystemPtes(PointerPte, PageCount, 0);
235 }
236
237 /*
238 * @implemented
239 */
240 PVOID
241 NTAPI
242 MmMapVideoDisplay(IN PHYSICAL_ADDRESS PhysicalAddress,
243 IN SIZE_T NumberOfBytes,
244 IN MEMORY_CACHING_TYPE CacheType)
245 {
246 PAGED_CODE();
247
248 //
249 // Call the real function
250 //
251 return MmMapIoSpace(PhysicalAddress, NumberOfBytes, CacheType);
252 }
253
254 /*
255 * @implemented
256 */
257 VOID
258 NTAPI
259 MmUnmapVideoDisplay(IN PVOID BaseAddress,
260 IN SIZE_T NumberOfBytes)
261 {
262 //
263 // Call the real function
264 //
265 MmUnmapIoSpace(BaseAddress, NumberOfBytes);
266 }
267
268 LOGICAL
269 NTAPI
270 MmIsIoSpaceActive(IN PHYSICAL_ADDRESS StartAddress,
271 IN SIZE_T NumberOfBytes)
272 {
273 UNIMPLEMENTED;
274 return FALSE;
275 }
276
277 /* EOF */