reactos/ntoskrnl/mm/ARM3/iosup.c

   1 /*
   2  * PROJECT:         ReactOS Kernel
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            ntoskrnl/mm/ARM3/iosup.c
   5  * PURPOSE:         ARM Memory Manager I/O Mapping Functionality
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 /* INCLUDES *******************************************************************/
  10
  11 #include <ntoskrnl.h>
  12 #define NDEBUG
  13 #include <debug.h>
  14
  15 #line 15 "ARM³::IOSUP"
  16 #define MODULE_INVOLVED_IN_ARM3
  17 #include "../ARM3/miarm.h"
  18
  19 /* GLOBALS ********************************************************************/
  20
  21 //
  22 // Each architecture has its own caching attributes for both I/O and Physical
  23 // memory mappings.
  24 //
  25 // This describes the attributes for the x86 architecture. It eventually needs
  26 // to go in the appropriate i386 directory.
  27 //
  28 MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType] =
  29 {
  30     //
  31     // RAM
  32     //
  33     {MiNonCached,MiCached,MiWriteCombined,MiCached,MiNonCached,MiWriteCombined},
  34
  35     //
  36     // Device Memory
  37     //
  38     {MiNonCached,MiCached,MiWriteCombined,MiCached,MiNonCached,MiWriteCombined},
  39 };
  40
  41 /* PUBLIC FUNCTIONS ***********************************************************/
  42
  43 /*
  44  * @implemented
  45  */
  46 PVOID
  47 NTAPI
  48 MmMapIoSpace(IN PHYSICAL_ADDRESS PhysicalAddress,
  49              IN SIZE_T NumberOfBytes,
  50              IN MEMORY_CACHING_TYPE CacheType)
  51 {
  52
  53     PFN_NUMBER Pfn, PageCount;
  54     PMMPTE PointerPte;
  55     PVOID BaseAddress;
  56     MMPTE TempPte;
  57     PMMPFN Pfn1 = NULL;
  58     MI_PFN_CACHE_ATTRIBUTE CacheAttribute;
  59     BOOLEAN IsIoMapping;
  60
  61     //
  62     // Must be called with a non-zero count
  63     //
  64     ASSERT(NumberOfBytes != 0);
  65
  66     //
  67     // Make sure the upper bits are 0 if this system
  68     // can't describe more than 4 GB of physical memory.
  69     // FIXME: This doesn't respect PAE, but we currently don't
  70     // define a PAE build flag since there is no such build.
  71     //
  72 #if !defined(_M_AMD64)
  73     ASSERT(PhysicalAddress.HighPart == 0);
  74 #endif
  75
  76     //
  77     // Normalize and validate the caching attributes
  78     //
  79     CacheType &= 0xFF;
  80     if (CacheType >= MmMaximumCacheType) return NULL;
  81
  82     //
  83     // Calculate page count
  84     //
  85     PageCount = ADDRESS_AND_SIZE_TO_SPAN_PAGES(PhysicalAddress.LowPart,
  86                                                NumberOfBytes);
  87
  88     //
  89     // Compute the PFN and check if it's a known I/O mapping
  90     // Also translate the cache attribute
  91     //
  92     Pfn = (PFN_NUMBER)(PhysicalAddress.QuadPart >> PAGE_SHIFT);
  93     Pfn1 = MiGetPfnEntry(Pfn);
  94     IsIoMapping = (Pfn1 == NULL) ? TRUE : FALSE;
  95     CacheAttribute = MiPlatformCacheAttributes[IsIoMapping][CacheType];
  96
  97     //
  98     // Now allocate system PTEs for the mapping, and get the VA
  99     //
 100     PointerPte = MiReserveSystemPtes(PageCount, SystemPteSpace);
 101     if (!PointerPte) return NULL;
 102     BaseAddress = MiPteToAddress(PointerPte);
 103
 104     //
 105     // Check if this is uncached
 106     //
 107     if (CacheAttribute != MiCached)
 108     {
 109         //
 110         // Flush all caches
 111         //
 112         KeFlushEntireTb(TRUE, TRUE);
 113         KeInvalidateAllCaches();
 114     }
 115
 116     //
 117     // Now compute the VA offset
 118     //
 119     BaseAddress = (PVOID)((ULONG_PTR)BaseAddress +
 120                           BYTE_OFFSET(PhysicalAddress.LowPart));
 121
 122     //
 123     // Get the template and configure caching
 124     //
 125     TempPte = ValidKernelPte;
 126     switch (CacheAttribute)
 127     {
 128         case MiNonCached:
 129
 130             //
 131             // Disable the cache
 132             //
 133             MI_PAGE_DISABLE_CACHE(&TempPte);
 134             MI_PAGE_WRITE_THROUGH(&TempPte);
 135             break;
 136
 137         case MiCached:
 138
 139             //
 140             // Leave defaults
 141             //
 142             break;
 143
 144         case MiWriteCombined:
 145
 146             //
 147             // We don't support write combining yet
 148             //
 149             ASSERT(FALSE);
 150             break;
 151
 152         default:
 153
 154             //
 155             // Should never happen
 156             //
 157             ASSERT(FALSE);
 158             break;
 159     }
 160
 161     //
 162     // Sanity check and re-flush
 163     //
 164     Pfn = (PFN_NUMBER)(PhysicalAddress.QuadPart >> PAGE_SHIFT);
 165     ASSERT((Pfn1 == MiGetPfnEntry(Pfn)) || (Pfn1 == NULL));
 166     KeFlushEntireTb(TRUE, TRUE);
 167     KeInvalidateAllCaches();
 168
 169     //
 170     // Do the mapping
 171     //
 172     do
 173     {
 174         //
 175         // Write the PFN
 176         //
 177         TempPte.u.Hard.PageFrameNumber = Pfn++;
 178         MI_WRITE_VALID_PTE(PointerPte++, TempPte);
 179     } while (--PageCount);
 180
 181     //
 182     // We're done!
 183     //
 184     return BaseAddress;
 185 }
 186
 187 /*
 188  * @implemented
 189  */
 190 VOID
 191 NTAPI
 192 MmUnmapIoSpace(IN PVOID BaseAddress,
 193                IN SIZE_T NumberOfBytes)
 194 {
 195     PFN_NUMBER PageCount, Pfn;
 196     PMMPTE PointerPte;
 197
 198     //
 199     // Sanity check
 200     //
 201     ASSERT(NumberOfBytes != 0);
 202
 203     //
 204     // Get the page count
 205     //
 206     PageCount = ADDRESS_AND_SIZE_TO_SPAN_PAGES(BaseAddress, NumberOfBytes);
 207
 208     //
 209     // Get the PTE and PFN
 210     //
 211     PointerPte = MiAddressToPte(BaseAddress);
 212     Pfn = PFN_FROM_PTE(PointerPte);
 213
 214     //
 215     // Is this an I/O mapping?
 216     //
 217     if (!MiGetPfnEntry(Pfn))
 218     {
 219         //
 220         // Destroy the PTE
 221         //
 222         RtlZeroMemory(PointerPte, PageCount * sizeof(MMPTE));
 223
 224         //
 225         // Blow the TLB
 226         //
 227         KeFlushEntireTb(TRUE, TRUE);
 228     }
 229
 230     //
 231     // Release the PTEs
 232     //
 233     MiReleaseSystemPtes(PointerPte, PageCount, 0);
 234 }
 235
 236 /*
 237  * @implemented
 238  */
 239 PVOID
 240 NTAPI
 241 MmMapVideoDisplay(IN PHYSICAL_ADDRESS PhysicalAddress,
 242                   IN SIZE_T NumberOfBytes,
 243                   IN MEMORY_CACHING_TYPE CacheType)
 244 {
 245     PAGED_CODE();
 246
 247     //
 248     // Call the real function
 249     //
 250     return MmMapIoSpace(PhysicalAddress, NumberOfBytes, CacheType);
 251 }
 252
 253 /*
 254  * @implemented
 255  */
 256 VOID
 257 NTAPI
 258 MmUnmapVideoDisplay(IN PVOID BaseAddress,
 259                     IN SIZE_T NumberOfBytes)
 260 {
 261     //
 262     // Call the real function
 263     //
 264     MmUnmapIoSpace(BaseAddress, NumberOfBytes);
 265 }
 266
 267 /* EOF */