2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/iosup.c
5 * PURPOSE: ARM Memory Manager I/O Mapping Functionality
6 * PROGRAMMERS: ReactOS Portable Systems Group
9 /* INCLUDES *******************************************************************/
15 #define MODULE_INVOLVED_IN_ARM3
16 #include "../ARM3/miarm.h"
18 /* GLOBALS ********************************************************************/
21 // Each architecture has its own caching attributes for both I/O and Physical
24 // This describes the attributes for the x86 architecture. It eventually needs
25 // to go in the appropriate i386 directory.
27 MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes
[2][MmMaximumCacheType
] =
32 {MiNonCached
,MiCached
,MiWriteCombined
,MiCached
,MiNonCached
,MiWriteCombined
},
37 {MiNonCached
,MiCached
,MiWriteCombined
,MiCached
,MiNonCached
,MiWriteCombined
},
40 /* PUBLIC FUNCTIONS ***********************************************************/
47 MmMapIoSpace(IN PHYSICAL_ADDRESS PhysicalAddress
,
48 IN SIZE_T NumberOfBytes
,
49 IN MEMORY_CACHING_TYPE CacheType
)
58 MI_PFN_CACHE_ATTRIBUTE CacheAttribute
;
62 // Must be called with a non-zero count
64 ASSERT(NumberOfBytes
!= 0);
67 // Make sure the upper bits are 0 if this system
68 // can't describe more than 4 GB of physical memory.
69 // FIXME: This doesn't respect PAE, but we currently don't
70 // define a PAE build flag since there is no such build.
72 #if !defined(_M_AMD64)
73 ASSERT(PhysicalAddress
.HighPart
== 0);
77 // Normalize and validate the caching attributes
80 if (CacheType
>= MmMaximumCacheType
) return NULL
;
83 // Calculate page count
85 PageCount
= ADDRESS_AND_SIZE_TO_SPAN_PAGES(PhysicalAddress
.LowPart
,
89 // Compute the PFN and check if it's a known I/O mapping
90 // Also translate the cache attribute
92 Pfn
= (PFN_NUMBER
)(PhysicalAddress
.QuadPart
>> PAGE_SHIFT
);
93 Pfn1
= MiGetPfnEntry(Pfn
);
94 IsIoMapping
= (Pfn1
== NULL
) ? TRUE
: FALSE
;
95 CacheAttribute
= MiPlatformCacheAttributes
[IsIoMapping
][CacheType
];
98 // Now allocate system PTEs for the mapping, and get the VA
100 PointerPte
= MiReserveSystemPtes(PageCount
, SystemPteSpace
);
101 if (!PointerPte
) return NULL
;
102 BaseAddress
= MiPteToAddress(PointerPte
);
105 // Check if this is uncached
107 if (CacheAttribute
!= MiCached
)
112 KeFlushEntireTb(TRUE
, TRUE
);
113 KeInvalidateAllCaches();
117 // Now compute the VA offset
119 BaseAddress
= (PVOID
)((ULONG_PTR
)BaseAddress
+
120 BYTE_OFFSET(PhysicalAddress
.LowPart
));
123 // Get the template and configure caching
125 TempPte
= ValidKernelPte
;
126 switch (CacheAttribute
)
133 MI_PAGE_DISABLE_CACHE(&TempPte
);
134 MI_PAGE_WRITE_THROUGH(&TempPte
);
144 case MiWriteCombined
:
147 // We don't support write combining yet
155 // Should never happen
162 // Sanity check and re-flush
164 Pfn
= (PFN_NUMBER
)(PhysicalAddress
.QuadPart
>> PAGE_SHIFT
);
165 ASSERT((Pfn1
== MiGetPfnEntry(Pfn
)) || (Pfn1
== NULL
));
166 KeFlushEntireTb(TRUE
, TRUE
);
167 KeInvalidateAllCaches();
177 TempPte
.u
.Hard
.PageFrameNumber
= Pfn
++;
178 MI_WRITE_VALID_PTE(PointerPte
++, TempPte
);
179 } while (--PageCount
);
192 MmUnmapIoSpace(IN PVOID BaseAddress
,
193 IN SIZE_T NumberOfBytes
)
202 ASSERT(NumberOfBytes
!= 0);
205 // Get the page count
207 PageCount
= ADDRESS_AND_SIZE_TO_SPAN_PAGES(BaseAddress
, NumberOfBytes
);
210 // Get the PTE and PFN
212 PointerPte
= MiAddressToPte(BaseAddress
);
213 Pfn
= PFN_FROM_PTE(PointerPte
);
216 // Is this an I/O mapping?
218 if (!MiGetPfnEntry(Pfn
))
223 RtlZeroMemory(PointerPte
, PageCount
* sizeof(MMPTE
));
228 KeFlushEntireTb(TRUE
, TRUE
);
234 MiReleaseSystemPtes(PointerPte
, PageCount
, 0);
242 MmMapVideoDisplay(IN PHYSICAL_ADDRESS PhysicalAddress
,
243 IN SIZE_T NumberOfBytes
,
244 IN MEMORY_CACHING_TYPE CacheType
)
249 // Call the real function
251 return MmMapIoSpace(PhysicalAddress
, NumberOfBytes
, CacheType
);
259 MmUnmapVideoDisplay(IN PVOID BaseAddress
,
260 IN SIZE_T NumberOfBytes
)
263 // Call the real function
265 MmUnmapIoSpace(BaseAddress
, NumberOfBytes
);