[NTOSKRNL]
[reactos.git] / reactos / ntoskrnl / mm / ARM3 / miarm.h
1 /*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/miarm.h
5 * PURPOSE: ARM Memory Manager Header
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9 #ifndef _M_AMD64
10
11 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
12 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT)
13 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT)
14 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * 1024 * 1024)
15 #define MI_MAX_NONPAGED_POOL_SIZE (128 * 1024 * 1024)
16 #define MI_MAX_FREE_PAGE_LISTS 4
17
18 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024)
19
20 #define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024)
21 #define MI_SESSION_POOL_SIZE (16 * 1024 * 1024)
22 #define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024)
23 #define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024)
24 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
25 MI_SESSION_POOL_SIZE + \
26 MI_SESSION_IMAGE_SIZE + \
27 MI_SESSION_WORKING_SET_SIZE)
28
29 #define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024)
30
31 #define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
32 #define MI_PAGED_POOL_START (PVOID)0xE1000000
33 #define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
34 #define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
35
36 #define MI_MIN_SECONDARY_COLORS 8
37 #define MI_SECONDARY_COLORS 64
38 #define MI_MAX_SECONDARY_COLORS 1024
39
40 #define MM_HIGHEST_VAD_ADDRESS \
41 (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
42
43 #endif /* !_M_AMD64 */
44
45 /* Make the code cleaner with some definitions for size multiples */
46 #define _1KB (1024)
47 #define _1MB (1024 * _1KB)
48
49 /* Area mapped by a PDE */
50 #define PDE_MAPPED_VA (PTE_COUNT * PAGE_SIZE)
51
52 /* Size of a page table */
53 #define PT_SIZE (PTE_COUNT * sizeof(MMPTE))
54
55 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
56 #ifdef _M_IX86
57 #define PD_COUNT 1
58 #define PDE_COUNT 1024
59 #define PTE_COUNT 1024
60 #elif _M_ARM
61 #define PD_COUNT 1
62 #define PDE_COUNT 4096
63 #define PTE_COUNT 256
64 #else
65 #define PD_COUNT PPE_PER_PAGE
66 #define PDE_COUNT PDE_PER_PAGE
67 #define PTE_COUNT PTE_PER_PAGE
68 #endif
69
70 #ifdef _M_IX86
71 #define IMAGE_FILE_MACHINE_NATIVE IMAGE_FILE_MACHINE_I386
72 #elif _M_ARM
73 #define IMAGE_FILE_MACHINE_NATIVE IMAGE_FILE_MACHINE_ARM
74 #elif _M_AMD64
75 #define IMAGE_FILE_MACHINE_NATIVE IMAGE_FILE_MACHINE_AMD64
76 #else
77 #error Define these please!
78 #endif
79
80 //
81 // Protection Bits part of the internal memory manager Protection Mask
82 // Taken from http://www.reactos.org/wiki/Techwiki:Memory_management_in_the_Windows_XP_kernel
83 // and public assertions.
84 //
85 #define MM_ZERO_ACCESS 0
86 #define MM_READONLY 1
87 #define MM_EXECUTE 2
88 #define MM_EXECUTE_READ 3
89 #define MM_READWRITE 4
90 #define MM_WRITECOPY 5
91 #define MM_EXECUTE_READWRITE 6
92 #define MM_EXECUTE_WRITECOPY 7
93 #define MM_NOCACHE 8
94 #define MM_DECOMMIT 0x10
95 #define MM_NOACCESS (MM_DECOMMIT | MM_NOCACHE)
96
97 //
98 // Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits
99 // The Memory Manager's definition define the attributes that must be preserved
100 // and these PTE definitions describe the attributes in the hardware sense. This
101 // helps deal with hardware differences between the actual boolean expression of
102 // the argument.
103 //
104 // For example, in the logical attributes, we want to express read-only as a flag
105 // but on x86, it is writability that must be set. On the other hand, on x86, just
106 // like in the kernel, it is disabling the caches that requires a special flag,
107 // while on certain architectures such as ARM, it is enabling the cache which
108 // requires a flag.
109 //
110 #if defined(_M_IX86) || defined(_M_AMD64)
111 //
112 // Access Flags
113 //
114 #define PTE_READONLY 0
115 #define PTE_EXECUTE 0 // Not worrying about NX yet
116 #define PTE_EXECUTE_READ 0 // Not worrying about NX yet
117 #define PTE_READWRITE 0x2
118 #define PTE_WRITECOPY 0x200
119 #define PTE_EXECUTE_READWRITE 0x0
120 #define PTE_EXECUTE_WRITECOPY 0x200
121 //
122 // Cache flags
123 //
124 #define PTE_ENABLE_CACHE 0
125 #define PTE_DISABLE_CACHE 0x10
126 #define PTE_WRITECOMBINED_CACHE 0x10
127 #elif defined(_M_ARM)
128 #else
129 #error Define these please!
130 #endif
131 static const
132 ULONG
133 MmProtectToPteMask[32] =
134 {
135 //
136 // These are the base MM_ protection flags
137 //
138 0,
139 PTE_READONLY | PTE_ENABLE_CACHE,
140 PTE_EXECUTE | PTE_ENABLE_CACHE,
141 PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
142 PTE_READWRITE | PTE_ENABLE_CACHE,
143 PTE_WRITECOPY | PTE_ENABLE_CACHE,
144 PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
145 PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
146 //
147 // These OR in the MM_NOCACHE flag
148 //
149 0,
150 PTE_READONLY | PTE_DISABLE_CACHE,
151 PTE_EXECUTE | PTE_DISABLE_CACHE,
152 PTE_EXECUTE_READ | PTE_DISABLE_CACHE,
153 PTE_READWRITE | PTE_DISABLE_CACHE,
154 PTE_WRITECOPY | PTE_DISABLE_CACHE,
155 PTE_EXECUTE_READWRITE | PTE_DISABLE_CACHE,
156 PTE_EXECUTE_WRITECOPY | PTE_DISABLE_CACHE,
157 //
158 // These OR in the MM_DECOMMIT flag, which doesn't seem supported on x86/64/ARM
159 //
160 0,
161 PTE_READONLY | PTE_ENABLE_CACHE,
162 PTE_EXECUTE | PTE_ENABLE_CACHE,
163 PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
164 PTE_READWRITE | PTE_ENABLE_CACHE,
165 PTE_WRITECOPY | PTE_ENABLE_CACHE,
166 PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
167 PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
168 //
169 // These OR in the MM_NOACCESS flag, which seems to enable WriteCombining?
170 //
171 0,
172 PTE_READONLY | PTE_WRITECOMBINED_CACHE,
173 PTE_EXECUTE | PTE_WRITECOMBINED_CACHE,
174 PTE_EXECUTE_READ | PTE_WRITECOMBINED_CACHE,
175 PTE_READWRITE | PTE_WRITECOMBINED_CACHE,
176 PTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
177 PTE_EXECUTE_READWRITE | PTE_WRITECOMBINED_CACHE,
178 PTE_EXECUTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
179 };
180
181 //
182 // Assertions for session images, addresses, and PTEs
183 //
184 #define MI_IS_SESSION_IMAGE_ADDRESS(Address) \
185 (((Address) >= MiSessionImageStart) && ((Address) < MiSessionImageEnd))
186
187 #define MI_IS_SESSION_ADDRESS(Address) \
188 (((Address) >= MmSessionBase) && ((Address) < MiSessionSpaceEnd))
189
190 #define MI_IS_SESSION_PTE(Pte) \
191 ((((PMMPTE)Pte) >= MiSessionBasePte) && (((PMMPTE)Pte) < MiSessionLastPte))
192
193 //
194 // Corresponds to MMPTE_SOFTWARE.Protection
195 //
196 #ifdef _M_IX86
197 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5
198 #elif _M_ARM
199 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5
200 #elif _M_AMD64
201 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5
202 #else
203 #error Define these please!
204 #endif
205
206 //
207 // Creates a software PTE with the given protection
208 //
209 #define MI_MAKE_SOFTWARE_PTE(p, x) ((p)->u.Long = (x << MM_PTE_SOFTWARE_PROTECTION_BITS))
210
211 //
212 // Marks a PTE as deleted
213 //
214 #define MI_SET_PFN_DELETED(x) ((x)->PteAddress = (PMMPTE)((ULONG_PTR)(x)->PteAddress | 1))
215 #define MI_IS_PFN_DELETED(x) ((ULONG_PTR)((x)->PteAddress) & 1)
216
217 //
218 // Special values for LoadedImports
219 //
220 #define MM_SYSLDR_NO_IMPORTS (PVOID)0xFFFFFFFE
221 #define MM_SYSLDR_BOOT_LOADED (PVOID)0xFFFFFFFF
222 #define MM_SYSLDR_SINGLE_ENTRY 0x1
223
224 //
225 // PFN List Sentinel
226 //
227 #define LIST_HEAD 0xFFFFFFFF
228
229 //
230 // Special IRQL value (found in assertions)
231 //
232 #define MM_NOIRQL (KIRQL)0xFFFFFFFF
233
234 //
235 // FIXFIX: These should go in ex.h after the pool merge
236 //
237 #ifdef _M_AMD64
238 #define POOL_BLOCK_SIZE 16
239 #else
240 #define POOL_BLOCK_SIZE 8
241 #endif
242 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / POOL_BLOCK_SIZE)
243 #define BASE_POOL_TYPE_MASK 1
244 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + POOL_BLOCK_SIZE))
245
246 typedef struct _POOL_DESCRIPTOR
247 {
248 POOL_TYPE PoolType;
249 ULONG PoolIndex;
250 ULONG RunningAllocs;
251 ULONG RunningDeAllocs;
252 ULONG TotalPages;
253 ULONG TotalBigPages;
254 ULONG Threshold;
255 PVOID LockAddress;
256 PVOID PendingFrees;
257 LONG PendingFreeDepth;
258 SIZE_T TotalBytes;
259 SIZE_T Spare0;
260 LIST_ENTRY ListHeads[POOL_LISTS_PER_PAGE];
261 } POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
262
263 typedef struct _POOL_HEADER
264 {
265 union
266 {
267 struct
268 {
269 #ifdef _M_AMD64
270 ULONG PreviousSize:8;
271 ULONG PoolIndex:8;
272 ULONG BlockSize:8;
273 ULONG PoolType:8;
274 #else
275 USHORT PreviousSize:9;
276 USHORT PoolIndex:7;
277 USHORT BlockSize:9;
278 USHORT PoolType:7;
279 #endif
280 };
281 ULONG Ulong1;
282 };
283 #ifdef _M_AMD64
284 ULONG PoolTag;
285 #endif
286 union
287 {
288 #ifdef _M_AMD64
289 PEPROCESS ProcessBilled;
290 #else
291 ULONG PoolTag;
292 #endif
293 struct
294 {
295 USHORT AllocatorBackTraceIndex;
296 USHORT PoolTagHash;
297 };
298 };
299 } POOL_HEADER, *PPOOL_HEADER;
300
301 C_ASSERT(sizeof(POOL_HEADER) == POOL_BLOCK_SIZE);
302 C_ASSERT(POOL_BLOCK_SIZE == sizeof(LIST_ENTRY));
303
304 extern ULONG ExpNumberOfPagedPools;
305 extern POOL_DESCRIPTOR NonPagedPoolDescriptor;
306 extern PPOOL_DESCRIPTOR ExpPagedPoolDescriptor[16 + 1];
307 extern PVOID PoolTrackTable;
308
309 //
310 // END FIXFIX
311 //
312
313 typedef struct _MI_LARGE_PAGE_DRIVER_ENTRY
314 {
315 LIST_ENTRY Links;
316 UNICODE_STRING BaseName;
317 } MI_LARGE_PAGE_DRIVER_ENTRY, *PMI_LARGE_PAGE_DRIVER_ENTRY;
318
319 typedef enum _MMSYSTEM_PTE_POOL_TYPE
320 {
321 SystemPteSpace,
322 NonPagedPoolExpansion,
323 MaximumPtePoolTypes
324 } MMSYSTEM_PTE_POOL_TYPE;
325
326 typedef enum _MI_PFN_CACHE_ATTRIBUTE
327 {
328 MiNonCached,
329 MiCached,
330 MiWriteCombined,
331 MiNotMapped
332 } MI_PFN_CACHE_ATTRIBUTE, *PMI_PFN_CACHE_ATTRIBUTE;
333
334 typedef struct _PHYSICAL_MEMORY_RUN
335 {
336 ULONG BasePage;
337 ULONG PageCount;
338 } PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
339
340 typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
341 {
342 ULONG NumberOfRuns;
343 ULONG NumberOfPages;
344 PHYSICAL_MEMORY_RUN Run[1];
345 } PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
346
347 typedef struct _MMCOLOR_TABLES
348 {
349 PFN_NUMBER Flink;
350 PVOID Blink;
351 PFN_NUMBER Count;
352 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
353
354 typedef struct _MI_LARGE_PAGE_RANGES
355 {
356 PFN_NUMBER StartFrame;
357 PFN_NUMBER LastFrame;
358 } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
359
360 extern MMPTE HyperTemplatePte;
361 extern MMPDE ValidKernelPde;
362 extern MMPTE ValidKernelPte;
363 extern BOOLEAN MmLargeSystemCache;
364 extern BOOLEAN MmZeroPageFile;
365 extern BOOLEAN MmProtectFreedNonPagedPool;
366 extern BOOLEAN MmTrackLockedPages;
367 extern BOOLEAN MmTrackPtes;
368 extern BOOLEAN MmDynamicPfn;
369 extern BOOLEAN MmMirroring;
370 extern BOOLEAN MmMakeLowMemory;
371 extern BOOLEAN MmEnforceWriteProtection;
372 extern ULONG MmAllocationFragment;
373 extern ULONG MmConsumedPoolPercentage;
374 extern ULONG MmVerifyDriverBufferType;
375 extern ULONG MmVerifyDriverLevel;
376 extern WCHAR MmVerifyDriverBuffer[512];
377 extern WCHAR MmLargePageDriverBuffer[512];
378 extern LIST_ENTRY MiLargePageDriverList;
379 extern BOOLEAN MiLargePageAllDrivers;
380 extern ULONG MmVerifyDriverBufferLength;
381 extern ULONG MmLargePageDriverBufferLength;
382 extern SIZE_T MmSizeOfNonPagedPoolInBytes;
383 extern SIZE_T MmMaximumNonPagedPoolInBytes;
384 extern PFN_NUMBER MmMaximumNonPagedPoolInPages;
385 extern PFN_NUMBER MmSizeOfPagedPoolInPages;
386 extern PVOID MmNonPagedSystemStart;
387 extern PVOID MmNonPagedPoolStart;
388 extern PVOID MmNonPagedPoolExpansionStart;
389 extern PVOID MmNonPagedPoolEnd;
390 extern SIZE_T MmSizeOfPagedPoolInBytes;
391 extern PVOID MmPagedPoolStart;
392 extern PVOID MmPagedPoolEnd;
393 extern PVOID MmSessionBase;
394 extern SIZE_T MmSessionSize;
395 extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
396 extern PMMPTE MiFirstReservedZeroingPte;
397 extern MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType];
398 extern PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
399 extern SIZE_T MmBootImageSize;
400 extern PMMPTE MmSystemPtesStart[MaximumPtePoolTypes];
401 extern PMMPTE MmSystemPtesEnd[MaximumPtePoolTypes];
402 extern PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
403 extern MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
404 extern ULONG_PTR MxPfnAllocation;
405 extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
406 extern RTL_BITMAP MiPfnBitMap;
407 extern KGUARDED_MUTEX MmPagedPoolMutex;
408 extern PVOID MmPagedPoolStart;
409 extern PVOID MmPagedPoolEnd;
410 extern PVOID MmNonPagedSystemStart;
411 extern PVOID MiSystemViewStart;
412 extern SIZE_T MmSystemViewSize;
413 extern PVOID MmSessionBase;
414 extern PVOID MiSessionSpaceEnd;
415 extern PMMPTE MiSessionImagePteStart;
416 extern PMMPTE MiSessionImagePteEnd;
417 extern PMMPTE MiSessionBasePte;
418 extern PMMPTE MiSessionLastPte;
419 extern SIZE_T MmSizeOfPagedPoolInBytes;
420 extern PMMPTE MmSystemPagePtes;
421 extern PVOID MmSystemCacheStart;
422 extern PVOID MmSystemCacheEnd;
423 extern MMSUPPORT MmSystemCacheWs;
424 extern SIZE_T MmAllocatedNonPagedPool;
425 extern ULONG_PTR MmSubsectionBase;
426 extern ULONG MmSpecialPoolTag;
427 extern PVOID MmHyperSpaceEnd;
428 extern PMMWSL MmSystemCacheWorkingSetList;
429 extern SIZE_T MmMinimumNonPagedPoolSize;
430 extern ULONG MmMinAdditionNonPagedPoolPerMb;
431 extern SIZE_T MmDefaultMaximumNonPagedPool;
432 extern ULONG MmMaxAdditionNonPagedPoolPerMb;
433 extern ULONG MmSecondaryColors;
434 extern ULONG MmSecondaryColorMask;
435 extern ULONG_PTR MmNumberOfSystemPtes;
436 extern ULONG MmMaximumNonPagedPoolPercent;
437 extern ULONG MmLargeStackSize;
438 extern PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
439 extern ULONG MmProductType;
440 extern MM_SYSTEMSIZE MmSystemSize;
441 extern PKEVENT MiLowMemoryEvent;
442 extern PKEVENT MiHighMemoryEvent;
443 extern PKEVENT MiLowPagedPoolEvent;
444 extern PKEVENT MiHighPagedPoolEvent;
445 extern PKEVENT MiLowNonPagedPoolEvent;
446 extern PKEVENT MiHighNonPagedPoolEvent;
447 extern PFN_NUMBER MmLowMemoryThreshold;
448 extern PFN_NUMBER MmHighMemoryThreshold;
449 extern PFN_NUMBER MiLowPagedPoolThreshold;
450 extern PFN_NUMBER MiHighPagedPoolThreshold;
451 extern PFN_NUMBER MiLowNonPagedPoolThreshold;
452 extern PFN_NUMBER MiHighNonPagedPoolThreshold;
453 extern PFN_NUMBER MmMinimumFreePages;
454 extern PFN_NUMBER MmPlentyFreePages;
455 extern PFN_NUMBER MiExpansionPoolPagesInitialCharge;
456 extern PFN_NUMBER MmResidentAvailablePages;
457 extern PFN_NUMBER MmResidentAvailableAtInit;
458 extern ULONG MmTotalFreeSystemPtes[MaximumPtePoolTypes];
459 extern PFN_NUMBER MmTotalSystemDriverPages;
460 extern PVOID MiSessionImageStart;
461 extern PVOID MiSessionImageEnd;
462 extern PMMPTE MiHighestUserPte;
463 extern PMMPDE MiHighestUserPde;
464 extern PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
465
466 #define MI_PFN_TO_PFNENTRY(x) (&MmPfnDatabase[1][x])
467 #define MI_PFNENTRY_TO_PFN(x) (x - MmPfnDatabase[1])
468
469 //
470 // Creates a valid kernel PTE with the given protection
471 //
472 FORCEINLINE
473 VOID
474 MI_MAKE_HARDWARE_PTE(IN PMMPTE NewPte,
475 IN PMMPTE MappingPte,
476 IN ULONG ProtectionMask,
477 IN PFN_NUMBER PageFrameNumber)
478 {
479 /* Only valid for kernel, non-session PTEs */
480 ASSERT(MappingPte > MiHighestUserPte);
481 ASSERT(!MI_IS_SESSION_PTE(MappingPte));
482 ASSERT((MappingPte < (PMMPTE)PDE_BASE) || (MappingPte > (PMMPTE)PDE_TOP));
483
484 /* Start fresh */
485 *NewPte = ValidKernelPte;
486
487 /* Set the protection and page */
488 NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
489 NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
490 }
491
492 //
493 // Returns if the page is physically resident (ie: a large page)
494 // FIXFIX: CISC/x86 only?
495 //
496 FORCEINLINE
497 BOOLEAN
498 MI_IS_PHYSICAL_ADDRESS(IN PVOID Address)
499 {
500 PMMPDE PointerPde;
501
502 /* Large pages are never paged out, always physically resident */
503 PointerPde = MiAddressToPde(Address);
504 return ((PointerPde->u.Hard.LargePage) && (PointerPde->u.Hard.Valid));
505 }
506
507 //
508 // Writes a valid PTE
509 //
510 VOID
511 FORCEINLINE
512 MI_WRITE_VALID_PTE(IN PMMPTE PointerPte,
513 IN MMPTE TempPte)
514 {
515 /* Write the valid PTE */
516 ASSERT(PointerPte->u.Hard.Valid == 0);
517 ASSERT(TempPte.u.Hard.Valid == 1);
518 *PointerPte = TempPte;
519 }
520
521 //
522 // Writes an invalid PTE
523 //
524 VOID
525 FORCEINLINE
526 MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte,
527 IN MMPTE InvalidPte)
528 {
529 /* Write the invalid PTE */
530 ASSERT(InvalidPte.u.Hard.Valid == 0);
531 *PointerPte = InvalidPte;
532 }
533
534 NTSTATUS
535 NTAPI
536 MmArmInitSystem(
537 IN ULONG Phase,
538 IN PLOADER_PARAMETER_BLOCK LoaderBlock
539 );
540
541 NTSTATUS
542 NTAPI
543 MiInitMachineDependent(
544 IN PLOADER_PARAMETER_BLOCK LoaderBlock
545 );
546
547 VOID
548 NTAPI
549 MiComputeColorInformation(
550 VOID
551 );
552
553 VOID
554 NTAPI
555 MiMapPfnDatabase(
556 IN PLOADER_PARAMETER_BLOCK LoaderBlock
557 );
558
559 VOID
560 NTAPI
561 MiInitializeColorTables(
562 VOID
563 );
564
565 VOID
566 NTAPI
567 MiInitializePfnDatabase(
568 IN PLOADER_PARAMETER_BLOCK LoaderBlock
569 );
570
571 BOOLEAN
572 NTAPI
573 MiInitializeMemoryEvents(
574 VOID
575 );
576
577 PFN_NUMBER
578 NTAPI
579 MxGetNextPage(
580 IN PFN_NUMBER PageCount
581 );
582
583 PPHYSICAL_MEMORY_DESCRIPTOR
584 NTAPI
585 MmInitializeMemoryLimits(
586 IN PLOADER_PARAMETER_BLOCK LoaderBlock,
587 IN PBOOLEAN IncludeType
588 );
589
590 PFN_NUMBER
591 NTAPI
592 MiPagesInLoaderBlock(
593 IN PLOADER_PARAMETER_BLOCK LoaderBlock,
594 IN PBOOLEAN IncludeType
595 );
596
597 VOID
598 FASTCALL
599 MiSyncARM3WithROS(
600 IN PVOID AddressStart,
601 IN PVOID AddressEnd
602 );
603
604 NTSTATUS
605 NTAPI
606 MmArmAccessFault(
607 IN BOOLEAN StoreInstruction,
608 IN PVOID Address,
609 IN KPROCESSOR_MODE Mode,
610 IN PVOID TrapInformation
611 );
612
613 NTSTATUS
614 FASTCALL
615 MiCheckPdeForPagedPool(
616 IN PVOID Address
617 );
618
619 VOID
620 NTAPI
621 MiInitializeNonPagedPool(
622 VOID
623 );
624
625 VOID
626 NTAPI
627 MiInitializeNonPagedPoolThresholds(
628 VOID
629 );
630
631 VOID
632 NTAPI
633 MiInitializePoolEvents(
634 VOID
635 );
636
637 VOID //
638 NTAPI //
639 InitializePool( //
640 IN POOL_TYPE PoolType,// FIXFIX: This should go in ex.h after the pool merge
641 IN ULONG Threshold //
642 ); //
643
644 VOID
645 NTAPI
646 MiInitializeSystemPtes(
647 IN PMMPTE StartingPte,
648 IN ULONG NumberOfPtes,
649 IN MMSYSTEM_PTE_POOL_TYPE PoolType
650 );
651
652 PMMPTE
653 NTAPI
654 MiReserveSystemPtes(
655 IN ULONG NumberOfPtes,
656 IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
657 );
658
659 VOID
660 NTAPI
661 MiReleaseSystemPtes(
662 IN PMMPTE StartingPte,
663 IN ULONG NumberOfPtes,
664 IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
665 );
666
667
668 PFN_NUMBER
669 NTAPI
670 MiFindContiguousPages(
671 IN PFN_NUMBER LowestPfn,
672 IN PFN_NUMBER HighestPfn,
673 IN PFN_NUMBER BoundaryPfn,
674 IN PFN_NUMBER SizeInPages,
675 IN MEMORY_CACHING_TYPE CacheType
676 );
677
678 PVOID
679 NTAPI
680 MiCheckForContiguousMemory(
681 IN PVOID BaseAddress,
682 IN PFN_NUMBER BaseAddressPages,
683 IN PFN_NUMBER SizeInPages,
684 IN PFN_NUMBER LowestPfn,
685 IN PFN_NUMBER HighestPfn,
686 IN PFN_NUMBER BoundaryPfn,
687 IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
688 );
689
690 PMDL
691 NTAPI
692 MiAllocatePagesForMdl(
693 IN PHYSICAL_ADDRESS LowAddress,
694 IN PHYSICAL_ADDRESS HighAddress,
695 IN PHYSICAL_ADDRESS SkipBytes,
696 IN SIZE_T TotalBytes,
697 IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
698 IN ULONG Flags
699 );
700
701 PVOID
702 NTAPI
703 MiMapLockedPagesInUserSpace(
704 IN PMDL Mdl,
705 IN PVOID BaseVa,
706 IN MEMORY_CACHING_TYPE CacheType,
707 IN PVOID BaseAddress
708 );
709
710 VOID
711 NTAPI
712 MiUnmapLockedPagesInUserSpace(
713 IN PVOID BaseAddress,
714 IN PMDL Mdl
715 );
716
717 VOID
718 NTAPI
719 MiInsertInListTail(
720 IN PMMPFNLIST ListHead,
721 IN PMMPFN Entry
722 );
723
724 VOID
725 NTAPI
726 MiInsertZeroListAtBack(
727 IN PFN_NUMBER PageIndex
728 );
729
730 VOID
731 NTAPI
732 MiUnlinkFreeOrZeroedPage(
733 IN PMMPFN Entry
734 );
735
736 PMMPFN
737 NTAPI
738 MiRemoveHeadList(
739 IN PMMPFNLIST ListHead
740 );
741
742 PFN_NUMBER
743 NTAPI
744 MiAllocatePfn(
745 IN PMMPTE PointerPte,
746 IN ULONG Protection
747 );
748
749 VOID
750 NTAPI
751 MiInitializePfn(
752 IN PFN_NUMBER PageFrameIndex,
753 IN PMMPTE PointerPte,
754 IN BOOLEAN Modified
755 );
756
757 VOID
758 NTAPI
759 MiInitializePfnForOtherProcess(
760 IN PFN_NUMBER PageFrameIndex,
761 IN PMMPTE PointerPte,
762 IN PFN_NUMBER PteFrame
763 );
764
765 VOID
766 NTAPI
767 MiDecrementShareCount(
768 IN PMMPFN Pfn1,
769 IN PFN_NUMBER PageFrameIndex
770 );
771
772 PFN_NUMBER
773 NTAPI
774 MiRemoveAnyPage(
775 IN ULONG Color
776 );
777
778 PFN_NUMBER
779 NTAPI
780 MiRemoveZeroPage(
781 IN ULONG Color
782 );
783
784 VOID
785 NTAPI
786 MiInsertPageInFreeList(
787 IN PFN_NUMBER PageFrameIndex
788 );
789
790 PFN_NUMBER
791 NTAPI
792 MiDeleteSystemPageableVm(
793 IN PMMPTE PointerPte,
794 IN PFN_NUMBER PageCount,
795 IN ULONG Flags,
796 OUT PPFN_NUMBER ValidPages
797 );
798
799 PLDR_DATA_TABLE_ENTRY
800 NTAPI
801 MiLookupDataTableEntry(
802 IN PVOID Address
803 );
804
805 VOID
806 NTAPI
807 MiInitializeDriverLargePageList(
808 VOID
809 );
810
811 VOID
812 NTAPI
813 MiInitializeLargePageSupport(
814 VOID
815 );
816
817 VOID
818 NTAPI
819 MiSyncCachedRanges(
820 VOID
821 );
822
823 BOOLEAN
824 NTAPI
825 MiIsPfnInUse(
826 IN PMMPFN Pfn1
827 );
828
829 /* EOF */