23271256c9115bf548fea94389e9b61bfa990eae
[reactos.git] / reactos / ntoskrnl / mm / ARM3 / miarm.h
1 /*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/miarm.h
5 * PURPOSE: ARM Memory Manager Header
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9 #ifndef _M_AMD64
10
11 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
12 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
13 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
14 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB)
15 #define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB)
16 #define MI_MAX_FREE_PAGE_LISTS 4
17
18 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
19
20 #define MI_SESSION_VIEW_SIZE (20 * _1MB)
21 #define MI_SESSION_POOL_SIZE (16 * _1MB)
22 #define MI_SESSION_IMAGE_SIZE (8 * _1MB)
23 #define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
24 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
25 MI_SESSION_POOL_SIZE + \
26 MI_SESSION_IMAGE_SIZE + \
27 MI_SESSION_WORKING_SET_SIZE)
28
29 #define MI_SYSTEM_VIEW_SIZE (16 * _1MB)
30
31 #define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000
32 #define MI_PAGED_POOL_START (PVOID)0xE1000000
33 #define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000
34 #define MI_DEBUG_MAPPING (PVOID)0xFFBFF000
35
36 #define MI_MIN_SECONDARY_COLORS 8
37 #define MI_SECONDARY_COLORS 64
38 #define MI_MAX_SECONDARY_COLORS 1024
39
40 #define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
41 #define MI_ALLOCATION_FRAGMENT (64 * _1KB)
42 #define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
43
44 #define MM_HIGHEST_VAD_ADDRESS \
45 (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
46
47 /* The range 0x10000->0x7FEFFFFF is reserved for the ROSMM MAREA Allocator */
48 #define MI_LOWEST_VAD_ADDRESS (PVOID)0x7FF00000
49
50 #endif /* !_M_AMD64 */
51
52 /* Make the code cleaner with some definitions for size multiples */
53 #define _1KB (1024u)
54 #define _1MB (1024 * _1KB)
55 #define _1GB (1024 * _1MB)
56
57 /* Area mapped by a PDE */
58 #define PDE_MAPPED_VA (PTE_COUNT * PAGE_SIZE)
59
60 /* Size of a page table */
61 #define PT_SIZE (PTE_COUNT * sizeof(MMPTE))
62
63 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
64 #ifdef _M_IX86
65 #define PD_COUNT 1
66 #define PDE_COUNT 1024
67 #define PTE_COUNT 1024
68 #elif _M_ARM
69 #define PD_COUNT 1
70 #define PDE_COUNT 4096
71 #define PTE_COUNT 256
72 #else
73 #define PD_COUNT PPE_PER_PAGE
74 #define PDE_COUNT PDE_PER_PAGE
75 #define PTE_COUNT PTE_PER_PAGE
76 #endif
77
78 #ifdef _M_IX86
79 #define IMAGE_FILE_MACHINE_NATIVE IMAGE_FILE_MACHINE_I386
80 #elif _M_ARM
81 #define IMAGE_FILE_MACHINE_NATIVE IMAGE_FILE_MACHINE_ARM
82 #elif _M_AMD64
83 #define IMAGE_FILE_MACHINE_NATIVE IMAGE_FILE_MACHINE_AMD64
84 #else
85 #error Define these please!
86 #endif
87
88 //
89 // Protection Bits part of the internal memory manager Protection Mask
90 // Taken from http://www.reactos.org/wiki/Techwiki:Memory_management_in_the_Windows_XP_kernel
91 // and public assertions.
92 //
93 #define MM_ZERO_ACCESS 0
94 #define MM_READONLY 1
95 #define MM_EXECUTE 2
96 #define MM_EXECUTE_READ 3
97 #define MM_READWRITE 4
98 #define MM_WRITECOPY 5
99 #define MM_EXECUTE_READWRITE 6
100 #define MM_EXECUTE_WRITECOPY 7
101 #define MM_NOCACHE 8
102 #define MM_DECOMMIT 0x10
103 #define MM_NOACCESS (MM_DECOMMIT | MM_NOCACHE)
104
105 //
106 // Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits
107 // The Memory Manager's definition define the attributes that must be preserved
108 // and these PTE definitions describe the attributes in the hardware sense. This
109 // helps deal with hardware differences between the actual boolean expression of
110 // the argument.
111 //
112 // For example, in the logical attributes, we want to express read-only as a flag
113 // but on x86, it is writability that must be set. On the other hand, on x86, just
114 // like in the kernel, it is disabling the caches that requires a special flag,
115 // while on certain architectures such as ARM, it is enabling the cache which
116 // requires a flag.
117 //
118 #if defined(_M_IX86) || defined(_M_AMD64)
119 //
120 // Access Flags
121 //
122 #define PTE_READONLY 0
123 #define PTE_EXECUTE 0 // Not worrying about NX yet
124 #define PTE_EXECUTE_READ 0 // Not worrying about NX yet
125 #define PTE_READWRITE 0x2
126 #define PTE_WRITECOPY 0x200
127 #define PTE_EXECUTE_READWRITE 0x0
128 #define PTE_EXECUTE_WRITECOPY 0x200
129 //
130 // Cache flags
131 //
132 #define PTE_ENABLE_CACHE 0
133 #define PTE_DISABLE_CACHE 0x10
134 #define PTE_WRITECOMBINED_CACHE 0x10
135 #elif defined(_M_ARM)
136 #else
137 #error Define these please!
138 #endif
139 static const
140 ULONG
141 MmProtectToPteMask[32] =
142 {
143 //
144 // These are the base MM_ protection flags
145 //
146 0,
147 PTE_READONLY | PTE_ENABLE_CACHE,
148 PTE_EXECUTE | PTE_ENABLE_CACHE,
149 PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
150 PTE_READWRITE | PTE_ENABLE_CACHE,
151 PTE_WRITECOPY | PTE_ENABLE_CACHE,
152 PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
153 PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
154 //
155 // These OR in the MM_NOCACHE flag
156 //
157 0,
158 PTE_READONLY | PTE_DISABLE_CACHE,
159 PTE_EXECUTE | PTE_DISABLE_CACHE,
160 PTE_EXECUTE_READ | PTE_DISABLE_CACHE,
161 PTE_READWRITE | PTE_DISABLE_CACHE,
162 PTE_WRITECOPY | PTE_DISABLE_CACHE,
163 PTE_EXECUTE_READWRITE | PTE_DISABLE_CACHE,
164 PTE_EXECUTE_WRITECOPY | PTE_DISABLE_CACHE,
165 //
166 // These OR in the MM_DECOMMIT flag, which doesn't seem supported on x86/64/ARM
167 //
168 0,
169 PTE_READONLY | PTE_ENABLE_CACHE,
170 PTE_EXECUTE | PTE_ENABLE_CACHE,
171 PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
172 PTE_READWRITE | PTE_ENABLE_CACHE,
173 PTE_WRITECOPY | PTE_ENABLE_CACHE,
174 PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
175 PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
176 //
177 // These OR in the MM_NOACCESS flag, which seems to enable WriteCombining?
178 //
179 0,
180 PTE_READONLY | PTE_WRITECOMBINED_CACHE,
181 PTE_EXECUTE | PTE_WRITECOMBINED_CACHE,
182 PTE_EXECUTE_READ | PTE_WRITECOMBINED_CACHE,
183 PTE_READWRITE | PTE_WRITECOMBINED_CACHE,
184 PTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
185 PTE_EXECUTE_READWRITE | PTE_WRITECOMBINED_CACHE,
186 PTE_EXECUTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
187 };
188
189 //
190 // Assertions for session images, addresses, and PTEs
191 //
192 #define MI_IS_SESSION_IMAGE_ADDRESS(Address) \
193 (((Address) >= MiSessionImageStart) && ((Address) < MiSessionImageEnd))
194
195 #define MI_IS_SESSION_ADDRESS(Address) \
196 (((Address) >= MmSessionBase) && ((Address) < MiSessionSpaceEnd))
197
198 #define MI_IS_SESSION_PTE(Pte) \
199 ((((PMMPTE)Pte) >= MiSessionBasePte) && (((PMMPTE)Pte) < MiSessionLastPte))
200
201 #define MI_IS_PAGE_TABLE_ADDRESS(Address) \
202 (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)PTE_TOP))
203
204 #define MI_IS_SYSTEM_PAGE_TABLE_ADDRESS(Address) \
205 (((Address) >= (PVOID)MiAddressToPte(MmSystemRangeStart)) && ((Address) <= (PVOID)PTE_TOP))
206
207 #define MI_IS_PAGE_TABLE_OR_HYPER_ADDRESS(Address) \
208 (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)MmHyperSpaceEnd))
209
210 //
211 // Corresponds to MMPTE_SOFTWARE.Protection
212 //
213 #ifdef _M_IX86
214 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5
215 #elif _M_ARM
216 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5
217 #elif _M_AMD64
218 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5
219 #else
220 #error Define these please!
221 #endif
222
223 //
224 // Creates a software PTE with the given protection
225 //
226 #define MI_MAKE_SOFTWARE_PTE(p, x) ((p)->u.Long = (x << MM_PTE_SOFTWARE_PROTECTION_BITS))
227
228 //
229 // Marks a PTE as deleted
230 //
231 #define MI_SET_PFN_DELETED(x) ((x)->PteAddress = (PMMPTE)((ULONG_PTR)(x)->PteAddress | 1))
232 #define MI_IS_PFN_DELETED(x) ((ULONG_PTR)((x)->PteAddress) & 1)
233
234 //
235 // Special values for LoadedImports
236 //
237 #define MM_SYSLDR_NO_IMPORTS (PVOID)0xFFFFFFFE
238 #define MM_SYSLDR_BOOT_LOADED (PVOID)0xFFFFFFFF
239 #define MM_SYSLDR_SINGLE_ENTRY 0x1
240
241 //
242 // PFN List Sentinel
243 //
244 #define LIST_HEAD 0xFFFFFFFF
245
246 //
247 // Special IRQL value (found in assertions)
248 //
249 #define MM_NOIRQL (KIRQL)0xFFFFFFFF
250
251 //
252 // FIXFIX: These should go in ex.h after the pool merge
253 //
254 #ifdef _M_AMD64
255 #define POOL_BLOCK_SIZE 16
256 #else
257 #define POOL_BLOCK_SIZE 8
258 #endif
259 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / POOL_BLOCK_SIZE)
260 #define BASE_POOL_TYPE_MASK 1
261 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + POOL_BLOCK_SIZE))
262
263 typedef struct _POOL_DESCRIPTOR
264 {
265 POOL_TYPE PoolType;
266 ULONG PoolIndex;
267 ULONG RunningAllocs;
268 ULONG RunningDeAllocs;
269 ULONG TotalPages;
270 ULONG TotalBigPages;
271 ULONG Threshold;
272 PVOID LockAddress;
273 PVOID PendingFrees;
274 LONG PendingFreeDepth;
275 SIZE_T TotalBytes;
276 SIZE_T Spare0;
277 LIST_ENTRY ListHeads[POOL_LISTS_PER_PAGE];
278 } POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
279
280 typedef struct _POOL_HEADER
281 {
282 union
283 {
284 struct
285 {
286 #ifdef _M_AMD64
287 ULONG PreviousSize:8;
288 ULONG PoolIndex:8;
289 ULONG BlockSize:8;
290 ULONG PoolType:8;
291 #else
292 USHORT PreviousSize:9;
293 USHORT PoolIndex:7;
294 USHORT BlockSize:9;
295 USHORT PoolType:7;
296 #endif
297 };
298 ULONG Ulong1;
299 };
300 #ifdef _M_AMD64
301 ULONG PoolTag;
302 #endif
303 union
304 {
305 #ifdef _M_AMD64
306 PEPROCESS ProcessBilled;
307 #else
308 ULONG PoolTag;
309 #endif
310 struct
311 {
312 USHORT AllocatorBackTraceIndex;
313 USHORT PoolTagHash;
314 };
315 };
316 } POOL_HEADER, *PPOOL_HEADER;
317
318 C_ASSERT(sizeof(POOL_HEADER) == POOL_BLOCK_SIZE);
319 C_ASSERT(POOL_BLOCK_SIZE == sizeof(LIST_ENTRY));
320
321 extern ULONG ExpNumberOfPagedPools;
322 extern POOL_DESCRIPTOR NonPagedPoolDescriptor;
323 extern PPOOL_DESCRIPTOR ExpPagedPoolDescriptor[16 + 1];
324 extern PVOID PoolTrackTable;
325
326 //
327 // END FIXFIX
328 //
329
330 typedef struct _MI_LARGE_PAGE_DRIVER_ENTRY
331 {
332 LIST_ENTRY Links;
333 UNICODE_STRING BaseName;
334 } MI_LARGE_PAGE_DRIVER_ENTRY, *PMI_LARGE_PAGE_DRIVER_ENTRY;
335
336 typedef enum _MMSYSTEM_PTE_POOL_TYPE
337 {
338 SystemPteSpace,
339 NonPagedPoolExpansion,
340 MaximumPtePoolTypes
341 } MMSYSTEM_PTE_POOL_TYPE;
342
343 typedef enum _MI_PFN_CACHE_ATTRIBUTE
344 {
345 MiNonCached,
346 MiCached,
347 MiWriteCombined,
348 MiNotMapped
349 } MI_PFN_CACHE_ATTRIBUTE, *PMI_PFN_CACHE_ATTRIBUTE;
350
351 typedef struct _PHYSICAL_MEMORY_RUN
352 {
353 ULONG BasePage;
354 ULONG PageCount;
355 } PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
356
357 typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
358 {
359 ULONG NumberOfRuns;
360 ULONG NumberOfPages;
361 PHYSICAL_MEMORY_RUN Run[1];
362 } PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
363
364 typedef struct _MMCOLOR_TABLES
365 {
366 PFN_NUMBER Flink;
367 PVOID Blink;
368 PFN_NUMBER Count;
369 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
370
371 typedef struct _MI_LARGE_PAGE_RANGES
372 {
373 PFN_NUMBER StartFrame;
374 PFN_NUMBER LastFrame;
375 } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
376
377 extern MMPTE HyperTemplatePte;
378 extern MMPDE ValidKernelPde;
379 extern MMPTE ValidKernelPte;
380 extern BOOLEAN MmLargeSystemCache;
381 extern BOOLEAN MmZeroPageFile;
382 extern BOOLEAN MmProtectFreedNonPagedPool;
383 extern BOOLEAN MmTrackLockedPages;
384 extern BOOLEAN MmTrackPtes;
385 extern BOOLEAN MmDynamicPfn;
386 extern BOOLEAN MmMirroring;
387 extern BOOLEAN MmMakeLowMemory;
388 extern BOOLEAN MmEnforceWriteProtection;
389 extern ULONG MmAllocationFragment;
390 extern ULONG MmConsumedPoolPercentage;
391 extern ULONG MmVerifyDriverBufferType;
392 extern ULONG MmVerifyDriverLevel;
393 extern WCHAR MmVerifyDriverBuffer[512];
394 extern WCHAR MmLargePageDriverBuffer[512];
395 extern LIST_ENTRY MiLargePageDriverList;
396 extern BOOLEAN MiLargePageAllDrivers;
397 extern ULONG MmVerifyDriverBufferLength;
398 extern ULONG MmLargePageDriverBufferLength;
399 extern SIZE_T MmSizeOfNonPagedPoolInBytes;
400 extern SIZE_T MmMaximumNonPagedPoolInBytes;
401 extern PFN_NUMBER MmMaximumNonPagedPoolInPages;
402 extern PFN_NUMBER MmSizeOfPagedPoolInPages;
403 extern PVOID MmNonPagedSystemStart;
404 extern PVOID MmNonPagedPoolStart;
405 extern PVOID MmNonPagedPoolExpansionStart;
406 extern PVOID MmNonPagedPoolEnd;
407 extern SIZE_T MmSizeOfPagedPoolInBytes;
408 extern PVOID MmPagedPoolStart;
409 extern PVOID MmPagedPoolEnd;
410 extern PVOID MmSessionBase;
411 extern SIZE_T MmSessionSize;
412 extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
413 extern PMMPTE MiFirstReservedZeroingPte;
414 extern MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType];
415 extern PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
416 extern SIZE_T MmBootImageSize;
417 extern PMMPTE MmSystemPtesStart[MaximumPtePoolTypes];
418 extern PMMPTE MmSystemPtesEnd[MaximumPtePoolTypes];
419 extern PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
420 extern MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
421 extern ULONG_PTR MxPfnAllocation;
422 extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
423 extern RTL_BITMAP MiPfnBitMap;
424 extern KGUARDED_MUTEX MmPagedPoolMutex;
425 extern PVOID MmPagedPoolStart;
426 extern PVOID MmPagedPoolEnd;
427 extern PVOID MmNonPagedSystemStart;
428 extern PVOID MiSystemViewStart;
429 extern SIZE_T MmSystemViewSize;
430 extern PVOID MmSessionBase;
431 extern PVOID MiSessionSpaceEnd;
432 extern PMMPTE MiSessionImagePteStart;
433 extern PMMPTE MiSessionImagePteEnd;
434 extern PMMPTE MiSessionBasePte;
435 extern PMMPTE MiSessionLastPte;
436 extern SIZE_T MmSizeOfPagedPoolInBytes;
437 extern PMMPTE MmSystemPagePtes;
438 extern PVOID MmSystemCacheStart;
439 extern PVOID MmSystemCacheEnd;
440 extern MMSUPPORT MmSystemCacheWs;
441 extern SIZE_T MmAllocatedNonPagedPool;
442 extern ULONG_PTR MmSubsectionBase;
443 extern ULONG MmSpecialPoolTag;
444 extern PVOID MmHyperSpaceEnd;
445 extern PMMWSL MmSystemCacheWorkingSetList;
446 extern SIZE_T MmMinimumNonPagedPoolSize;
447 extern ULONG MmMinAdditionNonPagedPoolPerMb;
448 extern SIZE_T MmDefaultMaximumNonPagedPool;
449 extern ULONG MmMaxAdditionNonPagedPoolPerMb;
450 extern ULONG MmSecondaryColors;
451 extern ULONG MmSecondaryColorMask;
452 extern ULONG_PTR MmNumberOfSystemPtes;
453 extern ULONG MmMaximumNonPagedPoolPercent;
454 extern ULONG MmLargeStackSize;
455 extern PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
456 extern ULONG MmProductType;
457 extern MM_SYSTEMSIZE MmSystemSize;
458 extern PKEVENT MiLowMemoryEvent;
459 extern PKEVENT MiHighMemoryEvent;
460 extern PKEVENT MiLowPagedPoolEvent;
461 extern PKEVENT MiHighPagedPoolEvent;
462 extern PKEVENT MiLowNonPagedPoolEvent;
463 extern PKEVENT MiHighNonPagedPoolEvent;
464 extern PFN_NUMBER MmLowMemoryThreshold;
465 extern PFN_NUMBER MmHighMemoryThreshold;
466 extern PFN_NUMBER MiLowPagedPoolThreshold;
467 extern PFN_NUMBER MiHighPagedPoolThreshold;
468 extern PFN_NUMBER MiLowNonPagedPoolThreshold;
469 extern PFN_NUMBER MiHighNonPagedPoolThreshold;
470 extern PFN_NUMBER MmMinimumFreePages;
471 extern PFN_NUMBER MmPlentyFreePages;
472 extern PFN_NUMBER MiExpansionPoolPagesInitialCharge;
473 extern PFN_NUMBER MmResidentAvailablePages;
474 extern PFN_NUMBER MmResidentAvailableAtInit;
475 extern ULONG MmTotalFreeSystemPtes[MaximumPtePoolTypes];
476 extern PFN_NUMBER MmTotalSystemDriverPages;
477 extern PVOID MiSessionImageStart;
478 extern PVOID MiSessionImageEnd;
479 extern PMMPTE MiHighestUserPte;
480 extern PMMPDE MiHighestUserPde;
481 extern PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
482
483 #define MI_PFN_TO_PFNENTRY(x) (&MmPfnDatabase[1][x])
484 #define MI_PFNENTRY_TO_PFN(x) (x - MmPfnDatabase[1])
485
486 //
487 // Figures out the hardware bits for a PTE
488 //
489 ULONG
490 FORCEINLINE
491 MiDetermineUserGlobalPteMask(IN PMMPTE PointerPte)
492 {
493 MMPTE TempPte;
494
495 /* Start fresh */
496 TempPte.u.Long = 0;
497
498 /* Make it valid and accessed */
499 TempPte.u.Hard.Valid = TRUE;
500 TempPte.u.Hard.Accessed = TRUE;
501
502 /* Is this for user-mode? */
503 if ((PointerPte <= MiHighestUserPte) ||
504 ((PointerPte >= MiAddressToPde(NULL)) && (PointerPte <= MiHighestUserPde)))
505 {
506 /* Set the owner bit */
507 TempPte.u.Hard.Owner = TRUE;
508 }
509
510 /* FIXME: We should also set the global bit */
511
512 /* Return the protection */
513 return TempPte.u.Long;
514 }
515
516 //
517 // Creates a valid kernel PTE with the given protection
518 //
519 FORCEINLINE
520 VOID
521 MI_MAKE_HARDWARE_PTE_KERNEL(IN PMMPTE NewPte,
522 IN PMMPTE MappingPte,
523 IN ULONG ProtectionMask,
524 IN PFN_NUMBER PageFrameNumber)
525 {
526 /* Only valid for kernel, non-session PTEs */
527 ASSERT(MappingPte > MiHighestUserPte);
528 ASSERT(!MI_IS_SESSION_PTE(MappingPte));
529 ASSERT((MappingPte < (PMMPTE)PDE_BASE) || (MappingPte > (PMMPTE)PDE_TOP));
530
531 /* Start fresh */
532 *NewPte = ValidKernelPte;
533
534 /* Set the protection and page */
535 NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
536 NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
537 }
538
539 //
540 // Creates a valid PTE with the given protection
541 //
542 FORCEINLINE
543 VOID
544 MI_MAKE_HARDWARE_PTE(IN PMMPTE NewPte,
545 IN PMMPTE MappingPte,
546 IN ULONG ProtectionMask,
547 IN PFN_NUMBER PageFrameNumber)
548 {
549 /* Set the protection and page */
550 NewPte->u.Long = MiDetermineUserGlobalPteMask(MappingPte);
551 NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
552 NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
553 }
554
555 //
556 // Creates a valid user PTE with the given protection
557 //
558 FORCEINLINE
559 VOID
560 MI_MAKE_HARDWARE_PTE_USER(IN PMMPTE NewPte,
561 IN PMMPTE MappingPte,
562 IN ULONG ProtectionMask,
563 IN PFN_NUMBER PageFrameNumber)
564 {
565 /* Only valid for kernel, non-session PTEs */
566 ASSERT(MappingPte <= MiHighestUserPte);
567
568 /* Start fresh */
569 *NewPte = ValidKernelPte;
570
571 /* Set the protection and page */
572 NewPte->u.Hard.Owner = TRUE;
573 NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
574 NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
575 }
576
577 //
578 // Returns if the page is physically resident (ie: a large page)
579 // FIXFIX: CISC/x86 only?
580 //
581 FORCEINLINE
582 BOOLEAN
583 MI_IS_PHYSICAL_ADDRESS(IN PVOID Address)
584 {
585 PMMPDE PointerPde;
586
587 /* Large pages are never paged out, always physically resident */
588 PointerPde = MiAddressToPde(Address);
589 return ((PointerPde->u.Hard.LargePage) && (PointerPde->u.Hard.Valid));
590 }
591
592 //
593 // Writes a valid PTE
594 //
595 VOID
596 FORCEINLINE
597 MI_WRITE_VALID_PTE(IN PMMPTE PointerPte,
598 IN MMPTE TempPte)
599 {
600 /* Write the valid PTE */
601 ASSERT(PointerPte->u.Hard.Valid == 0);
602 ASSERT(TempPte.u.Hard.Valid == 1);
603 *PointerPte = TempPte;
604 }
605
606 //
607 // Writes an invalid PTE
608 //
609 VOID
610 FORCEINLINE
611 MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte,
612 IN MMPTE InvalidPte)
613 {
614 /* Write the invalid PTE */
615 ASSERT(InvalidPte.u.Hard.Valid == 0);
616 *PointerPte = InvalidPte;
617 }
618
619 //
620 // Checks if the thread already owns a working set
621 //
622 FORCEINLINE
623 BOOLEAN
624 MM_ANY_WS_LOCK_HELD(IN PETHREAD Thread)
625 {
626 /* If any of these are held, return TRUE */
627 return ((Thread->OwnsProcessWorkingSetExclusive) ||
628 (Thread->OwnsProcessWorkingSetShared) ||
629 (Thread->OwnsSystemWorkingSetExclusive) ||
630 (Thread->OwnsSystemWorkingSetShared) ||
631 (Thread->OwnsSessionWorkingSetExclusive) ||
632 (Thread->OwnsSessionWorkingSetShared));
633 }
634
635 //
636 // Checks if the process owns the working set lock
637 //
638 FORCEINLINE
639 BOOLEAN
640 MI_WS_OWNER(IN PEPROCESS Process)
641 {
642 /* Check if this process is the owner, and that the thread owns the WS */
643 return ((KeGetCurrentThread()->ApcState.Process == &Process->Pcb) &&
644 ((PsGetCurrentThread()->OwnsProcessWorkingSetExclusive) ||
645 (PsGetCurrentThread()->OwnsProcessWorkingSetShared)));
646 }
647
648 //
649 // Locks the working set for the given process
650 //
651 FORCEINLINE
652 VOID
653 MiLockProcessWorkingSet(IN PEPROCESS Process,
654 IN PETHREAD Thread)
655 {
656 /* Shouldn't already be owning the process working set */
657 ASSERT(Thread->OwnsProcessWorkingSetShared == FALSE);
658 ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
659
660 /* Block APCs, make sure that still nothing is already held */
661 KeEnterGuardedRegion();
662 ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
663
664 /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
665
666 /* FIXME: This also can't be checked because Vm is used by MAREAs) */
667 //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
668
669 /* Okay, now we can own it exclusively */
670 ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
671 Thread->OwnsProcessWorkingSetExclusive = TRUE;
672 }
673
674 //
675 // Unlocks the working set for the given process
676 //
677 FORCEINLINE
678 VOID
679 MiUnlockProcessWorkingSet(IN PEPROCESS Process,
680 IN PETHREAD Thread)
681 {
682 /* Make sure this process really is owner, and it was a safe acquisition */
683 ASSERT(MI_WS_OWNER(Process));
684 /* This can't be checked because Vm is used by MAREAs) */
685 //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
686
687 /* The thread doesn't own it anymore */
688 ASSERT(Thread->OwnsProcessWorkingSetExclusive == TRUE);
689 Thread->OwnsProcessWorkingSetExclusive = FALSE;
690
691 /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
692
693 /* Unblock APCs */
694 KeLeaveGuardedRegion();
695 }
696
697 //
698 // Locks the working set
699 //
700 FORCEINLINE
701 VOID
702 MiLockWorkingSet(IN PETHREAD Thread,
703 IN PMMSUPPORT WorkingSet)
704 {
705 /* Block APCs */
706 KeEnterGuardedRegion();
707
708 /* Working set should be in global memory */
709 ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
710
711 /* Thread shouldn't already be owning something */
712 ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
713
714 /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
715
716 /* Which working set is this? */
717 if (WorkingSet == &MmSystemCacheWs)
718 {
719 /* Own the system working set */
720 ASSERT((Thread->OwnsSystemWorkingSetExclusive == FALSE) &&
721 (Thread->OwnsSystemWorkingSetShared == FALSE));
722 Thread->OwnsSystemWorkingSetExclusive = TRUE;
723 }
724 else if (WorkingSet->Flags.SessionSpace)
725 {
726 /* We don't implement this yet */
727 UNIMPLEMENTED;
728 while (TRUE);
729 }
730 else
731 {
732 /* Own the process working set */
733 ASSERT((Thread->OwnsProcessWorkingSetExclusive == FALSE) &&
734 (Thread->OwnsProcessWorkingSetShared == FALSE));
735 Thread->OwnsProcessWorkingSetExclusive = TRUE;
736 }
737 }
738
739 //
740 // Unlocks the working set
741 //
742 FORCEINLINE
743 VOID
744 MiUnlockWorkingSet(IN PETHREAD Thread,
745 IN PMMSUPPORT WorkingSet)
746 {
747 /* Working set should be in global memory */
748 ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
749
750 /* Which working set is this? */
751 if (WorkingSet == &MmSystemCacheWs)
752 {
753 /* Release the system working set */
754 ASSERT((Thread->OwnsSystemWorkingSetExclusive == TRUE) ||
755 (Thread->OwnsSystemWorkingSetShared == TRUE));
756 Thread->OwnsSystemWorkingSetExclusive = FALSE;
757 }
758 else if (WorkingSet->Flags.SessionSpace)
759 {
760 /* We don't implement this yet */
761 UNIMPLEMENTED;
762 while (TRUE);
763 }
764 else
765 {
766 /* Release the process working set */
767 ASSERT((Thread->OwnsProcessWorkingSetExclusive) ||
768 (Thread->OwnsProcessWorkingSetShared));
769 Thread->OwnsProcessWorkingSetExclusive = FALSE;
770 }
771
772 /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
773
774 /* Unblock APCs */
775 KeLeaveGuardedRegion();
776 }
777
778 NTSTATUS
779 NTAPI
780 MmArmInitSystem(
781 IN ULONG Phase,
782 IN PLOADER_PARAMETER_BLOCK LoaderBlock
783 );
784
785 NTSTATUS
786 NTAPI
787 MiInitMachineDependent(
788 IN PLOADER_PARAMETER_BLOCK LoaderBlock
789 );
790
791 VOID
792 NTAPI
793 MiComputeColorInformation(
794 VOID
795 );
796
797 VOID
798 NTAPI
799 MiMapPfnDatabase(
800 IN PLOADER_PARAMETER_BLOCK LoaderBlock
801 );
802
803 VOID
804 NTAPI
805 MiInitializeColorTables(
806 VOID
807 );
808
809 VOID
810 NTAPI
811 MiInitializePfnDatabase(
812 IN PLOADER_PARAMETER_BLOCK LoaderBlock
813 );
814
815 BOOLEAN
816 NTAPI
817 MiInitializeMemoryEvents(
818 VOID
819 );
820
821 PFN_NUMBER
822 NTAPI
823 MxGetNextPage(
824 IN PFN_NUMBER PageCount
825 );
826
827 PPHYSICAL_MEMORY_DESCRIPTOR
828 NTAPI
829 MmInitializeMemoryLimits(
830 IN PLOADER_PARAMETER_BLOCK LoaderBlock,
831 IN PBOOLEAN IncludeType
832 );
833
834 PFN_NUMBER
835 NTAPI
836 MiPagesInLoaderBlock(
837 IN PLOADER_PARAMETER_BLOCK LoaderBlock,
838 IN PBOOLEAN IncludeType
839 );
840
841 VOID
842 FASTCALL
843 MiSyncARM3WithROS(
844 IN PVOID AddressStart,
845 IN PVOID AddressEnd
846 );
847
848 NTSTATUS
849 NTAPI
850 MmArmAccessFault(
851 IN BOOLEAN StoreInstruction,
852 IN PVOID Address,
853 IN KPROCESSOR_MODE Mode,
854 IN PVOID TrapInformation
855 );
856
857 NTSTATUS
858 FASTCALL
859 MiCheckPdeForPagedPool(
860 IN PVOID Address
861 );
862
863 VOID
864 NTAPI
865 MiInitializeNonPagedPool(
866 VOID
867 );
868
869 VOID
870 NTAPI
871 MiInitializeNonPagedPoolThresholds(
872 VOID
873 );
874
875 VOID
876 NTAPI
877 MiInitializePoolEvents(
878 VOID
879 );
880
881 VOID //
882 NTAPI //
883 InitializePool( //
884 IN POOL_TYPE PoolType,// FIXFIX: This should go in ex.h after the pool merge
885 IN ULONG Threshold //
886 ); //
887
888 VOID
889 NTAPI
890 MiInitializeSystemPtes(
891 IN PMMPTE StartingPte,
892 IN ULONG NumberOfPtes,
893 IN MMSYSTEM_PTE_POOL_TYPE PoolType
894 );
895
896 PMMPTE
897 NTAPI
898 MiReserveSystemPtes(
899 IN ULONG NumberOfPtes,
900 IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
901 );
902
903 VOID
904 NTAPI
905 MiReleaseSystemPtes(
906 IN PMMPTE StartingPte,
907 IN ULONG NumberOfPtes,
908 IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
909 );
910
911
912 PFN_NUMBER
913 NTAPI
914 MiFindContiguousPages(
915 IN PFN_NUMBER LowestPfn,
916 IN PFN_NUMBER HighestPfn,
917 IN PFN_NUMBER BoundaryPfn,
918 IN PFN_NUMBER SizeInPages,
919 IN MEMORY_CACHING_TYPE CacheType
920 );
921
922 PVOID
923 NTAPI
924 MiCheckForContiguousMemory(
925 IN PVOID BaseAddress,
926 IN PFN_NUMBER BaseAddressPages,
927 IN PFN_NUMBER SizeInPages,
928 IN PFN_NUMBER LowestPfn,
929 IN PFN_NUMBER HighestPfn,
930 IN PFN_NUMBER BoundaryPfn,
931 IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
932 );
933
934 PMDL
935 NTAPI
936 MiAllocatePagesForMdl(
937 IN PHYSICAL_ADDRESS LowAddress,
938 IN PHYSICAL_ADDRESS HighAddress,
939 IN PHYSICAL_ADDRESS SkipBytes,
940 IN SIZE_T TotalBytes,
941 IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
942 IN ULONG Flags
943 );
944
945 PVOID
946 NTAPI
947 MiMapLockedPagesInUserSpace(
948 IN PMDL Mdl,
949 IN PVOID BaseVa,
950 IN MEMORY_CACHING_TYPE CacheType,
951 IN PVOID BaseAddress
952 );
953
954 VOID
955 NTAPI
956 MiUnmapLockedPagesInUserSpace(
957 IN PVOID BaseAddress,
958 IN PMDL Mdl
959 );
960
961 VOID
962 NTAPI
963 MiInsertInListTail(
964 IN PMMPFNLIST ListHead,
965 IN PMMPFN Entry
966 );
967
968 VOID
969 NTAPI
970 MiInsertZeroListAtBack(
971 IN PFN_NUMBER PageIndex
972 );
973
974 VOID
975 NTAPI
976 MiUnlinkFreeOrZeroedPage(
977 IN PMMPFN Entry
978 );
979
980 PMMPFN
981 NTAPI
982 MiRemoveHeadList(
983 IN PMMPFNLIST ListHead
984 );
985
986 PFN_NUMBER
987 NTAPI
988 MiAllocatePfn(
989 IN PMMPTE PointerPte,
990 IN ULONG Protection
991 );
992
993 VOID
994 NTAPI
995 MiInitializePfn(
996 IN PFN_NUMBER PageFrameIndex,
997 IN PMMPTE PointerPte,
998 IN BOOLEAN Modified
999 );
1000
1001 VOID
1002 NTAPI
1003 MiInitializePfnForOtherProcess(
1004 IN PFN_NUMBER PageFrameIndex,
1005 IN PMMPTE PointerPte,
1006 IN PFN_NUMBER PteFrame
1007 );
1008
1009 VOID
1010 NTAPI
1011 MiDecrementShareCount(
1012 IN PMMPFN Pfn1,
1013 IN PFN_NUMBER PageFrameIndex
1014 );
1015
1016 PFN_NUMBER
1017 NTAPI
1018 MiRemoveAnyPage(
1019 IN ULONG Color
1020 );
1021
1022 PFN_NUMBER
1023 NTAPI
1024 MiRemoveZeroPage(
1025 IN ULONG Color
1026 );
1027
1028 VOID
1029 NTAPI
1030 MiInsertPageInFreeList(
1031 IN PFN_NUMBER PageFrameIndex
1032 );
1033
1034 PFN_NUMBER
1035 NTAPI
1036 MiDeleteSystemPageableVm(
1037 IN PMMPTE PointerPte,
1038 IN PFN_NUMBER PageCount,
1039 IN ULONG Flags,
1040 OUT PPFN_NUMBER ValidPages
1041 );
1042
1043 PLDR_DATA_TABLE_ENTRY
1044 NTAPI
1045 MiLookupDataTableEntry(
1046 IN PVOID Address
1047 );
1048
1049 VOID
1050 NTAPI
1051 MiInitializeDriverLargePageList(
1052 VOID
1053 );
1054
1055 VOID
1056 NTAPI
1057 MiInitializeLargePageSupport(
1058 VOID
1059 );
1060
1061 VOID
1062 NTAPI
1063 MiSyncCachedRanges(
1064 VOID
1065 );
1066
1067 BOOLEAN
1068 NTAPI
1069 MiIsPfnInUse(
1070 IN PMMPFN Pfn1
1071 );
1072
1073 PMMVAD
1074 NTAPI
1075 MiLocateAddress(
1076 IN PVOID VirtualAddress
1077 );
1078
1079 PMMADDRESS_NODE
1080 NTAPI
1081 MiCheckForConflictingNode(
1082 IN ULONG_PTR StartVpn,
1083 IN ULONG_PTR EndVpn,
1084 IN PMM_AVL_TABLE Table
1085 );
1086
1087 NTSTATUS
1088 NTAPI
1089 MiFindEmptyAddressRangeDownTree(
1090 IN SIZE_T Length,
1091 IN ULONG_PTR BoundaryAddress,
1092 IN ULONG_PTR Alignment,
1093 IN PMM_AVL_TABLE Table,
1094 OUT PULONG_PTR Base
1095 );
1096
1097 VOID
1098 NTAPI
1099 MiInsertNode(
1100 IN PMMADDRESS_NODE NewNode,
1101 IN PMM_AVL_TABLE Table
1102 );
1103
1104 /* EOF */