reactos/ntoskrnl/mm/ARM3/miarm.h

   1 /*
   2  * PROJECT:         ReactOS Kernel
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            ntoskrnl/mm/ARM3/miarm.h
   5  * PURPOSE:         ARM Memory Manager Header
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 #ifndef _M_AMD64
  10
  11 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING   ((255 * _1MB) >> PAGE_SHIFT)
  12 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING          ((19 * _1MB) >> PAGE_SHIFT)
  13 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST           ((32 * _1MB) >> PAGE_SHIFT)
  14 #define MI_MAX_INIT_NONPAGED_POOL_SIZE          (128 * _1MB)
  15 #define MI_MAX_NONPAGED_POOL_SIZE               (128 * _1MB)
  16 #define MI_MAX_FREE_PAGE_LISTS                  4
  17
  18 #define MI_MIN_INIT_PAGED_POOLSIZE              (32 * _1MB)
  19
  20 #define MI_SESSION_VIEW_SIZE                    (20 * _1MB)
  21 #define MI_SESSION_POOL_SIZE                    (16 * _1MB)
  22 #define MI_SESSION_IMAGE_SIZE                   (8 * _1MB)
  23 #define MI_SESSION_WORKING_SET_SIZE             (4 * _1MB)
  24 #define MI_SESSION_SIZE                         (MI_SESSION_VIEW_SIZE + \
  25                                                  MI_SESSION_POOL_SIZE + \
  26                                                  MI_SESSION_IMAGE_SIZE + \
  27                                                  MI_SESSION_WORKING_SET_SIZE)
  28
  29 #define MI_SYSTEM_VIEW_SIZE                     (16 * _1MB)
  30
  31 #define MI_SYSTEM_CACHE_WS_START                (PVOID)0xC0C00000
  32 #define MI_PAGED_POOL_START                     (PVOID)0xE1000000
  33 #define MI_NONPAGED_POOL_END                    (PVOID)0xFFBE0000
  34 #define MI_DEBUG_MAPPING                        (PVOID)0xFFBFF000
  35
  36 #define MI_SYSTEM_PTE_BASE                      (PVOID)MiAddressToPte(NULL)
  37
  38 #define MI_MIN_SECONDARY_COLORS                 8
  39 #define MI_SECONDARY_COLORS                     64
  40 #define MI_MAX_SECONDARY_COLORS                 1024
  41
  42 #define MI_MIN_ALLOCATION_FRAGMENT              (4 * _1KB)
  43 #define MI_ALLOCATION_FRAGMENT                  (64 * _1KB)
  44 #define MI_MAX_ALLOCATION_FRAGMENT              (2  * _1MB)
  45
  46 #define MM_HIGHEST_VAD_ADDRESS \
  47     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  48
  49 /* The range 0x10000->0x7FEFFFFF is reserved for the ROSMM MAREA Allocator */
  50 #define MI_LOWEST_VAD_ADDRESS                   (PVOID)0x7FF00000
  51
  52 #endif /* !_M_AMD64 */
  53
  54 /* Make the code cleaner with some definitions for size multiples */
  55 #define _1KB (1024u)
  56 #define _1MB (1024 * _1KB)
  57 #define _1GB (1024 * _1MB)
  58
  59 /* Area mapped by a PDE */
  60 #define PDE_MAPPED_VA  (PTE_COUNT * PAGE_SIZE)
  61
  62 /* Size of a page table */
  63 #define PT_SIZE  (PTE_COUNT * sizeof(MMPTE))
  64
  65 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
  66 #ifdef _M_IX86
  67 #define PD_COUNT  1
  68 #define PDE_COUNT 1024
  69 #define PTE_COUNT 1024
  70 #elif _M_ARM
  71 #define PD_COUNT  1
  72 #define PDE_COUNT 4096
  73 #define PTE_COUNT 256
  74 #else
  75 #define PD_COUNT  PPE_PER_PAGE
  76 #define PDE_COUNT PDE_PER_PAGE
  77 #define PTE_COUNT PTE_PER_PAGE
  78 #endif
  79
  80 #ifdef _M_IX86
  81 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_I386
  82 #elif _M_ARM
  83 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_ARM
  84 #elif _M_AMD64
  85 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_AMD64
  86 #else
  87 #error Define these please!
  88 #endif
  89
  90 //
  91 // Protection Bits part of the internal memory manager Protection Mask
  92 // Taken from http://www.reactos.org/wiki/Techwiki:Memory_management_in_the_Windows_XP_kernel
  93 // and public assertions.
  94 //
  95 #define MM_ZERO_ACCESS         0
  96 #define MM_READONLY            1
  97 #define MM_EXECUTE             2
  98 #define MM_EXECUTE_READ        3
  99 #define MM_READWRITE           4
 100 #define MM_WRITECOPY           5
 101 #define MM_EXECUTE_READWRITE   6
 102 #define MM_EXECUTE_WRITECOPY   7
 103 #define MM_NOCACHE             8
 104 #define MM_DECOMMIT            0x10
 105 #define MM_NOACCESS            (MM_DECOMMIT | MM_NOCACHE)
 106
 107 //
 108 // Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits
 109 // The Memory Manager's definition define the attributes that must be preserved
 110 // and these PTE definitions describe the attributes in the hardware sense. This
 111 // helps deal with hardware differences between the actual boolean expression of
 112 // the argument.
 113 //
 114 // For example, in the logical attributes, we want to express read-only as a flag
 115 // but on x86, it is writability that must be set. On the other hand, on x86, just
 116 // like in the kernel, it is disabling the caches that requires a special flag,
 117 // while on certain architectures such as ARM, it is enabling the cache which
 118 // requires a flag.
 119 //
 120 #if defined(_M_IX86) || defined(_M_AMD64)
 121 //
 122 // Access Flags
 123 //
 124 #define PTE_READONLY            0
 125 #define PTE_EXECUTE             0 // Not worrying about NX yet
 126 #define PTE_EXECUTE_READ        0 // Not worrying about NX yet
 127 #define PTE_READWRITE           0x2
 128 #define PTE_WRITECOPY           0x200
 129 #define PTE_EXECUTE_READWRITE   0x0
 130 #define PTE_EXECUTE_WRITECOPY   0x200
 131 #define PTE_PROTOTYPE           0x400
 132 //
 133 // Cache flags
 134 //
 135 #define PTE_ENABLE_CACHE        0
 136 #define PTE_DISABLE_CACHE       0x10
 137 #define PTE_WRITECOMBINED_CACHE 0x10
 138 #elif defined(_M_ARM)
 139 #else
 140 #error Define these please!
 141 #endif
 142
 143 extern const ULONG MmProtectToPteMask[32];
 144
 145 //
 146 // Assertions for session images, addresses, and PTEs
 147 //
 148 #define MI_IS_SESSION_IMAGE_ADDRESS(Address) \
 149     (((Address) >= MiSessionImageStart) && ((Address) < MiSessionImageEnd))
 150
 151 #define MI_IS_SESSION_ADDRESS(Address) \
 152     (((Address) >= MmSessionBase) && ((Address) < MiSessionSpaceEnd))
 153
 154 #define MI_IS_SESSION_PTE(Pte) \
 155     ((((PMMPTE)Pte) >= MiSessionBasePte) && (((PMMPTE)Pte) < MiSessionLastPte))
 156
 157 #define MI_IS_PAGE_TABLE_ADDRESS(Address) \
 158     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)PTE_TOP))
 159
 160 #define MI_IS_SYSTEM_PAGE_TABLE_ADDRESS(Address) \
 161     (((Address) >= (PVOID)MiAddressToPte(MmSystemRangeStart)) && ((Address) <= (PVOID)PTE_TOP))
 162
 163 #define MI_IS_PAGE_TABLE_OR_HYPER_ADDRESS(Address) \
 164     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)MmHyperSpaceEnd))
 165
 166 //
 167 // Corresponds to MMPTE_SOFTWARE.Protection
 168 //
 169 #ifdef _M_IX86
 170 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 171 #elif _M_ARM
 172 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 173 #elif _M_AMD64
 174 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 175 #else
 176 #error Define these please!
 177 #endif
 178
 179 //
 180 // Creates a software PTE with the given protection
 181 //
 182 #define MI_MAKE_SOFTWARE_PTE(p, x)          ((p)->u.Long = (x << MM_PTE_SOFTWARE_PROTECTION_BITS))
 183
 184 //
 185 // Marks a PTE as deleted
 186 //
 187 #define MI_SET_PFN_DELETED(x)               ((x)->PteAddress = (PMMPTE)((ULONG_PTR)(x)->PteAddress | 1))
 188 #define MI_IS_PFN_DELETED(x)                ((ULONG_PTR)((x)->PteAddress) & 1)
 189
 190 //
 191 // Special values for LoadedImports
 192 //
 193 #define MM_SYSLDR_NO_IMPORTS   (PVOID)0xFFFFFFFE
 194 #define MM_SYSLDR_BOOT_LOADED  (PVOID)0xFFFFFFFF
 195 #define MM_SYSLDR_SINGLE_ENTRY 0x1
 196
 197 //
 198 // PFN List Sentinel
 199 //
 200 #define LIST_HEAD 0xFFFFFFFF
 201
 202 //
 203 // Special IRQL value (found in assertions)
 204 //
 205 #define MM_NOIRQL (KIRQL)0xFFFFFFFF
 206
 207 //
 208 // FIXFIX: These should go in ex.h after the pool merge
 209 //
 210 #ifdef _M_AMD64
 211 #define POOL_BLOCK_SIZE 16
 212 #else
 213 #define POOL_BLOCK_SIZE  8
 214 #endif
 215 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / POOL_BLOCK_SIZE)
 216 #define BASE_POOL_TYPE_MASK 1
 217 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + POOL_BLOCK_SIZE))
 218
 219 typedef struct _POOL_DESCRIPTOR
 220 {
 221     POOL_TYPE PoolType;
 222     ULONG PoolIndex;
 223     ULONG RunningAllocs;
 224     ULONG RunningDeAllocs;
 225     ULONG TotalPages;
 226     ULONG TotalBigPages;
 227     ULONG Threshold;
 228     PVOID LockAddress;
 229     PVOID PendingFrees;
 230     LONG PendingFreeDepth;
 231     SIZE_T TotalBytes;
 232     SIZE_T Spare0;
 233     LIST_ENTRY ListHeads[POOL_LISTS_PER_PAGE];
 234 } POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
 235
 236 typedef struct _POOL_HEADER
 237 {
 238     union
 239     {
 240         struct
 241         {
 242 #ifdef _M_AMD64
 243             ULONG PreviousSize:8;
 244             ULONG PoolIndex:8;
 245             ULONG BlockSize:8;
 246             ULONG PoolType:8;
 247 #else
 248             USHORT PreviousSize:9;
 249             USHORT PoolIndex:7;
 250             USHORT BlockSize:9;
 251             USHORT PoolType:7;
 252 #endif
 253         };
 254         ULONG Ulong1;
 255     };
 256 #ifdef _M_AMD64
 257     ULONG PoolTag;
 258 #endif
 259     union
 260     {
 261 #ifdef _M_AMD64
 262         PEPROCESS ProcessBilled;
 263 #else
 264         ULONG PoolTag;
 265 #endif
 266         struct
 267         {
 268             USHORT AllocatorBackTraceIndex;
 269             USHORT PoolTagHash;
 270         };
 271     };
 272 } POOL_HEADER, *PPOOL_HEADER;
 273
 274 C_ASSERT(sizeof(POOL_HEADER) == POOL_BLOCK_SIZE);
 275 C_ASSERT(POOL_BLOCK_SIZE == sizeof(LIST_ENTRY));
 276
 277 extern ULONG ExpNumberOfPagedPools;
 278 extern POOL_DESCRIPTOR NonPagedPoolDescriptor;
 279 extern PPOOL_DESCRIPTOR ExpPagedPoolDescriptor[16 + 1];
 280 extern PVOID PoolTrackTable;
 281
 282 //
 283 // END FIXFIX
 284 //
 285
 286 typedef struct _MI_LARGE_PAGE_DRIVER_ENTRY
 287 {
 288     LIST_ENTRY Links;
 289     UNICODE_STRING BaseName;
 290 } MI_LARGE_PAGE_DRIVER_ENTRY, *PMI_LARGE_PAGE_DRIVER_ENTRY;
 291
 292 typedef enum _MMSYSTEM_PTE_POOL_TYPE
 293 {
 294     SystemPteSpace,
 295     NonPagedPoolExpansion,
 296     MaximumPtePoolTypes
 297 } MMSYSTEM_PTE_POOL_TYPE;
 298
 299 typedef enum _MI_PFN_CACHE_ATTRIBUTE
 300 {
 301     MiNonCached,
 302     MiCached,
 303     MiWriteCombined,
 304     MiNotMapped
 305 } MI_PFN_CACHE_ATTRIBUTE, *PMI_PFN_CACHE_ATTRIBUTE;
 306
 307 typedef struct _PHYSICAL_MEMORY_RUN
 308 {
 309     ULONG BasePage;
 310     ULONG PageCount;
 311 } PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
 312
 313 typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
 314 {
 315     ULONG NumberOfRuns;
 316     ULONG NumberOfPages;
 317     PHYSICAL_MEMORY_RUN Run[1];
 318 } PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
 319
 320 typedef struct _MMCOLOR_TABLES
 321 {
 322     PFN_NUMBER Flink;
 323     PVOID Blink;
 324     PFN_NUMBER Count;
 325 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 326
 327 typedef struct _MI_LARGE_PAGE_RANGES
 328 {
 329     PFN_NUMBER StartFrame;
 330     PFN_NUMBER LastFrame;
 331 } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
 332
 333 extern MMPTE HyperTemplatePte;
 334 extern MMPDE ValidKernelPde;
 335 extern MMPTE ValidKernelPte;
 336 extern MMPDE DemandZeroPde;
 337 extern MMPTE PrototypePte;
 338 extern BOOLEAN MmLargeSystemCache;
 339 extern BOOLEAN MmZeroPageFile;
 340 extern BOOLEAN MmProtectFreedNonPagedPool;
 341 extern BOOLEAN MmTrackLockedPages;
 342 extern BOOLEAN MmTrackPtes;
 343 extern BOOLEAN MmDynamicPfn;
 344 extern BOOLEAN MmMirroring;
 345 extern BOOLEAN MmMakeLowMemory;
 346 extern BOOLEAN MmEnforceWriteProtection;
 347 extern SIZE_T MmAllocationFragment;
 348 extern ULONG MmConsumedPoolPercentage;
 349 extern ULONG MmVerifyDriverBufferType;
 350 extern ULONG MmVerifyDriverLevel;
 351 extern WCHAR MmVerifyDriverBuffer[512];
 352 extern WCHAR MmLargePageDriverBuffer[512];
 353 extern LIST_ENTRY MiLargePageDriverList;
 354 extern BOOLEAN MiLargePageAllDrivers;
 355 extern ULONG MmVerifyDriverBufferLength;
 356 extern ULONG MmLargePageDriverBufferLength;
 357 extern SIZE_T MmSizeOfNonPagedPoolInBytes;
 358 extern SIZE_T MmMaximumNonPagedPoolInBytes;
 359 extern PFN_NUMBER MmMaximumNonPagedPoolInPages;
 360 extern PFN_NUMBER MmSizeOfPagedPoolInPages;
 361 extern PVOID MmNonPagedSystemStart;
 362 extern PVOID MmNonPagedPoolStart;
 363 extern PVOID MmNonPagedPoolExpansionStart;
 364 extern PVOID MmNonPagedPoolEnd;
 365 extern SIZE_T MmSizeOfPagedPoolInBytes;
 366 extern PVOID MmPagedPoolStart;
 367 extern PVOID MmPagedPoolEnd;
 368 extern PVOID MmSessionBase;
 369 extern SIZE_T MmSessionSize;
 370 extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
 371 extern PMMPTE MiFirstReservedZeroingPte;
 372 extern MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType];
 373 extern PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
 374 extern SIZE_T MmBootImageSize;
 375 extern PMMPTE MmSystemPtesStart[MaximumPtePoolTypes];
 376 extern PMMPTE MmSystemPtesEnd[MaximumPtePoolTypes];
 377 extern PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
 378 extern MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
 379 extern ULONG_PTR MxPfnAllocation;
 380 extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
 381 extern RTL_BITMAP MiPfnBitMap;
 382 extern KGUARDED_MUTEX MmPagedPoolMutex;
 383 extern PVOID MmPagedPoolStart;
 384 extern PVOID MmPagedPoolEnd;
 385 extern PVOID MmNonPagedSystemStart;
 386 extern PVOID MiSystemViewStart;
 387 extern SIZE_T MmSystemViewSize;
 388 extern PVOID MmSessionBase;
 389 extern PVOID MiSessionSpaceEnd;
 390 extern PMMPTE MiSessionImagePteStart;
 391 extern PMMPTE MiSessionImagePteEnd;
 392 extern PMMPTE MiSessionBasePte;
 393 extern PMMPTE MiSessionLastPte;
 394 extern SIZE_T MmSizeOfPagedPoolInBytes;
 395 extern PMMPTE MmSystemPagePtes;
 396 extern PVOID MmSystemCacheStart;
 397 extern PVOID MmSystemCacheEnd;
 398 extern MMSUPPORT MmSystemCacheWs;
 399 extern SIZE_T MmAllocatedNonPagedPool;
 400 extern ULONG_PTR MmSubsectionBase;
 401 extern ULONG MmSpecialPoolTag;
 402 extern PVOID MmHyperSpaceEnd;
 403 extern PMMWSL MmSystemCacheWorkingSetList;
 404 extern SIZE_T MmMinimumNonPagedPoolSize;
 405 extern ULONG MmMinAdditionNonPagedPoolPerMb;
 406 extern SIZE_T MmDefaultMaximumNonPagedPool;
 407 extern ULONG MmMaxAdditionNonPagedPoolPerMb;
 408 extern ULONG MmSecondaryColors;
 409 extern ULONG MmSecondaryColorMask;
 410 extern ULONG_PTR MmNumberOfSystemPtes;
 411 extern ULONG MmMaximumNonPagedPoolPercent;
 412 extern ULONG MmLargeStackSize;
 413 extern PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
 414 extern ULONG MmProductType;
 415 extern MM_SYSTEMSIZE MmSystemSize;
 416 extern PKEVENT MiLowMemoryEvent;
 417 extern PKEVENT MiHighMemoryEvent;
 418 extern PKEVENT MiLowPagedPoolEvent;
 419 extern PKEVENT MiHighPagedPoolEvent;
 420 extern PKEVENT MiLowNonPagedPoolEvent;
 421 extern PKEVENT MiHighNonPagedPoolEvent;
 422 extern PFN_NUMBER MmLowMemoryThreshold;
 423 extern PFN_NUMBER MmHighMemoryThreshold;
 424 extern PFN_NUMBER MiLowPagedPoolThreshold;
 425 extern PFN_NUMBER MiHighPagedPoolThreshold;
 426 extern PFN_NUMBER MiLowNonPagedPoolThreshold;
 427 extern PFN_NUMBER MiHighNonPagedPoolThreshold;
 428 extern PFN_NUMBER MmMinimumFreePages;
 429 extern PFN_NUMBER MmPlentyFreePages;
 430 extern PFN_NUMBER MiExpansionPoolPagesInitialCharge;
 431 extern PFN_NUMBER MmResidentAvailablePages;
 432 extern PFN_NUMBER MmResidentAvailableAtInit;
 433 extern ULONG MmTotalFreeSystemPtes[MaximumPtePoolTypes];
 434 extern PFN_NUMBER MmTotalSystemDriverPages;
 435 extern PVOID MiSessionImageStart;
 436 extern PVOID MiSessionImageEnd;
 437 extern PMMPTE MiHighestUserPte;
 438 extern PMMPDE MiHighestUserPde;
 439 extern PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
 440 extern PMMPTE MmSharedUserDataPte;
 441 extern LIST_ENTRY MmProcessList;
 442
 443 #define MI_PFN_TO_PFNENTRY(x)     (&MmPfnDatabase[1][x])
 444 #define MI_PFNENTRY_TO_PFN(x)     (x - MmPfnDatabase[1])
 445
 446 //
 447 // Figures out the hardware bits for a PTE
 448 //
 449 ULONG
 450 FORCEINLINE
 451 MiDetermineUserGlobalPteMask(IN PMMPTE PointerPte)
 452 {
 453     MMPTE TempPte;
 454
 455     /* Start fresh */
 456     TempPte.u.Long = 0;
 457
 458     /* Make it valid and accessed */
 459     TempPte.u.Hard.Valid = TRUE;
 460     TempPte.u.Hard.Accessed = TRUE;
 461
 462     /* Is this for user-mode? */
 463     if ((PointerPte <= MiHighestUserPte) ||
 464         ((PointerPte >= MiAddressToPde(NULL)) && (PointerPte <= MiHighestUserPde)))
 465     {
 466         /* Set the owner bit */
 467         TempPte.u.Hard.Owner = TRUE;
 468     }
 469
 470     /* FIXME: We should also set the global bit */
 471
 472     /* Return the protection */
 473     return TempPte.u.Long;
 474 }
 475
 476 //
 477 // Creates a valid kernel PTE with the given protection
 478 //
 479 FORCEINLINE
 480 VOID
 481 MI_MAKE_HARDWARE_PTE_KERNEL(IN PMMPTE NewPte,
 482                             IN PMMPTE MappingPte,
 483                             IN ULONG ProtectionMask,
 484                             IN PFN_NUMBER PageFrameNumber)
 485 {
 486     /* Only valid for kernel, non-session PTEs */
 487     ASSERT(MappingPte > MiHighestUserPte);
 488     ASSERT(!MI_IS_SESSION_PTE(MappingPte));
 489     ASSERT((MappingPte < (PMMPTE)PDE_BASE) || (MappingPte > (PMMPTE)PDE_TOP));
 490
 491     /* Start fresh */
 492     *NewPte = ValidKernelPte;
 493
 494     /* Set the protection and page */
 495     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 496     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 497 }
 498
 499 //
 500 // Creates a valid PTE with the given protection
 501 //
 502 FORCEINLINE
 503 VOID
 504 MI_MAKE_HARDWARE_PTE(IN PMMPTE NewPte,
 505                      IN PMMPTE MappingPte,
 506                      IN ULONG ProtectionMask,
 507                      IN PFN_NUMBER PageFrameNumber)
 508 {
 509     /* Set the protection and page */
 510     NewPte->u.Long = MiDetermineUserGlobalPteMask(MappingPte);
 511     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 512     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 513 }
 514
 515 //
 516 // Creates a valid user PTE with the given protection
 517 //
 518 FORCEINLINE
 519 VOID
 520 MI_MAKE_HARDWARE_PTE_USER(IN PMMPTE NewPte,
 521                           IN PMMPTE MappingPte,
 522                           IN ULONG ProtectionMask,
 523                           IN PFN_NUMBER PageFrameNumber)
 524 {
 525     /* Only valid for kernel, non-session PTEs */
 526     ASSERT(MappingPte <= MiHighestUserPte);
 527
 528     /* Start fresh */
 529     *NewPte = ValidKernelPte;
 530
 531     /* Set the protection and page */
 532     NewPte->u.Hard.Owner = TRUE;
 533     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 534     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 535 }
 536
 537 //
 538 // Returns if the page is physically resident (ie: a large page)
 539 // FIXFIX: CISC/x86 only?
 540 //
 541 FORCEINLINE
 542 BOOLEAN
 543 MI_IS_PHYSICAL_ADDRESS(IN PVOID Address)
 544 {
 545     PMMPDE PointerPde;
 546
 547     /* Large pages are never paged out, always physically resident */
 548     PointerPde = MiAddressToPde(Address);
 549     return ((PointerPde->u.Hard.LargePage) && (PointerPde->u.Hard.Valid));
 550 }
 551
 552 //
 553 // Writes a valid PTE
 554 //
 555 VOID
 556 FORCEINLINE
 557 MI_WRITE_VALID_PTE(IN PMMPTE PointerPte,
 558                    IN MMPTE TempPte)
 559 {
 560     /* Write the valid PTE */
 561     ASSERT(PointerPte->u.Hard.Valid == 0);
 562     ASSERT(TempPte.u.Hard.Valid == 1);
 563     *PointerPte = TempPte;
 564 }
 565
 566 //
 567 // Writes an invalid PTE
 568 //
 569 VOID
 570 FORCEINLINE
 571 MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte,
 572                      IN MMPTE InvalidPte)
 573 {
 574     /* Write the invalid PTE */
 575     ASSERT(InvalidPte.u.Hard.Valid == 0);
 576     *PointerPte = InvalidPte;
 577 }
 578
 579 //
 580 // Checks if the thread already owns a working set
 581 //
 582 FORCEINLINE
 583 BOOLEAN
 584 MM_ANY_WS_LOCK_HELD(IN PETHREAD Thread)
 585 {
 586     /* If any of these are held, return TRUE */
 587     return ((Thread->OwnsProcessWorkingSetExclusive) ||
 588             (Thread->OwnsProcessWorkingSetShared) ||
 589             (Thread->OwnsSystemWorkingSetExclusive) ||
 590             (Thread->OwnsSystemWorkingSetShared) ||
 591             (Thread->OwnsSessionWorkingSetExclusive) ||
 592             (Thread->OwnsSessionWorkingSetShared));
 593 }
 594
 595 //
 596 // Checks if the process owns the working set lock
 597 //
 598 FORCEINLINE
 599 BOOLEAN
 600 MI_WS_OWNER(IN PEPROCESS Process)
 601 {
 602     /* Check if this process is the owner, and that the thread owns the WS */
 603     return ((KeGetCurrentThread()->ApcState.Process == &Process->Pcb) &&
 604             ((PsGetCurrentThread()->OwnsProcessWorkingSetExclusive) ||
 605              (PsGetCurrentThread()->OwnsProcessWorkingSetShared)));
 606 }
 607
 608 //
 609 // Locks the working set for the given process
 610 //
 611 FORCEINLINE
 612 VOID
 613 MiLockProcessWorkingSet(IN PEPROCESS Process,
 614                         IN PETHREAD Thread)
 615 {
 616     /* Shouldn't already be owning the process working set */
 617     ASSERT(Thread->OwnsProcessWorkingSetShared == FALSE);
 618     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 619
 620     /* Block APCs, make sure that still nothing is already held */
 621     KeEnterGuardedRegion();
 622     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 623
 624     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 625
 626     /* FIXME: This also can't be checked because Vm is used by MAREAs) */
 627     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 628
 629     /* Okay, now we can own it exclusively */
 630     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 631     Thread->OwnsProcessWorkingSetExclusive = TRUE;
 632 }
 633
 634 //
 635 // Unlocks the working set for the given process
 636 //
 637 FORCEINLINE
 638 VOID
 639 MiUnlockProcessWorkingSet(IN PEPROCESS Process,
 640                           IN PETHREAD Thread)
 641 {
 642     /* Make sure this process really is owner, and it was a safe acquisition */
 643     ASSERT(MI_WS_OWNER(Process));
 644     /* This can't be checked because Vm is used by MAREAs) */
 645     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 646
 647     /* The thread doesn't own it anymore */
 648     ASSERT(Thread->OwnsProcessWorkingSetExclusive == TRUE);
 649     Thread->OwnsProcessWorkingSetExclusive = FALSE;
 650
 651     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 652
 653     /* Unblock APCs */
 654     KeLeaveGuardedRegion();
 655 }
 656
 657 //
 658 // Locks the working set
 659 //
 660 FORCEINLINE
 661 VOID
 662 MiLockWorkingSet(IN PETHREAD Thread,
 663                  IN PMMSUPPORT WorkingSet)
 664 {
 665     /* Block APCs */
 666     KeEnterGuardedRegion();
 667
 668     /* Working set should be in global memory */
 669     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 670
 671     /* Thread shouldn't already be owning something */
 672     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 673
 674     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 675
 676     /* Which working set is this? */
 677     if (WorkingSet == &MmSystemCacheWs)
 678     {
 679         /* Own the system working set */
 680         ASSERT((Thread->OwnsSystemWorkingSetExclusive == FALSE) &&
 681                (Thread->OwnsSystemWorkingSetShared == FALSE));
 682         Thread->OwnsSystemWorkingSetExclusive = TRUE;
 683     }
 684     else if (WorkingSet->Flags.SessionSpace)
 685     {
 686         /* We don't implement this yet */
 687         UNIMPLEMENTED;
 688         while (TRUE);
 689     }
 690     else
 691     {
 692         /* Own the process working set */
 693         ASSERT((Thread->OwnsProcessWorkingSetExclusive == FALSE) &&
 694                (Thread->OwnsProcessWorkingSetShared == FALSE));
 695         Thread->OwnsProcessWorkingSetExclusive = TRUE;
 696     }
 697 }
 698
 699 //
 700 // Unlocks the working set
 701 //
 702 FORCEINLINE
 703 VOID
 704 MiUnlockWorkingSet(IN PETHREAD Thread,
 705                    IN PMMSUPPORT WorkingSet)
 706 {
 707     /* Working set should be in global memory */
 708     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 709
 710     /* Which working set is this? */
 711     if (WorkingSet == &MmSystemCacheWs)
 712     {
 713         /* Release the system working set */
 714         ASSERT((Thread->OwnsSystemWorkingSetExclusive == TRUE) ||
 715                (Thread->OwnsSystemWorkingSetShared == TRUE));
 716         Thread->OwnsSystemWorkingSetExclusive = FALSE;
 717     }
 718     else if (WorkingSet->Flags.SessionSpace)
 719     {
 720         /* We don't implement this yet */
 721         UNIMPLEMENTED;
 722         while (TRUE);
 723     }
 724     else
 725     {
 726         /* Release the process working set */
 727         ASSERT((Thread->OwnsProcessWorkingSetExclusive) ||
 728                (Thread->OwnsProcessWorkingSetShared));
 729         Thread->OwnsProcessWorkingSetExclusive = FALSE;
 730     }
 731
 732     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 733
 734     /* Unblock APCs */
 735     KeLeaveGuardedRegion();
 736 }
 737
 738 NTSTATUS
 739 NTAPI
 740 MmArmInitSystem(
 741     IN ULONG Phase,
 742     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 743 );
 744
 745 NTSTATUS
 746 NTAPI
 747 MiInitMachineDependent(
 748     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 749 );
 750
 751 VOID
 752 NTAPI
 753 MiComputeColorInformation(
 754     VOID
 755 );
 756
 757 VOID
 758 NTAPI
 759 MiMapPfnDatabase(
 760     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 761 );
 762
 763 VOID
 764 NTAPI
 765 MiInitializeColorTables(
 766     VOID
 767 );
 768
 769 VOID
 770 NTAPI
 771 MiInitializePfnDatabase(
 772     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 773 );
 774
 775 BOOLEAN
 776 NTAPI
 777 MiInitializeMemoryEvents(
 778     VOID
 779 );
 780
 781 PFN_NUMBER
 782 NTAPI
 783 MxGetNextPage(
 784     IN PFN_NUMBER PageCount
 785 );
 786
 787 PPHYSICAL_MEMORY_DESCRIPTOR
 788 NTAPI
 789 MmInitializeMemoryLimits(
 790     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 791     IN PBOOLEAN IncludeType
 792 );
 793
 794 PFN_NUMBER
 795 NTAPI
 796 MiPagesInLoaderBlock(
 797     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 798     IN PBOOLEAN IncludeType
 799 );
 800
 801 VOID
 802 FASTCALL
 803 MiSyncARM3WithROS(
 804     IN PVOID AddressStart,
 805     IN PVOID AddressEnd
 806 );
 807
 808 NTSTATUS
 809 NTAPI
 810 MmArmAccessFault(
 811     IN BOOLEAN StoreInstruction,
 812     IN PVOID Address,
 813     IN KPROCESSOR_MODE Mode,
 814     IN PVOID TrapInformation
 815 );
 816
 817 NTSTATUS
 818 FASTCALL
 819 MiCheckPdeForPagedPool(
 820     IN PVOID Address
 821 );
 822
 823 VOID
 824 NTAPI
 825 MiInitializeNonPagedPool(
 826     VOID
 827 );
 828
 829 VOID
 830 NTAPI
 831 MiInitializeNonPagedPoolThresholds(
 832     VOID
 833 );
 834
 835 VOID
 836 NTAPI
 837 MiInitializePoolEvents(
 838     VOID
 839 );
 840
 841 VOID                      //
 842 NTAPI                     //
 843 InitializePool(           //
 844     IN POOL_TYPE PoolType,// FIXFIX: This should go in ex.h after the pool merge
 845     IN ULONG Threshold    //
 846 );                        //
 847
 848 VOID
 849 NTAPI
 850 MiInitializeSystemPtes(
 851     IN PMMPTE StartingPte,
 852     IN ULONG NumberOfPtes,
 853     IN MMSYSTEM_PTE_POOL_TYPE PoolType
 854 );
 855
 856 PMMPTE
 857 NTAPI
 858 MiReserveSystemPtes(
 859     IN ULONG NumberOfPtes,
 860     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 861 );
 862
 863 VOID
 864 NTAPI
 865 MiReleaseSystemPtes(
 866     IN PMMPTE StartingPte,
 867     IN ULONG NumberOfPtes,
 868     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 869 );
 870
 871
 872 PFN_NUMBER
 873 NTAPI
 874 MiFindContiguousPages(
 875     IN PFN_NUMBER LowestPfn,
 876     IN PFN_NUMBER HighestPfn,
 877     IN PFN_NUMBER BoundaryPfn,
 878     IN PFN_NUMBER SizeInPages,
 879     IN MEMORY_CACHING_TYPE CacheType
 880 );
 881
 882 PVOID
 883 NTAPI
 884 MiCheckForContiguousMemory(
 885     IN PVOID BaseAddress,
 886     IN PFN_NUMBER BaseAddressPages,
 887     IN PFN_NUMBER SizeInPages,
 888     IN PFN_NUMBER LowestPfn,
 889     IN PFN_NUMBER HighestPfn,
 890     IN PFN_NUMBER BoundaryPfn,
 891     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
 892 );
 893
 894 PMDL
 895 NTAPI
 896 MiAllocatePagesForMdl(
 897     IN PHYSICAL_ADDRESS LowAddress,
 898     IN PHYSICAL_ADDRESS HighAddress,
 899     IN PHYSICAL_ADDRESS SkipBytes,
 900     IN SIZE_T TotalBytes,
 901     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
 902     IN ULONG Flags
 903 );
 904
 905 PVOID
 906 NTAPI
 907 MiMapLockedPagesInUserSpace(
 908     IN PMDL Mdl,
 909     IN PVOID BaseVa,
 910     IN MEMORY_CACHING_TYPE CacheType,
 911     IN PVOID BaseAddress
 912 );
 913
 914 VOID
 915 NTAPI
 916 MiUnmapLockedPagesInUserSpace(
 917     IN PVOID BaseAddress,
 918     IN PMDL Mdl
 919 );
 920
 921 VOID
 922 NTAPI
 923 MiInsertPageInList(
 924     IN PMMPFNLIST ListHead,
 925     IN PFN_NUMBER PageFrameIndex
 926 );
 927
 928 VOID
 929 NTAPI
 930 MiUnlinkFreeOrZeroedPage(
 931     IN PMMPFN Entry
 932 );
 933
 934 PMMPFN
 935 NTAPI
 936 MiRemoveHeadList(
 937     IN PMMPFNLIST ListHead
 938 );
 939
 940 PFN_NUMBER
 941 NTAPI
 942 MiAllocatePfn(
 943     IN PMMPTE PointerPte,
 944     IN ULONG Protection
 945 );
 946
 947 VOID
 948 NTAPI
 949 MiInitializePfn(
 950     IN PFN_NUMBER PageFrameIndex,
 951     IN PMMPTE PointerPte,
 952     IN BOOLEAN Modified
 953 );
 954
 955 VOID
 956 NTAPI
 957 MiInitializePfnForOtherProcess(
 958     IN PFN_NUMBER PageFrameIndex,
 959     IN PMMPTE PointerPte,
 960     IN PFN_NUMBER PteFrame
 961 );
 962
 963 VOID
 964 NTAPI
 965 MiDecrementShareCount(
 966     IN PMMPFN Pfn1,
 967     IN PFN_NUMBER PageFrameIndex
 968 );
 969
 970 PFN_NUMBER
 971 NTAPI
 972 MiRemoveAnyPage(
 973     IN ULONG Color
 974 );
 975
 976 PFN_NUMBER
 977 NTAPI
 978 MiRemoveZeroPage(
 979     IN ULONG Color
 980 );
 981
 982 VOID
 983 NTAPI
 984 MiZeroPhysicalPage(
 985     IN PFN_NUMBER PageFrameIndex
 986 );
 987
 988 VOID
 989 NTAPI
 990 MiInsertPageInFreeList(
 991     IN PFN_NUMBER PageFrameIndex
 992 );
 993
 994 PFN_NUMBER
 995 NTAPI
 996 MiDeleteSystemPageableVm(
 997     IN PMMPTE PointerPte,
 998     IN PFN_NUMBER PageCount,
 999     IN ULONG Flags,
1000     OUT PPFN_NUMBER ValidPages
1001 );
1002
1003 PLDR_DATA_TABLE_ENTRY
1004 NTAPI
1005 MiLookupDataTableEntry(
1006     IN PVOID Address
1007 );
1008
1009 VOID
1010 NTAPI
1011 MiInitializeDriverLargePageList(
1012     VOID
1013 );
1014
1015 VOID
1016 NTAPI
1017 MiInitializeLargePageSupport(
1018     VOID
1019 );
1020
1021 VOID
1022 NTAPI
1023 MiSyncCachedRanges(
1024     VOID
1025 );
1026
1027 BOOLEAN
1028 NTAPI
1029 MiIsPfnInUse(
1030     IN PMMPFN Pfn1
1031 );
1032
1033 PMMVAD
1034 NTAPI
1035 MiLocateAddress(
1036     IN PVOID VirtualAddress
1037 );
1038
1039 PMMADDRESS_NODE
1040 NTAPI
1041 MiCheckForConflictingNode(
1042     IN ULONG_PTR StartVpn,
1043     IN ULONG_PTR EndVpn,
1044     IN PMM_AVL_TABLE Table
1045 );
1046
1047 TABLE_SEARCH_RESULT
1048 NTAPI
1049 MiFindEmptyAddressRangeDownTree(
1050     IN SIZE_T Length,
1051     IN ULONG_PTR BoundaryAddress,
1052     IN ULONG_PTR Alignment,
1053     IN PMM_AVL_TABLE Table,
1054     OUT PULONG_PTR Base,
1055     OUT PMMADDRESS_NODE *Parent
1056 );
1057
1058 VOID
1059 NTAPI
1060 MiInsertNode(
1061     IN PMM_AVL_TABLE Table,
1062     IN PMMADDRESS_NODE NewNode,
1063     PMMADDRESS_NODE Parent,
1064     TABLE_SEARCH_RESULT Result
1065 );
1066
1067 VOID
1068 NTAPI
1069 MiRemoveNode(
1070     IN PMMADDRESS_NODE Node,
1071     IN PMM_AVL_TABLE Table
1072 );
1073
1074 PMMADDRESS_NODE
1075 NTAPI
1076 MiGetPreviousNode(
1077     IN PMMADDRESS_NODE Node
1078 );
1079
1080 PMMADDRESS_NODE
1081 NTAPI
1082 MiGetNextNode(
1083     IN PMMADDRESS_NODE Node
1084 );
1085
1086 /* EOF */