reactos/ntoskrnl/mm/ARM3/miarm.h

   1 /*
   2  * PROJECT:         ReactOS Kernel
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            ntoskrnl/mm/ARM3/miarm.h
   5  * PURPOSE:         ARM Memory Manager Header
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 #ifndef _M_AMD64
  10
  11 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING   ((255 * _1MB) >> PAGE_SHIFT)
  12 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING          ((19 * _1MB) >> PAGE_SHIFT)
  13 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST           ((32 * _1MB) >> PAGE_SHIFT)
  14 #define MI_MAX_INIT_NONPAGED_POOL_SIZE          (128 * _1MB)
  15 #define MI_MAX_NONPAGED_POOL_SIZE               (128 * _1MB)
  16 #define MI_MAX_FREE_PAGE_LISTS                  4
  17
  18 #define MI_MIN_INIT_PAGED_POOLSIZE              (32 * _1MB)
  19
  20 #define MI_SESSION_VIEW_SIZE                    (20 * _1MB)
  21 #define MI_SESSION_POOL_SIZE                    (16 * _1MB)
  22 #define MI_SESSION_IMAGE_SIZE                   (8 * _1MB)
  23 #define MI_SESSION_WORKING_SET_SIZE             (4 * _1MB)
  24 #define MI_SESSION_SIZE                         (MI_SESSION_VIEW_SIZE + \
  25                                                  MI_SESSION_POOL_SIZE + \
  26                                                  MI_SESSION_IMAGE_SIZE + \
  27                                                  MI_SESSION_WORKING_SET_SIZE)
  28
  29 #define MI_SYSTEM_VIEW_SIZE                     (16 * _1MB)
  30
  31 #define MI_SYSTEM_CACHE_WS_START                (PVOID)0xC0C00000
  32 #define MI_PAGED_POOL_START                     (PVOID)0xE1000000
  33 #define MI_NONPAGED_POOL_END                    (PVOID)0xFFBE0000
  34 #define MI_DEBUG_MAPPING                        (PVOID)0xFFBFF000
  35
  36 #define MI_SYSTEM_PTE_BASE                      (PVOID)MiAddressToPte(NULL)
  37
  38 #define MI_MIN_SECONDARY_COLORS                 8
  39 #define MI_SECONDARY_COLORS                     64
  40 #define MI_MAX_SECONDARY_COLORS                 1024
  41
  42 #define MI_MIN_ALLOCATION_FRAGMENT              (4 * _1KB)
  43 #define MI_ALLOCATION_FRAGMENT                  (64 * _1KB)
  44 #define MI_MAX_ALLOCATION_FRAGMENT              (2  * _1MB)
  45
  46 #define MM_HIGHEST_VAD_ADDRESS \
  47     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  48 #define MI_LOWEST_VAD_ADDRESS                   (PVOID)MM_LOWEST_USER_ADDRESS
  49
  50 #endif /* !_M_AMD64 */
  51
  52 /* Make the code cleaner with some definitions for size multiples */
  53 #define _1KB (1024u)
  54 #define _1MB (1024 * _1KB)
  55 #define _1GB (1024 * _1MB)
  56
  57 /* Everyone loves 64K */
  58 #define _64K (64 * _1KB)
  59
  60 /* Area mapped by a PDE */
  61 #define PDE_MAPPED_VA  (PTE_COUNT * PAGE_SIZE)
  62
  63 /* Size of a page table */
  64 #define PT_SIZE  (PTE_COUNT * sizeof(MMPTE))
  65
  66 /* Size of a page directory */
  67 #define PD_SIZE  (PDE_COUNT * sizeof(MMPDE))
  68
  69 /* Size of all page directories for a process */
  70 #define SYSTEM_PD_SIZE (PD_COUNT * PD_SIZE)
  71
  72 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
  73 #ifdef _M_IX86
  74 #define PD_COUNT  1
  75 #define PDE_COUNT 1024
  76 #define PTE_COUNT 1024
  77 C_ASSERT(SYSTEM_PD_SIZE == PAGE_SIZE);
  78 #elif _M_ARM
  79 #define PD_COUNT  1
  80 #define PDE_COUNT 4096
  81 #define PTE_COUNT 256
  82 #else
  83 #define PD_COUNT  PPE_PER_PAGE
  84 #define PDE_COUNT PDE_PER_PAGE
  85 #define PTE_COUNT PTE_PER_PAGE
  86 #endif
  87
  88 #ifdef _M_IX86
  89 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_I386
  90 #elif _M_ARM
  91 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_ARM
  92 #elif _M_AMD64
  93 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_AMD64
  94 #else
  95 #error Define these please!
  96 #endif
  97
  98 //
  99 // Protection Bits part of the internal memory manager Protection Mask
 100 // Taken from http://www.reactos.org/wiki/Techwiki:Memory_management_in_the_Windows_XP_kernel
 101 // and public assertions.
 102 //
 103 #define MM_ZERO_ACCESS         0
 104 #define MM_READONLY            1
 105 #define MM_EXECUTE             2
 106 #define MM_EXECUTE_READ        3
 107 #define MM_READWRITE           4
 108 #define MM_WRITECOPY           5
 109 #define MM_EXECUTE_READWRITE   6
 110 #define MM_EXECUTE_WRITECOPY   7
 111 #define MM_NOCACHE             8
 112 #define MM_DECOMMIT            0x10
 113 #define MM_NOACCESS            (MM_DECOMMIT | MM_NOCACHE)
 114 #define MM_INVALID_PROTECTION  0xFFFFFFFF
 115
 116 //
 117 // Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits
 118 // The Memory Manager's definition define the attributes that must be preserved
 119 // and these PTE definitions describe the attributes in the hardware sense. This
 120 // helps deal with hardware differences between the actual boolean expression of
 121 // the argument.
 122 //
 123 // For example, in the logical attributes, we want to express read-only as a flag
 124 // but on x86, it is writability that must be set. On the other hand, on x86, just
 125 // like in the kernel, it is disabling the caches that requires a special flag,
 126 // while on certain architectures such as ARM, it is enabling the cache which
 127 // requires a flag.
 128 //
 129 #if defined(_M_IX86) || defined(_M_AMD64)
 130 //
 131 // Access Flags
 132 //
 133 #define PTE_READONLY            0
 134 #define PTE_EXECUTE             0 // Not worrying about NX yet
 135 #define PTE_EXECUTE_READ        0 // Not worrying about NX yet
 136 #define PTE_READWRITE           0x2
 137 #define PTE_WRITECOPY           0x200
 138 #define PTE_EXECUTE_READWRITE   0x0
 139 #define PTE_EXECUTE_WRITECOPY   0x200
 140 #define PTE_PROTOTYPE           0x400
 141 //
 142 // Cache flags
 143 //
 144 #define PTE_ENABLE_CACHE        0
 145 #define PTE_DISABLE_CACHE       0x10
 146 #define PTE_WRITECOMBINED_CACHE 0x10
 147 #elif defined(_M_ARM)
 148 #else
 149 #error Define these please!
 150 #endif
 151
 152 extern const ULONG MmProtectToPteMask[32];
 153 extern const ULONG MmProtectToValue[32];
 154
 155 //
 156 // Assertions for session images, addresses, and PTEs
 157 //
 158 #define MI_IS_SESSION_IMAGE_ADDRESS(Address) \
 159     (((Address) >= MiSessionImageStart) && ((Address) < MiSessionImageEnd))
 160
 161 #define MI_IS_SESSION_ADDRESS(Address) \
 162     (((Address) >= MmSessionBase) && ((Address) < MiSessionSpaceEnd))
 163
 164 #define MI_IS_SESSION_PTE(Pte) \
 165     ((((PMMPTE)Pte) >= MiSessionBasePte) && (((PMMPTE)Pte) < MiSessionLastPte))
 166
 167 #define MI_IS_PAGE_TABLE_ADDRESS(Address) \
 168     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)PTE_TOP))
 169
 170 #define MI_IS_SYSTEM_PAGE_TABLE_ADDRESS(Address) \
 171     (((Address) >= (PVOID)MiAddressToPte(MmSystemRangeStart)) && ((Address) <= (PVOID)PTE_TOP))
 172
 173 #define MI_IS_PAGE_TABLE_OR_HYPER_ADDRESS(Address) \
 174     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)MmHyperSpaceEnd))
 175
 176 //
 177 // Corresponds to MMPTE_SOFTWARE.Protection
 178 //
 179 #ifdef _M_IX86
 180 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 181 #elif _M_ARM
 182 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 183 #elif _M_AMD64
 184 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 185 #else
 186 #error Define these please!
 187 #endif
 188
 189 //
 190 // Creates a software PTE with the given protection
 191 //
 192 #define MI_MAKE_SOFTWARE_PTE(p, x)          ((p)->u.Long = (x << MM_PTE_SOFTWARE_PROTECTION_BITS))
 193
 194 //
 195 // Marks a PTE as deleted
 196 //
 197 #define MI_SET_PFN_DELETED(x)               ((x)->PteAddress = (PMMPTE)((ULONG_PTR)(x)->PteAddress | 1))
 198 #define MI_IS_PFN_DELETED(x)                ((ULONG_PTR)((x)->PteAddress) & 1)
 199
 200 //
 201 // Special values for LoadedImports
 202 //
 203 #define MM_SYSLDR_NO_IMPORTS   (PVOID)0xFFFFFFFE
 204 #define MM_SYSLDR_BOOT_LOADED  (PVOID)0xFFFFFFFF
 205 #define MM_SYSLDR_SINGLE_ENTRY 0x1
 206
 207 #if defined(_M_IX86) || defined(_M_ARM)
 208 //
 209 // PFN List Sentinel
 210 //
 211 #define LIST_HEAD 0xFFFFFFFF
 212
 213 //
 214 // Because GCC cannot automatically downcast 0xFFFFFFFF to lesser-width bits,
 215 // we need a manual definition suited to the number of bits in the PteFrame.
 216 // This is used as a LIST_HEAD for the colored list
 217 //
 218 #define COLORED_LIST_HEAD ((1 << 25) - 1) // 0x1FFFFFF
 219 #elif defined(_M_AMD64)
 220 #define LIST_HEAD 0xFFFFFFFFFFFFFFFFLL
 221 #define COLORED_LIST_HEAD ((1 << 57) - 1) // 0x1FFFFFFFFFFFFFFLL
 222 #else
 223 #error Define these please!
 224 #endif
 225
 226 //
 227 // Special IRQL value (found in assertions)
 228 //
 229 #define MM_NOIRQL (KIRQL)0xFFFFFFFF
 230
 231 //
 232 // Returns the color of a page
 233 //
 234 #define MI_GET_PAGE_COLOR(x)                ((x) & MmSecondaryColorMask)
 235 #define MI_GET_NEXT_COLOR(x)                (MI_GET_PAGE_COLOR(++MmSystemPageColor))
 236 #define MI_GET_NEXT_PROCESS_COLOR(x)        (MI_GET_PAGE_COLOR(++(x)->NextPageColor))
 237
 238 #ifdef _M_IX86
 239 //
 240 // Decodes a Prototype PTE into the underlying PTE
 241 //
 242 #define MiProtoPteToPte(x)                  \
 243     (PMMPTE)((ULONG_PTR)MmPagedPoolStart +  \
 244              (((x)->u.Proto.ProtoAddressHigh << 7) | (x)->u.Proto.ProtoAddressLow))
 245 #endif
 246
 247 //
 248 // Prototype PTEs that don't yet have a pagefile association
 249 //
 250 #define MI_PTE_LOOKUP_NEEDED 0xFFFFF
 251
 252 //
 253 // System views are binned into 64K chunks
 254 //
 255 #define MI_SYSTEM_VIEW_BUCKET_SIZE  _64K
 256
 257 //
 258 // FIXFIX: These should go in ex.h after the pool merge
 259 //
 260 #ifdef _M_AMD64
 261 #define POOL_BLOCK_SIZE 16
 262 #else
 263 #define POOL_BLOCK_SIZE  8
 264 #endif
 265 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / POOL_BLOCK_SIZE)
 266 #define BASE_POOL_TYPE_MASK 1
 267 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + POOL_BLOCK_SIZE))
 268
 269 typedef struct _POOL_DESCRIPTOR
 270 {
 271     POOL_TYPE PoolType;
 272     ULONG PoolIndex;
 273     ULONG RunningAllocs;
 274     ULONG RunningDeAllocs;
 275     ULONG TotalPages;
 276     ULONG TotalBigPages;
 277     ULONG Threshold;
 278     PVOID LockAddress;
 279     PVOID PendingFrees;
 280     LONG PendingFreeDepth;
 281     SIZE_T TotalBytes;
 282     SIZE_T Spare0;
 283     LIST_ENTRY ListHeads[POOL_LISTS_PER_PAGE];
 284 } POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
 285
 286 typedef struct _POOL_HEADER
 287 {
 288     union
 289     {
 290         struct
 291         {
 292 #ifdef _M_AMD64
 293             ULONG PreviousSize:8;
 294             ULONG PoolIndex:8;
 295             ULONG BlockSize:8;
 296             ULONG PoolType:8;
 297 #else
 298             USHORT PreviousSize:9;
 299             USHORT PoolIndex:7;
 300             USHORT BlockSize:9;
 301             USHORT PoolType:7;
 302 #endif
 303         };
 304         ULONG Ulong1;
 305     };
 306 #ifdef _M_AMD64
 307     ULONG PoolTag;
 308 #endif
 309     union
 310     {
 311 #ifdef _M_AMD64
 312         PEPROCESS ProcessBilled;
 313 #else
 314         ULONG PoolTag;
 315 #endif
 316         struct
 317         {
 318             USHORT AllocatorBackTraceIndex;
 319             USHORT PoolTagHash;
 320         };
 321     };
 322 } POOL_HEADER, *PPOOL_HEADER;
 323
 324 C_ASSERT(sizeof(POOL_HEADER) == POOL_BLOCK_SIZE);
 325 C_ASSERT(POOL_BLOCK_SIZE == sizeof(LIST_ENTRY));
 326
 327 extern ULONG ExpNumberOfPagedPools;
 328 extern POOL_DESCRIPTOR NonPagedPoolDescriptor;
 329 extern PPOOL_DESCRIPTOR ExpPagedPoolDescriptor[16 + 1];
 330 extern PVOID PoolTrackTable;
 331
 332 //
 333 // END FIXFIX
 334 //
 335
 336 typedef struct _MI_LARGE_PAGE_DRIVER_ENTRY
 337 {
 338     LIST_ENTRY Links;
 339     UNICODE_STRING BaseName;
 340 } MI_LARGE_PAGE_DRIVER_ENTRY, *PMI_LARGE_PAGE_DRIVER_ENTRY;
 341
 342 typedef enum _MMSYSTEM_PTE_POOL_TYPE
 343 {
 344     SystemPteSpace,
 345     NonPagedPoolExpansion,
 346     MaximumPtePoolTypes
 347 } MMSYSTEM_PTE_POOL_TYPE;
 348
 349 typedef enum _MI_PFN_CACHE_ATTRIBUTE
 350 {
 351     MiNonCached,
 352     MiCached,
 353     MiWriteCombined,
 354     MiNotMapped
 355 } MI_PFN_CACHE_ATTRIBUTE, *PMI_PFN_CACHE_ATTRIBUTE;
 356
 357 typedef struct _PHYSICAL_MEMORY_RUN
 358 {
 359     ULONG BasePage;
 360     ULONG PageCount;
 361 } PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
 362
 363 typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
 364 {
 365     ULONG NumberOfRuns;
 366     ULONG NumberOfPages;
 367     PHYSICAL_MEMORY_RUN Run[1];
 368 } PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
 369
 370 typedef struct _MMCOLOR_TABLES
 371 {
 372     PFN_NUMBER Flink;
 373     PVOID Blink;
 374     PFN_NUMBER Count;
 375 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 376
 377 typedef struct _MI_LARGE_PAGE_RANGES
 378 {
 379     PFN_NUMBER StartFrame;
 380     PFN_NUMBER LastFrame;
 381 } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
 382
 383 typedef struct _MMVIEW
 384 {
 385     ULONG_PTR Entry;
 386     PCONTROL_AREA ControlArea;
 387 } MMVIEW, *PMMVIEW;
 388
 389 typedef struct _MMSESSION
 390 {
 391     KGUARDED_MUTEX SystemSpaceViewLock;
 392     PKGUARDED_MUTEX SystemSpaceViewLockPointer;
 393     PCHAR SystemSpaceViewStart;
 394     PMMVIEW SystemSpaceViewTable;
 395     ULONG SystemSpaceHashSize;
 396     ULONG SystemSpaceHashEntries;
 397     ULONG SystemSpaceHashKey;
 398     ULONG BitmapFailures;
 399     PRTL_BITMAP SystemSpaceBitMap;
 400 } MMSESSION, *PMMSESSION;
 401
 402 extern MMPTE HyperTemplatePte;
 403 extern MMPDE ValidKernelPde;
 404 extern MMPTE ValidKernelPte;
 405 extern MMPDE DemandZeroPde;
 406 extern MMPTE DemandZeroPte;
 407 extern MMPTE PrototypePte;
 408 extern BOOLEAN MmLargeSystemCache;
 409 extern BOOLEAN MmZeroPageFile;
 410 extern BOOLEAN MmProtectFreedNonPagedPool;
 411 extern BOOLEAN MmTrackLockedPages;
 412 extern BOOLEAN MmTrackPtes;
 413 extern BOOLEAN MmDynamicPfn;
 414 extern BOOLEAN MmMirroring;
 415 extern BOOLEAN MmMakeLowMemory;
 416 extern BOOLEAN MmEnforceWriteProtection;
 417 extern SIZE_T MmAllocationFragment;
 418 extern ULONG MmConsumedPoolPercentage;
 419 extern ULONG MmVerifyDriverBufferType;
 420 extern ULONG MmVerifyDriverLevel;
 421 extern WCHAR MmVerifyDriverBuffer[512];
 422 extern WCHAR MmLargePageDriverBuffer[512];
 423 extern LIST_ENTRY MiLargePageDriverList;
 424 extern BOOLEAN MiLargePageAllDrivers;
 425 extern ULONG MmVerifyDriverBufferLength;
 426 extern ULONG MmLargePageDriverBufferLength;
 427 extern SIZE_T MmSizeOfNonPagedPoolInBytes;
 428 extern SIZE_T MmMaximumNonPagedPoolInBytes;
 429 extern PFN_NUMBER MmMaximumNonPagedPoolInPages;
 430 extern PFN_NUMBER MmSizeOfPagedPoolInPages;
 431 extern PVOID MmNonPagedSystemStart;
 432 extern PVOID MmNonPagedPoolStart;
 433 extern PVOID MmNonPagedPoolExpansionStart;
 434 extern PVOID MmNonPagedPoolEnd;
 435 extern SIZE_T MmSizeOfPagedPoolInBytes;
 436 extern PVOID MmPagedPoolStart;
 437 extern PVOID MmPagedPoolEnd;
 438 extern PVOID MmSessionBase;
 439 extern SIZE_T MmSessionSize;
 440 extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
 441 extern PMMPTE MiFirstReservedZeroingPte;
 442 extern MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType];
 443 extern PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
 444 extern SIZE_T MmBootImageSize;
 445 extern PMMPTE MmSystemPtesStart[MaximumPtePoolTypes];
 446 extern PMMPTE MmSystemPtesEnd[MaximumPtePoolTypes];
 447 extern PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
 448 extern MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
 449 extern ULONG_PTR MxPfnAllocation;
 450 extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
 451 extern RTL_BITMAP MiPfnBitMap;
 452 extern KGUARDED_MUTEX MmPagedPoolMutex;
 453 extern PVOID MmPagedPoolStart;
 454 extern PVOID MmPagedPoolEnd;
 455 extern PVOID MmNonPagedSystemStart;
 456 extern PVOID MiSystemViewStart;
 457 extern SIZE_T MmSystemViewSize;
 458 extern PVOID MmSessionBase;
 459 extern PVOID MiSessionSpaceEnd;
 460 extern PMMPTE MiSessionImagePteStart;
 461 extern PMMPTE MiSessionImagePteEnd;
 462 extern PMMPTE MiSessionBasePte;
 463 extern PMMPTE MiSessionLastPte;
 464 extern SIZE_T MmSizeOfPagedPoolInBytes;
 465 extern PMMPTE MmSystemPagePtes;
 466 extern PVOID MmSystemCacheStart;
 467 extern PVOID MmSystemCacheEnd;
 468 extern MMSUPPORT MmSystemCacheWs;
 469 extern SIZE_T MmAllocatedNonPagedPool;
 470 extern ULONG_PTR MmSubsectionBase;
 471 extern ULONG MmSpecialPoolTag;
 472 extern PVOID MmHyperSpaceEnd;
 473 extern PMMWSL MmSystemCacheWorkingSetList;
 474 extern SIZE_T MmMinimumNonPagedPoolSize;
 475 extern ULONG MmMinAdditionNonPagedPoolPerMb;
 476 extern SIZE_T MmDefaultMaximumNonPagedPool;
 477 extern ULONG MmMaxAdditionNonPagedPoolPerMb;
 478 extern ULONG MmSecondaryColors;
 479 extern ULONG MmSecondaryColorMask;
 480 extern ULONG_PTR MmNumberOfSystemPtes;
 481 extern ULONG MmMaximumNonPagedPoolPercent;
 482 extern ULONG MmLargeStackSize;
 483 extern PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
 484 extern ULONG MmProductType;
 485 extern MM_SYSTEMSIZE MmSystemSize;
 486 extern PKEVENT MiLowMemoryEvent;
 487 extern PKEVENT MiHighMemoryEvent;
 488 extern PKEVENT MiLowPagedPoolEvent;
 489 extern PKEVENT MiHighPagedPoolEvent;
 490 extern PKEVENT MiLowNonPagedPoolEvent;
 491 extern PKEVENT MiHighNonPagedPoolEvent;
 492 extern PFN_NUMBER MmLowMemoryThreshold;
 493 extern PFN_NUMBER MmHighMemoryThreshold;
 494 extern PFN_NUMBER MiLowPagedPoolThreshold;
 495 extern PFN_NUMBER MiHighPagedPoolThreshold;
 496 extern PFN_NUMBER MiLowNonPagedPoolThreshold;
 497 extern PFN_NUMBER MiHighNonPagedPoolThreshold;
 498 extern PFN_NUMBER MmMinimumFreePages;
 499 extern PFN_NUMBER MmPlentyFreePages;
 500 extern PFN_NUMBER MiExpansionPoolPagesInitialCharge;
 501 extern PFN_NUMBER MmResidentAvailablePages;
 502 extern PFN_NUMBER MmResidentAvailableAtInit;
 503 extern ULONG MmTotalFreeSystemPtes[MaximumPtePoolTypes];
 504 extern PFN_NUMBER MmTotalSystemDriverPages;
 505 extern PVOID MiSessionImageStart;
 506 extern PVOID MiSessionImageEnd;
 507 extern PMMPTE MiHighestUserPte;
 508 extern PMMPDE MiHighestUserPde;
 509 extern PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
 510 extern PMMPTE MmSharedUserDataPte;
 511 extern LIST_ENTRY MmProcessList;
 512 extern BOOLEAN MmZeroingPageThreadActive;
 513 extern KEVENT MmZeroingPageEvent;
 514 extern ULONG MmSystemPageColor;
 515 extern ULONG MmProcessColorSeed;
 516 extern PMMWSL MmWorkingSetList;
 517
 518 //
 519 // Figures out the hardware bits for a PTE
 520 //
 521 ULONG
 522 FORCEINLINE
 523 MiDetermineUserGlobalPteMask(IN PMMPTE PointerPte)
 524 {
 525     MMPTE TempPte;
 526
 527     /* Start fresh */
 528     TempPte.u.Long = 0;
 529
 530     /* Make it valid and accessed */
 531     TempPte.u.Hard.Valid = TRUE;
 532     TempPte.u.Hard.Accessed = TRUE;
 533
 534     /* Is this for user-mode? */
 535     if ((PointerPte <= MiHighestUserPte) ||
 536         ((PointerPte >= MiAddressToPde(NULL)) && (PointerPte <= MiHighestUserPde)))
 537     {
 538         /* Set the owner bit */
 539         TempPte.u.Hard.Owner = TRUE;
 540     }
 541
 542     /* FIXME: We should also set the global bit */
 543
 544     /* Return the protection */
 545     return TempPte.u.Long;
 546 }
 547
 548 //
 549 // Creates a valid kernel PTE with the given protection
 550 //
 551 FORCEINLINE
 552 VOID
 553 MI_MAKE_HARDWARE_PTE_KERNEL(IN PMMPTE NewPte,
 554                             IN PMMPTE MappingPte,
 555                             IN ULONG ProtectionMask,
 556                             IN PFN_NUMBER PageFrameNumber)
 557 {
 558     /* Only valid for kernel, non-session PTEs */
 559     ASSERT(MappingPte > MiHighestUserPte);
 560     ASSERT(!MI_IS_SESSION_PTE(MappingPte));
 561     ASSERT((MappingPte < (PMMPTE)PDE_BASE) || (MappingPte > (PMMPTE)PDE_TOP));
 562
 563     /* Start fresh */
 564     *NewPte = ValidKernelPte;
 565
 566     /* Set the protection and page */
 567     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 568     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 569 }
 570
 571 //
 572 // Creates a valid PTE with the given protection
 573 //
 574 FORCEINLINE
 575 VOID
 576 MI_MAKE_HARDWARE_PTE(IN PMMPTE NewPte,
 577                      IN PMMPTE MappingPte,
 578                      IN ULONG ProtectionMask,
 579                      IN PFN_NUMBER PageFrameNumber)
 580 {
 581     /* Set the protection and page */
 582     NewPte->u.Long = MiDetermineUserGlobalPteMask(MappingPte);
 583     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 584     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 585 }
 586
 587 //
 588 // Creates a valid user PTE with the given protection
 589 //
 590 FORCEINLINE
 591 VOID
 592 MI_MAKE_HARDWARE_PTE_USER(IN PMMPTE NewPte,
 593                           IN PMMPTE MappingPte,
 594                           IN ULONG ProtectionMask,
 595                           IN PFN_NUMBER PageFrameNumber)
 596 {
 597     /* Only valid for kernel, non-session PTEs */
 598     ASSERT(MappingPte <= MiHighestUserPte);
 599
 600     /* Start fresh */
 601     *NewPte = ValidKernelPte;
 602
 603     /* Set the protection and page */
 604     NewPte->u.Hard.Owner = TRUE;
 605     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 606     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 607 }
 608
 609 #ifdef _M_IX86
 610 //
 611 // Builds a Prototype PTE for the address of the PTE
 612 //
 613 FORCEINLINE
 614 VOID
 615 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
 616                       IN PMMPTE PointerPte)
 617 {
 618     ULONG_PTR Offset;
 619
 620     /* Mark this as a prototype */
 621     NewPte->u.Long = 0;
 622     NewPte->u.Proto.Prototype = 1;
 623
 624     /*
 625      * Prototype PTEs are only valid in paged pool by design, this little trick
 626      * lets us only use 28 bits for the adress of the PTE
 627      */
 628     Offset = (ULONG_PTR)PointerPte - (ULONG_PTR)MmPagedPoolStart;
 629
 630     /* 7 bits go in the "low", and the other 21 bits go in the "high" */
 631     NewPte->u.Proto.ProtoAddressLow = Offset & 0x7F;
 632     NewPte->u.Proto.ProtoAddressHigh = (Offset & 0xFFFFFF80) >> 7;
 633     ASSERT(MiProtoPteToPte(NewPte) == PointerPte);
 634 }
 635 #endif
 636
 637 //
 638 // Returns if the page is physically resident (ie: a large page)
 639 // FIXFIX: CISC/x86 only?
 640 //
 641 FORCEINLINE
 642 BOOLEAN
 643 MI_IS_PHYSICAL_ADDRESS(IN PVOID Address)
 644 {
 645     PMMPDE PointerPde;
 646
 647     /* Large pages are never paged out, always physically resident */
 648     PointerPde = MiAddressToPde(Address);
 649     return ((PointerPde->u.Hard.LargePage) && (PointerPde->u.Hard.Valid));
 650 }
 651
 652 //
 653 // Writes a valid PTE
 654 //
 655 VOID
 656 FORCEINLINE
 657 MI_WRITE_VALID_PTE(IN PMMPTE PointerPte,
 658                    IN MMPTE TempPte)
 659 {
 660     /* Write the valid PTE */
 661     ASSERT(PointerPte->u.Hard.Valid == 0);
 662     ASSERT(TempPte.u.Hard.Valid == 1);
 663     *PointerPte = TempPte;
 664 }
 665
 666 //
 667 // Writes an invalid PTE
 668 //
 669 VOID
 670 FORCEINLINE
 671 MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte,
 672                      IN MMPTE InvalidPte)
 673 {
 674     /* Write the invalid PTE */
 675     ASSERT(InvalidPte.u.Hard.Valid == 0);
 676     *PointerPte = InvalidPte;
 677 }
 678
 679 //
 680 // Checks if the thread already owns a working set
 681 //
 682 FORCEINLINE
 683 BOOLEAN
 684 MM_ANY_WS_LOCK_HELD(IN PETHREAD Thread)
 685 {
 686     /* If any of these are held, return TRUE */
 687     return ((Thread->OwnsProcessWorkingSetExclusive) ||
 688             (Thread->OwnsProcessWorkingSetShared) ||
 689             (Thread->OwnsSystemWorkingSetExclusive) ||
 690             (Thread->OwnsSystemWorkingSetShared) ||
 691             (Thread->OwnsSessionWorkingSetExclusive) ||
 692             (Thread->OwnsSessionWorkingSetShared));
 693 }
 694
 695 //
 696 // Checks if the process owns the working set lock
 697 //
 698 FORCEINLINE
 699 BOOLEAN
 700 MI_WS_OWNER(IN PEPROCESS Process)
 701 {
 702     /* Check if this process is the owner, and that the thread owns the WS */
 703     return ((KeGetCurrentThread()->ApcState.Process == &Process->Pcb) &&
 704             ((PsGetCurrentThread()->OwnsProcessWorkingSetExclusive) ||
 705              (PsGetCurrentThread()->OwnsProcessWorkingSetShared)));
 706 }
 707
 708 //
 709 // Locks the working set for the given process
 710 //
 711 FORCEINLINE
 712 VOID
 713 MiLockProcessWorkingSet(IN PEPROCESS Process,
 714                         IN PETHREAD Thread)
 715 {
 716     /* Shouldn't already be owning the process working set */
 717     ASSERT(Thread->OwnsProcessWorkingSetShared == FALSE);
 718     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 719
 720     /* Block APCs, make sure that still nothing is already held */
 721     KeEnterGuardedRegion();
 722     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 723
 724     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 725
 726     /* FIXME: This also can't be checked because Vm is used by MAREAs) */
 727     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 728
 729     /* Okay, now we can own it exclusively */
 730     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 731     Thread->OwnsProcessWorkingSetExclusive = TRUE;
 732 }
 733
 734 //
 735 // Unlocks the working set for the given process
 736 //
 737 FORCEINLINE
 738 VOID
 739 MiUnlockProcessWorkingSet(IN PEPROCESS Process,
 740                           IN PETHREAD Thread)
 741 {
 742     /* Make sure this process really is owner, and it was a safe acquisition */
 743     ASSERT(MI_WS_OWNER(Process));
 744     /* This can't be checked because Vm is used by MAREAs) */
 745     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 746
 747     /* The thread doesn't own it anymore */
 748     ASSERT(Thread->OwnsProcessWorkingSetExclusive == TRUE);
 749     Thread->OwnsProcessWorkingSetExclusive = FALSE;
 750
 751     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 752
 753     /* Unblock APCs */
 754     KeLeaveGuardedRegion();
 755 }
 756
 757 //
 758 // Locks the working set
 759 //
 760 FORCEINLINE
 761 VOID
 762 MiLockWorkingSet(IN PETHREAD Thread,
 763                  IN PMMSUPPORT WorkingSet)
 764 {
 765     /* Block APCs */
 766     KeEnterGuardedRegion();
 767
 768     /* Working set should be in global memory */
 769     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 770
 771     /* Thread shouldn't already be owning something */
 772     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 773
 774     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 775
 776     /* Which working set is this? */
 777     if (WorkingSet == &MmSystemCacheWs)
 778     {
 779         /* Own the system working set */
 780         ASSERT((Thread->OwnsSystemWorkingSetExclusive == FALSE) &&
 781                (Thread->OwnsSystemWorkingSetShared == FALSE));
 782         Thread->OwnsSystemWorkingSetExclusive = TRUE;
 783     }
 784     else if (WorkingSet->Flags.SessionSpace)
 785     {
 786         /* We don't implement this yet */
 787         UNIMPLEMENTED;
 788         while (TRUE);
 789     }
 790     else
 791     {
 792         /* Own the process working set */
 793         ASSERT((Thread->OwnsProcessWorkingSetExclusive == FALSE) &&
 794                (Thread->OwnsProcessWorkingSetShared == FALSE));
 795         Thread->OwnsProcessWorkingSetExclusive = TRUE;
 796     }
 797 }
 798
 799 //
 800 // Unlocks the working set
 801 //
 802 FORCEINLINE
 803 VOID
 804 MiUnlockWorkingSet(IN PETHREAD Thread,
 805                    IN PMMSUPPORT WorkingSet)
 806 {
 807     /* Working set should be in global memory */
 808     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 809
 810     /* Which working set is this? */
 811     if (WorkingSet == &MmSystemCacheWs)
 812     {
 813         /* Release the system working set */
 814         ASSERT((Thread->OwnsSystemWorkingSetExclusive == TRUE) ||
 815                (Thread->OwnsSystemWorkingSetShared == TRUE));
 816         Thread->OwnsSystemWorkingSetExclusive = FALSE;
 817     }
 818     else if (WorkingSet->Flags.SessionSpace)
 819     {
 820         /* We don't implement this yet */
 821         UNIMPLEMENTED;
 822         while (TRUE);
 823     }
 824     else
 825     {
 826         /* Release the process working set */
 827         ASSERT((Thread->OwnsProcessWorkingSetExclusive) ||
 828                (Thread->OwnsProcessWorkingSetShared));
 829         Thread->OwnsProcessWorkingSetExclusive = FALSE;
 830     }
 831
 832     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 833
 834     /* Unblock APCs */
 835     KeLeaveGuardedRegion();
 836 }
 837
 838 //
 839 // Returns the ProtoPTE inside a VAD for the given VPN
 840 //
 841 FORCEINLINE
 842 PMMPTE
 843 MI_GET_PROTOTYPE_PTE_FOR_VPN(IN PMMVAD Vad,
 844                              IN ULONG_PTR Vpn)
 845 {
 846     PMMPTE ProtoPte;
 847
 848     /* Find the offset within the VAD's prototype PTEs */
 849     ProtoPte = Vad->FirstPrototypePte + (Vpn - Vad->StartingVpn);
 850     ASSERT(ProtoPte <= Vad->LastContiguousPte);
 851     return ProtoPte;
 852 }
 853
 854 //
 855 // Returns the PFN Database entry for the given page number
 856 // Warning: This is not necessarily a valid PFN database entry!
 857 //
 858 FORCEINLINE
 859 PMMPFN
 860 MI_PFN_ELEMENT(IN PFN_NUMBER Pfn)
 861 {
 862     /* Get the entry */
 863     return &MmPfnDatabase[Pfn];
 864 };
 865
 866 BOOLEAN
 867 NTAPI
 868 MmArmInitSystem(
 869     IN ULONG Phase,
 870     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 871 );
 872
 873 NTSTATUS
 874 NTAPI
 875 MiInitMachineDependent(
 876     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 877 );
 878
 879 VOID
 880 NTAPI
 881 MiComputeColorInformation(
 882     VOID
 883 );
 884
 885 VOID
 886 NTAPI
 887 MiMapPfnDatabase(
 888     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 889 );
 890
 891 VOID
 892 NTAPI
 893 MiInitializeColorTables(
 894     VOID
 895 );
 896
 897 VOID
 898 NTAPI
 899 MiInitializePfnDatabase(
 900     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 901 );
 902
 903 BOOLEAN
 904 NTAPI
 905 MiInitializeMemoryEvents(
 906     VOID
 907 );
 908
 909 PFN_NUMBER
 910 NTAPI
 911 MxGetNextPage(
 912     IN PFN_NUMBER PageCount
 913 );
 914
 915 PPHYSICAL_MEMORY_DESCRIPTOR
 916 NTAPI
 917 MmInitializeMemoryLimits(
 918     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 919     IN PBOOLEAN IncludeType
 920 );
 921
 922 PFN_NUMBER
 923 NTAPI
 924 MiPagesInLoaderBlock(
 925     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 926     IN PBOOLEAN IncludeType
 927 );
 928
 929 VOID
 930 FASTCALL
 931 MiSyncARM3WithROS(
 932     IN PVOID AddressStart,
 933     IN PVOID AddressEnd
 934 );
 935
 936 NTSTATUS
 937 NTAPI
 938 MmArmAccessFault(
 939     IN BOOLEAN StoreInstruction,
 940     IN PVOID Address,
 941     IN KPROCESSOR_MODE Mode,
 942     IN PVOID TrapInformation
 943 );
 944
 945 NTSTATUS
 946 FASTCALL
 947 MiCheckPdeForPagedPool(
 948     IN PVOID Address
 949 );
 950
 951 VOID
 952 NTAPI
 953 MiInitializeNonPagedPool(
 954     VOID
 955 );
 956
 957 VOID
 958 NTAPI
 959 MiInitializeNonPagedPoolThresholds(
 960     VOID
 961 );
 962
 963 VOID
 964 NTAPI
 965 MiInitializePoolEvents(
 966     VOID
 967 );
 968
 969 VOID                      //
 970 NTAPI                     //
 971 InitializePool(           //
 972     IN POOL_TYPE PoolType,// FIXFIX: This should go in ex.h after the pool merge
 973     IN ULONG Threshold    //
 974 );                        //
 975
 976 VOID
 977 NTAPI
 978 MiInitializeSystemPtes(
 979     IN PMMPTE StartingPte,
 980     IN ULONG NumberOfPtes,
 981     IN MMSYSTEM_PTE_POOL_TYPE PoolType
 982 );
 983
 984 PMMPTE
 985 NTAPI
 986 MiReserveSystemPtes(
 987     IN ULONG NumberOfPtes,
 988     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 989 );
 990
 991 VOID
 992 NTAPI
 993 MiReleaseSystemPtes(
 994     IN PMMPTE StartingPte,
 995     IN ULONG NumberOfPtes,
 996     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 997 );
 998
 999
1000 PFN_NUMBER
1001 NTAPI
1002 MiFindContiguousPages(
1003     IN PFN_NUMBER LowestPfn,
1004     IN PFN_NUMBER HighestPfn,
1005     IN PFN_NUMBER BoundaryPfn,
1006     IN PFN_NUMBER SizeInPages,
1007     IN MEMORY_CACHING_TYPE CacheType
1008 );
1009
1010 PVOID
1011 NTAPI
1012 MiCheckForContiguousMemory(
1013     IN PVOID BaseAddress,
1014     IN PFN_NUMBER BaseAddressPages,
1015     IN PFN_NUMBER SizeInPages,
1016     IN PFN_NUMBER LowestPfn,
1017     IN PFN_NUMBER HighestPfn,
1018     IN PFN_NUMBER BoundaryPfn,
1019     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
1020 );
1021
1022 PMDL
1023 NTAPI
1024 MiAllocatePagesForMdl(
1025     IN PHYSICAL_ADDRESS LowAddress,
1026     IN PHYSICAL_ADDRESS HighAddress,
1027     IN PHYSICAL_ADDRESS SkipBytes,
1028     IN SIZE_T TotalBytes,
1029     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
1030     IN ULONG Flags
1031 );
1032
1033 PVOID
1034 NTAPI
1035 MiMapLockedPagesInUserSpace(
1036     IN PMDL Mdl,
1037     IN PVOID BaseVa,
1038     IN MEMORY_CACHING_TYPE CacheType,
1039     IN PVOID BaseAddress
1040 );
1041
1042 VOID
1043 NTAPI
1044 MiUnmapLockedPagesInUserSpace(
1045     IN PVOID BaseAddress,
1046     IN PMDL Mdl
1047 );
1048
1049 VOID
1050 NTAPI
1051 MiInsertPageInList(
1052     IN PMMPFNLIST ListHead,
1053     IN PFN_NUMBER PageFrameIndex
1054 );
1055
1056 VOID
1057 NTAPI
1058 MiUnlinkFreeOrZeroedPage(
1059     IN PMMPFN Entry
1060 );
1061
1062 PFN_NUMBER
1063 NTAPI
1064 MiAllocatePfn(
1065     IN PMMPTE PointerPte,
1066     IN ULONG Protection
1067 );
1068
1069 VOID
1070 NTAPI
1071 MiInitializePfn(
1072     IN PFN_NUMBER PageFrameIndex,
1073     IN PMMPTE PointerPte,
1074     IN BOOLEAN Modified
1075 );
1076
1077 VOID
1078 NTAPI
1079 MiInitializePfnForOtherProcess(
1080     IN PFN_NUMBER PageFrameIndex,
1081     IN PMMPTE PointerPte,
1082     IN PFN_NUMBER PteFrame
1083 );
1084
1085 VOID
1086 NTAPI
1087 MiDecrementShareCount(
1088     IN PMMPFN Pfn1,
1089     IN PFN_NUMBER PageFrameIndex
1090 );
1091
1092 VOID
1093 NTAPI
1094 MiDecrementReferenceCount(
1095     IN PMMPFN Pfn1,
1096     IN PFN_NUMBER PageFrameIndex
1097 );
1098
1099 PFN_NUMBER
1100 NTAPI
1101 MiRemoveAnyPage(
1102     IN ULONG Color
1103 );
1104
1105 PFN_NUMBER
1106 NTAPI
1107 MiRemoveZeroPage(
1108     IN ULONG Color
1109 );
1110
1111 VOID
1112 NTAPI
1113 MiZeroPhysicalPage(
1114     IN PFN_NUMBER PageFrameIndex
1115 );
1116
1117 VOID
1118 NTAPI
1119 MiInsertPageInFreeList(
1120     IN PFN_NUMBER PageFrameIndex
1121 );
1122
1123 PFN_NUMBER
1124 NTAPI
1125 MiDeleteSystemPageableVm(
1126     IN PMMPTE PointerPte,
1127     IN PFN_NUMBER PageCount,
1128     IN ULONG Flags,
1129     OUT PPFN_NUMBER ValidPages
1130 );
1131
1132 PLDR_DATA_TABLE_ENTRY
1133 NTAPI
1134 MiLookupDataTableEntry(
1135     IN PVOID Address
1136 );
1137
1138 VOID
1139 NTAPI
1140 MiInitializeDriverLargePageList(
1141     VOID
1142 );
1143
1144 VOID
1145 NTAPI
1146 MiInitializeLargePageSupport(
1147     VOID
1148 );
1149
1150 VOID
1151 NTAPI
1152 MiSyncCachedRanges(
1153     VOID
1154 );
1155
1156 BOOLEAN
1157 NTAPI
1158 MiIsPfnInUse(
1159     IN PMMPFN Pfn1
1160 );
1161
1162 PMMVAD
1163 NTAPI
1164 MiLocateAddress(
1165     IN PVOID VirtualAddress
1166 );
1167
1168 PMMADDRESS_NODE
1169 NTAPI
1170 MiCheckForConflictingNode(
1171     IN ULONG_PTR StartVpn,
1172     IN ULONG_PTR EndVpn,
1173     IN PMM_AVL_TABLE Table
1174 );
1175
1176 TABLE_SEARCH_RESULT
1177 NTAPI
1178 MiFindEmptyAddressRangeDownTree(
1179     IN SIZE_T Length,
1180     IN ULONG_PTR BoundaryAddress,
1181     IN ULONG_PTR Alignment,
1182     IN PMM_AVL_TABLE Table,
1183     OUT PULONG_PTR Base,
1184     OUT PMMADDRESS_NODE *Parent
1185 );
1186
1187 NTSTATUS
1188 NTAPI
1189 MiFindEmptyAddressRangeInTree(
1190     IN SIZE_T Length,
1191     IN ULONG_PTR Alignment,
1192     IN PMM_AVL_TABLE Table,
1193     OUT PMMADDRESS_NODE *PreviousVad,
1194     OUT PULONG_PTR Base
1195 );
1196
1197 VOID
1198 NTAPI
1199 MiInsertVad(
1200     IN PMMVAD Vad,
1201     IN PEPROCESS Process
1202 );
1203
1204 VOID
1205 NTAPI
1206 MiInsertNode(
1207     IN PMM_AVL_TABLE Table,
1208     IN PMMADDRESS_NODE NewNode,
1209     PMMADDRESS_NODE Parent,
1210     TABLE_SEARCH_RESULT Result
1211 );
1212
1213 VOID
1214 NTAPI
1215 MiRemoveNode(
1216     IN PMMADDRESS_NODE Node,
1217     IN PMM_AVL_TABLE Table
1218 );
1219
1220 PMMADDRESS_NODE
1221 NTAPI
1222 MiGetPreviousNode(
1223     IN PMMADDRESS_NODE Node
1224 );
1225
1226 PMMADDRESS_NODE
1227 NTAPI
1228 MiGetNextNode(
1229     IN PMMADDRESS_NODE Node
1230 );
1231
1232 BOOLEAN
1233 NTAPI
1234 MiInitializeSystemSpaceMap(
1235     IN PVOID InputSession OPTIONAL
1236 );
1237
1238 ULONG
1239 NTAPI
1240 MiMakeProtectionMask(
1241     IN ULONG Protect
1242 );
1243
1244 VOID
1245 NTAPI
1246 MiDeleteVirtualAddresses(
1247     IN ULONG_PTR Va,
1248     IN ULONG_PTR EndingAddress,
1249     IN PMMVAD Vad
1250 );
1251
1252 ULONG
1253 NTAPI
1254 MiMakeSystemAddressValid(
1255     IN PVOID PageTableVirtualAddress,
1256     IN PEPROCESS CurrentProcess
1257 );
1258
1259 ULONG
1260 NTAPI
1261 MiMakeSystemAddressValidPfn(
1262     IN PVOID VirtualAddress,
1263     IN KIRQL OldIrql
1264 );
1265
1266 VOID
1267 NTAPI
1268 MiRemoveMappedView(
1269     IN PEPROCESS CurrentProcess,
1270     IN PMMVAD Vad
1271 );
1272
1273 PSUBSECTION
1274 NTAPI
1275 MiLocateSubsection(
1276     IN PMMVAD Vad,
1277     IN ULONG_PTR Vpn
1278 );
1279
1280 //
1281 // MiRemoveZeroPage will use inline code to zero out the page manually if only
1282 // free pages are available. In some scenarios, we don't/can't run that piece of
1283 // code and would rather only have a real zero page. If we can't have a zero page,
1284 // then we'd like to have our own code to grab a free page and zero it out, by
1285 // using MiRemoveAnyPage. This macro implements this.
1286 //
1287 PFN_NUMBER
1288 FORCEINLINE
1289 MiRemoveZeroPageSafe(IN ULONG Color)
1290 {
1291     if (MmFreePagesByColor[ZeroedPageList][Color].Flink != LIST_HEAD) return MiRemoveZeroPage(Color);
1292     return 0;
1293 }
1294
1295 //
1296 // New ARM3<->RosMM PAGE Architecture
1297 //
1298 #define MI_GET_ROS_DATA(x)   ((PMMROSPFN)(x->RosMmData))
1299 #define MI_IS_ROS_PFN(x)     (((x)->u4.AweAllocation == TRUE) && (MI_GET_ROS_DATA(x) != NULL))
1300 #define ASSERT_IS_ROS_PFN(x) ASSERT(MI_IS_ROS_PFN(x) == TRUE);
1301 typedef struct _MMROSPFN
1302 {
1303     PMM_RMAP_ENTRY RmapListHead;
1304     SWAPENTRY SwapEntry;
1305 } MMROSPFN, *PMMROSPFN;
1306
1307 #define RosMmData            AweReferenceCount
1308
1309 /* EOF */