reactos/ntoskrnl/mm/ARM3/miarm.h

   1 /*
   2  * PROJECT:         ReactOS Kernel
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            ntoskrnl/mm/ARM3/miarm.h
   5  * PURPOSE:         ARM Memory Manager Header
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 #ifndef _M_AMD64
  10
  11 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING   ((255 * _1MB) >> PAGE_SHIFT)
  12 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING          ((19 * _1MB) >> PAGE_SHIFT)
  13 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST           ((32 * _1MB) >> PAGE_SHIFT)
  14 #define MI_MAX_INIT_NONPAGED_POOL_SIZE          (128 * _1MB)
  15 #define MI_MAX_NONPAGED_POOL_SIZE               (128 * _1MB)
  16 #define MI_MAX_FREE_PAGE_LISTS                  4
  17
  18 #define MI_MIN_INIT_PAGED_POOLSIZE              (32 * _1MB)
  19
  20 #define MI_SESSION_VIEW_SIZE                    (20 * _1MB)
  21 #define MI_SESSION_POOL_SIZE                    (16 * _1MB)
  22 #define MI_SESSION_IMAGE_SIZE                   (8 * _1MB)
  23 #define MI_SESSION_WORKING_SET_SIZE             (4 * _1MB)
  24 #define MI_SESSION_SIZE                         (MI_SESSION_VIEW_SIZE + \
  25                                                  MI_SESSION_POOL_SIZE + \
  26                                                  MI_SESSION_IMAGE_SIZE + \
  27                                                  MI_SESSION_WORKING_SET_SIZE)
  28
  29 #define MI_SYSTEM_VIEW_SIZE                     (16 * _1MB)
  30
  31 #define MI_SYSTEM_CACHE_WS_START                (PVOID)0xC0C00000
  32 #define MI_PAGED_POOL_START                     (PVOID)0xE1000000
  33 #define MI_NONPAGED_POOL_END                    (PVOID)0xFFBE0000
  34 #define MI_DEBUG_MAPPING                        (PVOID)0xFFBFF000
  35
  36 #define MI_SYSTEM_PTE_BASE                      (PVOID)MiAddressToPte(NULL)
  37
  38 #define MI_MIN_SECONDARY_COLORS                 8
  39 #define MI_SECONDARY_COLORS                     64
  40 #define MI_MAX_SECONDARY_COLORS                 1024
  41
  42 #define MI_MIN_ALLOCATION_FRAGMENT              (4 * _1KB)
  43 #define MI_ALLOCATION_FRAGMENT                  (64 * _1KB)
  44 #define MI_MAX_ALLOCATION_FRAGMENT              (2  * _1MB)
  45
  46 #define MM_HIGHEST_VAD_ADDRESS \
  47     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  48 #define MI_LOWEST_VAD_ADDRESS                   (PVOID)MM_LOWEST_USER_ADDRESS
  49
  50 #endif /* !_M_AMD64 */
  51
  52 /* Make the code cleaner with some definitions for size multiples */
  53 #define _1KB (1024u)
  54 #define _1MB (1024 * _1KB)
  55 #define _1GB (1024 * _1MB)
  56
  57 /* Everyone loves 64K */
  58 #define _64K (64 * _1KB)
  59
  60 /* Area mapped by a PDE */
  61 #define PDE_MAPPED_VA  (PTE_COUNT * PAGE_SIZE)
  62
  63 /* Size of a page table */
  64 #define PT_SIZE  (PTE_COUNT * sizeof(MMPTE))
  65
  66 /* Size of a page directory */
  67 #define PD_SIZE  (PDE_COUNT * sizeof(MMPDE))
  68
  69 /* Size of all page directories for a process */
  70 #define SYSTEM_PD_SIZE (PD_COUNT * PD_SIZE)
  71
  72 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
  73 #ifdef _M_IX86
  74 #define PD_COUNT  1
  75 #define PDE_COUNT 1024
  76 #define PTE_COUNT 1024
  77 C_ASSERT(SYSTEM_PD_SIZE == PAGE_SIZE);
  78 #elif _M_ARM
  79 #define PD_COUNT  1
  80 #define PDE_COUNT 4096
  81 #define PTE_COUNT 256
  82 #else
  83 #define PD_COUNT  PPE_PER_PAGE
  84 #define PDE_COUNT PDE_PER_PAGE
  85 #define PTE_COUNT PTE_PER_PAGE
  86 #endif
  87
  88 #ifdef _M_IX86
  89 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_I386
  90 #elif _M_ARM
  91 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_ARM
  92 #elif _M_AMD64
  93 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_AMD64
  94 #else
  95 #error Define these please!
  96 #endif
  97
  98 //
  99 // Protection Bits part of the internal memory manager Protection Mask
 100 // Taken from http://www.reactos.org/wiki/Techwiki:Memory_management_in_the_Windows_XP_kernel
 101 // and public assertions.
 102 //
 103 #define MM_ZERO_ACCESS         0
 104 #define MM_READONLY            1
 105 #define MM_EXECUTE             2
 106 #define MM_EXECUTE_READ        3
 107 #define MM_READWRITE           4
 108 #define MM_WRITECOPY           5
 109 #define MM_EXECUTE_READWRITE   6
 110 #define MM_EXECUTE_WRITECOPY   7
 111 #define MM_NOCACHE             8
 112 #define MM_DECOMMIT            0x10
 113 #define MM_NOACCESS            (MM_DECOMMIT | MM_NOCACHE)
 114 #define MM_INVALID_PROTECTION  0xFFFFFFFF
 115
 116 //
 117 // Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits
 118 // The Memory Manager's definition define the attributes that must be preserved
 119 // and these PTE definitions describe the attributes in the hardware sense. This
 120 // helps deal with hardware differences between the actual boolean expression of
 121 // the argument.
 122 //
 123 // For example, in the logical attributes, we want to express read-only as a flag
 124 // but on x86, it is writability that must be set. On the other hand, on x86, just
 125 // like in the kernel, it is disabling the caches that requires a special flag,
 126 // while on certain architectures such as ARM, it is enabling the cache which
 127 // requires a flag.
 128 //
 129 #if defined(_M_IX86) || defined(_M_AMD64)
 130 //
 131 // Access Flags
 132 //
 133 #define PTE_READONLY            0
 134 #define PTE_EXECUTE             0 // Not worrying about NX yet
 135 #define PTE_EXECUTE_READ        0 // Not worrying about NX yet
 136 #define PTE_READWRITE           0x2
 137 #define PTE_WRITECOPY           0x200
 138 #define PTE_EXECUTE_READWRITE   0x0
 139 #define PTE_EXECUTE_WRITECOPY   0x200
 140 #define PTE_PROTOTYPE           0x400
 141 //
 142 // Cache flags
 143 //
 144 #define PTE_ENABLE_CACHE        0
 145 #define PTE_DISABLE_CACHE       0x10
 146 #define PTE_WRITECOMBINED_CACHE 0x10
 147 #elif defined(_M_ARM)
 148 #else
 149 #error Define these please!
 150 #endif
 151
 152 extern const ULONG MmProtectToPteMask[32];
 153 extern const ULONG MmProtectToValue[32];
 154
 155 //
 156 // Assertions for session images, addresses, and PTEs
 157 //
 158 #define MI_IS_SESSION_IMAGE_ADDRESS(Address) \
 159     (((Address) >= MiSessionImageStart) && ((Address) < MiSessionImageEnd))
 160
 161 #define MI_IS_SESSION_ADDRESS(Address) \
 162     (((Address) >= MmSessionBase) && ((Address) < MiSessionSpaceEnd))
 163
 164 #define MI_IS_SESSION_PTE(Pte) \
 165     ((((PMMPTE)Pte) >= MiSessionBasePte) && (((PMMPTE)Pte) < MiSessionLastPte))
 166
 167 #define MI_IS_PAGE_TABLE_ADDRESS(Address) \
 168     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)PTE_TOP))
 169
 170 #define MI_IS_SYSTEM_PAGE_TABLE_ADDRESS(Address) \
 171     (((Address) >= (PVOID)MiAddressToPte(MmSystemRangeStart)) && ((Address) <= (PVOID)PTE_TOP))
 172
 173 #define MI_IS_PAGE_TABLE_OR_HYPER_ADDRESS(Address) \
 174     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)MmHyperSpaceEnd))
 175
 176 //
 177 // Corresponds to MMPTE_SOFTWARE.Protection
 178 //
 179 #ifdef _M_IX86
 180 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 181 #elif _M_ARM
 182 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 183 #elif _M_AMD64
 184 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 185 #else
 186 #error Define these please!
 187 #endif
 188
 189 //
 190 // Creates a software PTE with the given protection
 191 //
 192 #define MI_MAKE_SOFTWARE_PTE(p, x)          ((p)->u.Long = (x << MM_PTE_SOFTWARE_PROTECTION_BITS))
 193
 194 //
 195 // Marks a PTE as deleted
 196 //
 197 #define MI_SET_PFN_DELETED(x)               ((x)->PteAddress = (PMMPTE)((ULONG_PTR)(x)->PteAddress | 1))
 198 #define MI_IS_PFN_DELETED(x)                ((ULONG_PTR)((x)->PteAddress) & 1)
 199
 200 //
 201 // Special values for LoadedImports
 202 //
 203 #define MM_SYSLDR_NO_IMPORTS   (PVOID)0xFFFFFFFE
 204 #define MM_SYSLDR_BOOT_LOADED  (PVOID)0xFFFFFFFF
 205 #define MM_SYSLDR_SINGLE_ENTRY 0x1
 206
 207 #if defined(_M_IX86) || defined(_M_ARM)
 208 //
 209 // PFN List Sentinel
 210 //
 211 #define LIST_HEAD 0xFFFFFFFF
 212
 213 //
 214 // Because GCC cannot automatically downcast 0xFFFFFFFF to lesser-width bits,
 215 // we need a manual definition suited to the number of bits in the PteFrame.
 216 // This is used as a LIST_HEAD for the colored list
 217 //
 218 #define COLORED_LIST_HEAD ((1 << 25) - 1) // 0x1FFFFFF
 219 #elif defined(_M_AMD64)
 220 #define LIST_HEAD 0xFFFFFFFFFFFFFFFFLL
 221 #define COLORED_LIST_HEAD ((1 << 57) - 1) // 0x1FFFFFFFFFFFFFFLL
 222 #else
 223 #error Define these please!
 224 #endif
 225
 226 //
 227 // Special IRQL value (found in assertions)
 228 //
 229 #define MM_NOIRQL (KIRQL)0xFFFFFFFF
 230
 231 //
 232 // Returns the color of a page
 233 //
 234 #define MI_GET_PAGE_COLOR(x)                ((x) & MmSecondaryColorMask)
 235 #define MI_GET_NEXT_COLOR(x)                (MI_GET_PAGE_COLOR(++MmSystemPageColor))
 236 #define MI_GET_NEXT_PROCESS_COLOR(x)        (MI_GET_PAGE_COLOR(++(x)->NextPageColor))
 237
 238 #ifdef _M_IX86
 239 //
 240 // Decodes a Prototype PTE into the underlying PTE
 241 //
 242 #define MiProtoPteToPte(x)                  \
 243     (PMMPTE)((ULONG_PTR)MmPagedPoolStart +  \
 244              (((x)->u.Proto.ProtoAddressHigh << 7) | (x)->u.Proto.ProtoAddressLow))
 245 #endif
 246
 247 //
 248 // Prototype PTEs that don't yet have a pagefile association
 249 //
 250 #define MI_PTE_LOOKUP_NEEDED 0xFFFFF
 251
 252 //
 253 // System views are binned into 64K chunks
 254 //
 255 #define MI_SYSTEM_VIEW_BUCKET_SIZE  _64K
 256
 257 //
 258 // FIXFIX: These should go in ex.h after the pool merge
 259 //
 260 #ifdef _M_AMD64
 261 #define POOL_BLOCK_SIZE 16
 262 #else
 263 #define POOL_BLOCK_SIZE  8
 264 #endif
 265 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / POOL_BLOCK_SIZE)
 266 #define BASE_POOL_TYPE_MASK 1
 267 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + POOL_BLOCK_SIZE))
 268
 269 typedef struct _POOL_DESCRIPTOR
 270 {
 271     POOL_TYPE PoolType;
 272     ULONG PoolIndex;
 273     ULONG RunningAllocs;
 274     ULONG RunningDeAllocs;
 275     ULONG TotalPages;
 276     ULONG TotalBigPages;
 277     ULONG Threshold;
 278     PVOID LockAddress;
 279     PVOID PendingFrees;
 280     LONG PendingFreeDepth;
 281     SIZE_T TotalBytes;
 282     SIZE_T Spare0;
 283     LIST_ENTRY ListHeads[POOL_LISTS_PER_PAGE];
 284 } POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
 285
 286 typedef struct _POOL_HEADER
 287 {
 288     union
 289     {
 290         struct
 291         {
 292 #ifdef _M_AMD64
 293             ULONG PreviousSize:8;
 294             ULONG PoolIndex:8;
 295             ULONG BlockSize:8;
 296             ULONG PoolType:8;
 297 #else
 298             USHORT PreviousSize:9;
 299             USHORT PoolIndex:7;
 300             USHORT BlockSize:9;
 301             USHORT PoolType:7;
 302 #endif
 303         };
 304         ULONG Ulong1;
 305     };
 306 #ifdef _M_AMD64
 307     ULONG PoolTag;
 308 #endif
 309     union
 310     {
 311 #ifdef _M_AMD64
 312         PEPROCESS ProcessBilled;
 313 #else
 314         ULONG PoolTag;
 315 #endif
 316         struct
 317         {
 318             USHORT AllocatorBackTraceIndex;
 319             USHORT PoolTagHash;
 320         };
 321     };
 322 } POOL_HEADER, *PPOOL_HEADER;
 323
 324 C_ASSERT(sizeof(POOL_HEADER) == POOL_BLOCK_SIZE);
 325 C_ASSERT(POOL_BLOCK_SIZE == sizeof(LIST_ENTRY));
 326
 327 extern ULONG ExpNumberOfPagedPools;
 328 extern POOL_DESCRIPTOR NonPagedPoolDescriptor;
 329 extern PPOOL_DESCRIPTOR ExpPagedPoolDescriptor[16 + 1];
 330 extern PVOID PoolTrackTable;
 331
 332 //
 333 // END FIXFIX
 334 //
 335
 336 typedef struct _MI_LARGE_PAGE_DRIVER_ENTRY
 337 {
 338     LIST_ENTRY Links;
 339     UNICODE_STRING BaseName;
 340 } MI_LARGE_PAGE_DRIVER_ENTRY, *PMI_LARGE_PAGE_DRIVER_ENTRY;
 341
 342 typedef enum _MMSYSTEM_PTE_POOL_TYPE
 343 {
 344     SystemPteSpace,
 345     NonPagedPoolExpansion,
 346     MaximumPtePoolTypes
 347 } MMSYSTEM_PTE_POOL_TYPE;
 348
 349 typedef enum _MI_PFN_CACHE_ATTRIBUTE
 350 {
 351     MiNonCached,
 352     MiCached,
 353     MiWriteCombined,
 354     MiNotMapped
 355 } MI_PFN_CACHE_ATTRIBUTE, *PMI_PFN_CACHE_ATTRIBUTE;
 356
 357 typedef struct _PHYSICAL_MEMORY_RUN
 358 {
 359     ULONG BasePage;
 360     ULONG PageCount;
 361 } PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
 362
 363 typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
 364 {
 365     ULONG NumberOfRuns;
 366     ULONG NumberOfPages;
 367     PHYSICAL_MEMORY_RUN Run[1];
 368 } PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
 369
 370 typedef struct _MMCOLOR_TABLES
 371 {
 372     PFN_NUMBER Flink;
 373     PVOID Blink;
 374     PFN_NUMBER Count;
 375 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 376
 377 typedef struct _MI_LARGE_PAGE_RANGES
 378 {
 379     PFN_NUMBER StartFrame;
 380     PFN_NUMBER LastFrame;
 381 } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
 382
 383 typedef struct _MMVIEW
 384 {
 385     ULONG_PTR Entry;
 386     PCONTROL_AREA ControlArea;
 387 } MMVIEW, *PMMVIEW;
 388
 389 typedef struct _MMSESSION
 390 {
 391     KGUARDED_MUTEX SystemSpaceViewLock;
 392     PKGUARDED_MUTEX SystemSpaceViewLockPointer;
 393     PCHAR SystemSpaceViewStart;
 394     PMMVIEW SystemSpaceViewTable;
 395     ULONG SystemSpaceHashSize;
 396     ULONG SystemSpaceHashEntries;
 397     ULONG SystemSpaceHashKey;
 398     ULONG BitmapFailures;
 399     PRTL_BITMAP SystemSpaceBitMap;
 400 } MMSESSION, *PMMSESSION;
 401
 402 extern MMPTE HyperTemplatePte;
 403 extern MMPDE ValidKernelPde;
 404 extern MMPTE ValidKernelPte;
 405 extern MMPDE DemandZeroPde;
 406 extern MMPTE PrototypePte;
 407 extern BOOLEAN MmLargeSystemCache;
 408 extern BOOLEAN MmZeroPageFile;
 409 extern BOOLEAN MmProtectFreedNonPagedPool;
 410 extern BOOLEAN MmTrackLockedPages;
 411 extern BOOLEAN MmTrackPtes;
 412 extern BOOLEAN MmDynamicPfn;
 413 extern BOOLEAN MmMirroring;
 414 extern BOOLEAN MmMakeLowMemory;
 415 extern BOOLEAN MmEnforceWriteProtection;
 416 extern SIZE_T MmAllocationFragment;
 417 extern ULONG MmConsumedPoolPercentage;
 418 extern ULONG MmVerifyDriverBufferType;
 419 extern ULONG MmVerifyDriverLevel;
 420 extern WCHAR MmVerifyDriverBuffer[512];
 421 extern WCHAR MmLargePageDriverBuffer[512];
 422 extern LIST_ENTRY MiLargePageDriverList;
 423 extern BOOLEAN MiLargePageAllDrivers;
 424 extern ULONG MmVerifyDriverBufferLength;
 425 extern ULONG MmLargePageDriverBufferLength;
 426 extern SIZE_T MmSizeOfNonPagedPoolInBytes;
 427 extern SIZE_T MmMaximumNonPagedPoolInBytes;
 428 extern PFN_NUMBER MmMaximumNonPagedPoolInPages;
 429 extern PFN_NUMBER MmSizeOfPagedPoolInPages;
 430 extern PVOID MmNonPagedSystemStart;
 431 extern PVOID MmNonPagedPoolStart;
 432 extern PVOID MmNonPagedPoolExpansionStart;
 433 extern PVOID MmNonPagedPoolEnd;
 434 extern SIZE_T MmSizeOfPagedPoolInBytes;
 435 extern PVOID MmPagedPoolStart;
 436 extern PVOID MmPagedPoolEnd;
 437 extern PVOID MmSessionBase;
 438 extern SIZE_T MmSessionSize;
 439 extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
 440 extern PMMPTE MiFirstReservedZeroingPte;
 441 extern MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType];
 442 extern PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
 443 extern SIZE_T MmBootImageSize;
 444 extern PMMPTE MmSystemPtesStart[MaximumPtePoolTypes];
 445 extern PMMPTE MmSystemPtesEnd[MaximumPtePoolTypes];
 446 extern PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
 447 extern MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
 448 extern ULONG_PTR MxPfnAllocation;
 449 extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
 450 extern RTL_BITMAP MiPfnBitMap;
 451 extern KGUARDED_MUTEX MmPagedPoolMutex;
 452 extern PVOID MmPagedPoolStart;
 453 extern PVOID MmPagedPoolEnd;
 454 extern PVOID MmNonPagedSystemStart;
 455 extern PVOID MiSystemViewStart;
 456 extern SIZE_T MmSystemViewSize;
 457 extern PVOID MmSessionBase;
 458 extern PVOID MiSessionSpaceEnd;
 459 extern PMMPTE MiSessionImagePteStart;
 460 extern PMMPTE MiSessionImagePteEnd;
 461 extern PMMPTE MiSessionBasePte;
 462 extern PMMPTE MiSessionLastPte;
 463 extern SIZE_T MmSizeOfPagedPoolInBytes;
 464 extern PMMPTE MmSystemPagePtes;
 465 extern PVOID MmSystemCacheStart;
 466 extern PVOID MmSystemCacheEnd;
 467 extern MMSUPPORT MmSystemCacheWs;
 468 extern SIZE_T MmAllocatedNonPagedPool;
 469 extern ULONG_PTR MmSubsectionBase;
 470 extern ULONG MmSpecialPoolTag;
 471 extern PVOID MmHyperSpaceEnd;
 472 extern PMMWSL MmSystemCacheWorkingSetList;
 473 extern SIZE_T MmMinimumNonPagedPoolSize;
 474 extern ULONG MmMinAdditionNonPagedPoolPerMb;
 475 extern SIZE_T MmDefaultMaximumNonPagedPool;
 476 extern ULONG MmMaxAdditionNonPagedPoolPerMb;
 477 extern ULONG MmSecondaryColors;
 478 extern ULONG MmSecondaryColorMask;
 479 extern ULONG_PTR MmNumberOfSystemPtes;
 480 extern ULONG MmMaximumNonPagedPoolPercent;
 481 extern ULONG MmLargeStackSize;
 482 extern PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
 483 extern ULONG MmProductType;
 484 extern MM_SYSTEMSIZE MmSystemSize;
 485 extern PKEVENT MiLowMemoryEvent;
 486 extern PKEVENT MiHighMemoryEvent;
 487 extern PKEVENT MiLowPagedPoolEvent;
 488 extern PKEVENT MiHighPagedPoolEvent;
 489 extern PKEVENT MiLowNonPagedPoolEvent;
 490 extern PKEVENT MiHighNonPagedPoolEvent;
 491 extern PFN_NUMBER MmLowMemoryThreshold;
 492 extern PFN_NUMBER MmHighMemoryThreshold;
 493 extern PFN_NUMBER MiLowPagedPoolThreshold;
 494 extern PFN_NUMBER MiHighPagedPoolThreshold;
 495 extern PFN_NUMBER MiLowNonPagedPoolThreshold;
 496 extern PFN_NUMBER MiHighNonPagedPoolThreshold;
 497 extern PFN_NUMBER MmMinimumFreePages;
 498 extern PFN_NUMBER MmPlentyFreePages;
 499 extern PFN_NUMBER MiExpansionPoolPagesInitialCharge;
 500 extern PFN_NUMBER MmResidentAvailablePages;
 501 extern PFN_NUMBER MmResidentAvailableAtInit;
 502 extern ULONG MmTotalFreeSystemPtes[MaximumPtePoolTypes];
 503 extern PFN_NUMBER MmTotalSystemDriverPages;
 504 extern PVOID MiSessionImageStart;
 505 extern PVOID MiSessionImageEnd;
 506 extern PMMPTE MiHighestUserPte;
 507 extern PMMPDE MiHighestUserPde;
 508 extern PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
 509 extern PMMPTE MmSharedUserDataPte;
 510 extern LIST_ENTRY MmProcessList;
 511 extern BOOLEAN MmZeroingPageThreadActive;
 512 extern KEVENT MmZeroingPageEvent;
 513 extern ULONG MmSystemPageColor;
 514 extern ULONG MmProcessColorSeed;
 515
 516 //
 517 // Figures out the hardware bits for a PTE
 518 //
 519 ULONG
 520 FORCEINLINE
 521 MiDetermineUserGlobalPteMask(IN PMMPTE PointerPte)
 522 {
 523     MMPTE TempPte;
 524
 525     /* Start fresh */
 526     TempPte.u.Long = 0;
 527
 528     /* Make it valid and accessed */
 529     TempPte.u.Hard.Valid = TRUE;
 530     TempPte.u.Hard.Accessed = TRUE;
 531
 532     /* Is this for user-mode? */
 533     if ((PointerPte <= MiHighestUserPte) ||
 534         ((PointerPte >= MiAddressToPde(NULL)) && (PointerPte <= MiHighestUserPde)))
 535     {
 536         /* Set the owner bit */
 537         TempPte.u.Hard.Owner = TRUE;
 538     }
 539
 540     /* FIXME: We should also set the global bit */
 541
 542     /* Return the protection */
 543     return TempPte.u.Long;
 544 }
 545
 546 //
 547 // Creates a valid kernel PTE with the given protection
 548 //
 549 FORCEINLINE
 550 VOID
 551 MI_MAKE_HARDWARE_PTE_KERNEL(IN PMMPTE NewPte,
 552                             IN PMMPTE MappingPte,
 553                             IN ULONG ProtectionMask,
 554                             IN PFN_NUMBER PageFrameNumber)
 555 {
 556     /* Only valid for kernel, non-session PTEs */
 557     ASSERT(MappingPte > MiHighestUserPte);
 558     ASSERT(!MI_IS_SESSION_PTE(MappingPte));
 559     ASSERT((MappingPte < (PMMPTE)PDE_BASE) || (MappingPte > (PMMPTE)PDE_TOP));
 560
 561     /* Start fresh */
 562     *NewPte = ValidKernelPte;
 563
 564     /* Set the protection and page */
 565     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 566     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 567 }
 568
 569 //
 570 // Creates a valid PTE with the given protection
 571 //
 572 FORCEINLINE
 573 VOID
 574 MI_MAKE_HARDWARE_PTE(IN PMMPTE NewPte,
 575                      IN PMMPTE MappingPte,
 576                      IN ULONG ProtectionMask,
 577                      IN PFN_NUMBER PageFrameNumber)
 578 {
 579     /* Set the protection and page */
 580     NewPte->u.Long = MiDetermineUserGlobalPteMask(MappingPte);
 581     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 582     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 583 }
 584
 585 //
 586 // Creates a valid user PTE with the given protection
 587 //
 588 FORCEINLINE
 589 VOID
 590 MI_MAKE_HARDWARE_PTE_USER(IN PMMPTE NewPte,
 591                           IN PMMPTE MappingPte,
 592                           IN ULONG ProtectionMask,
 593                           IN PFN_NUMBER PageFrameNumber)
 594 {
 595     /* Only valid for kernel, non-session PTEs */
 596     ASSERT(MappingPte <= MiHighestUserPte);
 597
 598     /* Start fresh */
 599     *NewPte = ValidKernelPte;
 600
 601     /* Set the protection and page */
 602     NewPte->u.Hard.Owner = TRUE;
 603     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 604     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 605 }
 606
 607 #ifdef _M_IX86
 608 //
 609 // Builds a Prototype PTE for the address of the PTE
 610 //
 611 FORCEINLINE
 612 VOID
 613 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
 614                       IN PMMPTE PointerPte)
 615 {
 616     ULONG_PTR Offset;
 617
 618     /* Mark this as a prototype */
 619     NewPte->u.Long = 0;
 620     NewPte->u.Proto.Prototype = 1;
 621
 622     /*
 623      * Prototype PTEs are only valid in paged pool by design, this little trick
 624      * lets us only use 28 bits for the adress of the PTE
 625      */
 626     Offset = (ULONG_PTR)PointerPte - (ULONG_PTR)MmPagedPoolStart;
 627
 628     /* 7 bits go in the "low", and the other 21 bits go in the "high" */
 629     NewPte->u.Proto.ProtoAddressLow = Offset & 0x7F;
 630     NewPte->u.Proto.ProtoAddressHigh = (Offset & 0xFFFFFF80) >> 7;
 631     ASSERT(MiProtoPteToPte(NewPte) == PointerPte);
 632 }
 633 #endif
 634
 635 //
 636 // Returns if the page is physically resident (ie: a large page)
 637 // FIXFIX: CISC/x86 only?
 638 //
 639 FORCEINLINE
 640 BOOLEAN
 641 MI_IS_PHYSICAL_ADDRESS(IN PVOID Address)
 642 {
 643     PMMPDE PointerPde;
 644
 645     /* Large pages are never paged out, always physically resident */
 646     PointerPde = MiAddressToPde(Address);
 647     return ((PointerPde->u.Hard.LargePage) && (PointerPde->u.Hard.Valid));
 648 }
 649
 650 //
 651 // Writes a valid PTE
 652 //
 653 VOID
 654 FORCEINLINE
 655 MI_WRITE_VALID_PTE(IN PMMPTE PointerPte,
 656                    IN MMPTE TempPte)
 657 {
 658     /* Write the valid PTE */
 659     ASSERT(PointerPte->u.Hard.Valid == 0);
 660     ASSERT(TempPte.u.Hard.Valid == 1);
 661     *PointerPte = TempPte;
 662 }
 663
 664 //
 665 // Writes an invalid PTE
 666 //
 667 VOID
 668 FORCEINLINE
 669 MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte,
 670                      IN MMPTE InvalidPte)
 671 {
 672     /* Write the invalid PTE */
 673     ASSERT(InvalidPte.u.Hard.Valid == 0);
 674     *PointerPte = InvalidPte;
 675 }
 676
 677 //
 678 // Checks if the thread already owns a working set
 679 //
 680 FORCEINLINE
 681 BOOLEAN
 682 MM_ANY_WS_LOCK_HELD(IN PETHREAD Thread)
 683 {
 684     /* If any of these are held, return TRUE */
 685     return ((Thread->OwnsProcessWorkingSetExclusive) ||
 686             (Thread->OwnsProcessWorkingSetShared) ||
 687             (Thread->OwnsSystemWorkingSetExclusive) ||
 688             (Thread->OwnsSystemWorkingSetShared) ||
 689             (Thread->OwnsSessionWorkingSetExclusive) ||
 690             (Thread->OwnsSessionWorkingSetShared));
 691 }
 692
 693 //
 694 // Checks if the process owns the working set lock
 695 //
 696 FORCEINLINE
 697 BOOLEAN
 698 MI_WS_OWNER(IN PEPROCESS Process)
 699 {
 700     /* Check if this process is the owner, and that the thread owns the WS */
 701     return ((KeGetCurrentThread()->ApcState.Process == &Process->Pcb) &&
 702             ((PsGetCurrentThread()->OwnsProcessWorkingSetExclusive) ||
 703              (PsGetCurrentThread()->OwnsProcessWorkingSetShared)));
 704 }
 705
 706 //
 707 // Locks the working set for the given process
 708 //
 709 FORCEINLINE
 710 VOID
 711 MiLockProcessWorkingSet(IN PEPROCESS Process,
 712                         IN PETHREAD Thread)
 713 {
 714     /* Shouldn't already be owning the process working set */
 715     ASSERT(Thread->OwnsProcessWorkingSetShared == FALSE);
 716     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 717
 718     /* Block APCs, make sure that still nothing is already held */
 719     KeEnterGuardedRegion();
 720     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 721
 722     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 723
 724     /* FIXME: This also can't be checked because Vm is used by MAREAs) */
 725     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 726
 727     /* Okay, now we can own it exclusively */
 728     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 729     Thread->OwnsProcessWorkingSetExclusive = TRUE;
 730 }
 731
 732 //
 733 // Unlocks the working set for the given process
 734 //
 735 FORCEINLINE
 736 VOID
 737 MiUnlockProcessWorkingSet(IN PEPROCESS Process,
 738                           IN PETHREAD Thread)
 739 {
 740     /* Make sure this process really is owner, and it was a safe acquisition */
 741     ASSERT(MI_WS_OWNER(Process));
 742     /* This can't be checked because Vm is used by MAREAs) */
 743     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 744
 745     /* The thread doesn't own it anymore */
 746     ASSERT(Thread->OwnsProcessWorkingSetExclusive == TRUE);
 747     Thread->OwnsProcessWorkingSetExclusive = FALSE;
 748
 749     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 750
 751     /* Unblock APCs */
 752     KeLeaveGuardedRegion();
 753 }
 754
 755 //
 756 // Locks the working set
 757 //
 758 FORCEINLINE
 759 VOID
 760 MiLockWorkingSet(IN PETHREAD Thread,
 761                  IN PMMSUPPORT WorkingSet)
 762 {
 763     /* Block APCs */
 764     KeEnterGuardedRegion();
 765
 766     /* Working set should be in global memory */
 767     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 768
 769     /* Thread shouldn't already be owning something */
 770     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 771
 772     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 773
 774     /* Which working set is this? */
 775     if (WorkingSet == &MmSystemCacheWs)
 776     {
 777         /* Own the system working set */
 778         ASSERT((Thread->OwnsSystemWorkingSetExclusive == FALSE) &&
 779                (Thread->OwnsSystemWorkingSetShared == FALSE));
 780         Thread->OwnsSystemWorkingSetExclusive = TRUE;
 781     }
 782     else if (WorkingSet->Flags.SessionSpace)
 783     {
 784         /* We don't implement this yet */
 785         UNIMPLEMENTED;
 786         while (TRUE);
 787     }
 788     else
 789     {
 790         /* Own the process working set */
 791         ASSERT((Thread->OwnsProcessWorkingSetExclusive == FALSE) &&
 792                (Thread->OwnsProcessWorkingSetShared == FALSE));
 793         Thread->OwnsProcessWorkingSetExclusive = TRUE;
 794     }
 795 }
 796
 797 //
 798 // Unlocks the working set
 799 //
 800 FORCEINLINE
 801 VOID
 802 MiUnlockWorkingSet(IN PETHREAD Thread,
 803                    IN PMMSUPPORT WorkingSet)
 804 {
 805     /* Working set should be in global memory */
 806     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 807
 808     /* Which working set is this? */
 809     if (WorkingSet == &MmSystemCacheWs)
 810     {
 811         /* Release the system working set */
 812         ASSERT((Thread->OwnsSystemWorkingSetExclusive == TRUE) ||
 813                (Thread->OwnsSystemWorkingSetShared == TRUE));
 814         Thread->OwnsSystemWorkingSetExclusive = FALSE;
 815     }
 816     else if (WorkingSet->Flags.SessionSpace)
 817     {
 818         /* We don't implement this yet */
 819         UNIMPLEMENTED;
 820         while (TRUE);
 821     }
 822     else
 823     {
 824         /* Release the process working set */
 825         ASSERT((Thread->OwnsProcessWorkingSetExclusive) ||
 826                (Thread->OwnsProcessWorkingSetShared));
 827         Thread->OwnsProcessWorkingSetExclusive = FALSE;
 828     }
 829
 830     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 831
 832     /* Unblock APCs */
 833     KeLeaveGuardedRegion();
 834 }
 835
 836 //
 837 // Returns the ProtoPTE inside a VAD for the given VPN
 838 //
 839 FORCEINLINE
 840 PMMPTE
 841 MI_GET_PROTOTYPE_PTE_FOR_VPN(IN PMMVAD Vad,
 842                              IN ULONG_PTR Vpn)
 843 {
 844     PMMPTE ProtoPte;
 845
 846     /* Find the offset within the VAD's prototype PTEs */
 847     ProtoPte = Vad->FirstPrototypePte + (Vpn - Vad->StartingVpn);
 848     ASSERT(ProtoPte <= Vad->LastContiguousPte);
 849     return ProtoPte;
 850 }
 851
 852 BOOLEAN
 853 NTAPI
 854 MmArmInitSystem(
 855     IN ULONG Phase,
 856     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 857 );
 858
 859 NTSTATUS
 860 NTAPI
 861 MiInitMachineDependent(
 862     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 863 );
 864
 865 VOID
 866 NTAPI
 867 MiComputeColorInformation(
 868     VOID
 869 );
 870
 871 VOID
 872 NTAPI
 873 MiMapPfnDatabase(
 874     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 875 );
 876
 877 VOID
 878 NTAPI
 879 MiInitializeColorTables(
 880     VOID
 881 );
 882
 883 VOID
 884 NTAPI
 885 MiInitializePfnDatabase(
 886     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 887 );
 888
 889 BOOLEAN
 890 NTAPI
 891 MiInitializeMemoryEvents(
 892     VOID
 893 );
 894
 895 PFN_NUMBER
 896 NTAPI
 897 MxGetNextPage(
 898     IN PFN_NUMBER PageCount
 899 );
 900
 901 PPHYSICAL_MEMORY_DESCRIPTOR
 902 NTAPI
 903 MmInitializeMemoryLimits(
 904     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 905     IN PBOOLEAN IncludeType
 906 );
 907
 908 PFN_NUMBER
 909 NTAPI
 910 MiPagesInLoaderBlock(
 911     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 912     IN PBOOLEAN IncludeType
 913 );
 914
 915 VOID
 916 FASTCALL
 917 MiSyncARM3WithROS(
 918     IN PVOID AddressStart,
 919     IN PVOID AddressEnd
 920 );
 921
 922 NTSTATUS
 923 NTAPI
 924 MmArmAccessFault(
 925     IN BOOLEAN StoreInstruction,
 926     IN PVOID Address,
 927     IN KPROCESSOR_MODE Mode,
 928     IN PVOID TrapInformation
 929 );
 930
 931 NTSTATUS
 932 FASTCALL
 933 MiCheckPdeForPagedPool(
 934     IN PVOID Address
 935 );
 936
 937 VOID
 938 NTAPI
 939 MiInitializeNonPagedPool(
 940     VOID
 941 );
 942
 943 VOID
 944 NTAPI
 945 MiInitializeNonPagedPoolThresholds(
 946     VOID
 947 );
 948
 949 VOID
 950 NTAPI
 951 MiInitializePoolEvents(
 952     VOID
 953 );
 954
 955 VOID                      //
 956 NTAPI                     //
 957 InitializePool(           //
 958     IN POOL_TYPE PoolType,// FIXFIX: This should go in ex.h after the pool merge
 959     IN ULONG Threshold    //
 960 );                        //
 961
 962 VOID
 963 NTAPI
 964 MiInitializeSystemPtes(
 965     IN PMMPTE StartingPte,
 966     IN ULONG NumberOfPtes,
 967     IN MMSYSTEM_PTE_POOL_TYPE PoolType
 968 );
 969
 970 PMMPTE
 971 NTAPI
 972 MiReserveSystemPtes(
 973     IN ULONG NumberOfPtes,
 974     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 975 );
 976
 977 VOID
 978 NTAPI
 979 MiReleaseSystemPtes(
 980     IN PMMPTE StartingPte,
 981     IN ULONG NumberOfPtes,
 982     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 983 );
 984
 985
 986 PFN_NUMBER
 987 NTAPI
 988 MiFindContiguousPages(
 989     IN PFN_NUMBER LowestPfn,
 990     IN PFN_NUMBER HighestPfn,
 991     IN PFN_NUMBER BoundaryPfn,
 992     IN PFN_NUMBER SizeInPages,
 993     IN MEMORY_CACHING_TYPE CacheType
 994 );
 995
 996 PVOID
 997 NTAPI
 998 MiCheckForContiguousMemory(
 999     IN PVOID BaseAddress,
1000     IN PFN_NUMBER BaseAddressPages,
1001     IN PFN_NUMBER SizeInPages,
1002     IN PFN_NUMBER LowestPfn,
1003     IN PFN_NUMBER HighestPfn,
1004     IN PFN_NUMBER BoundaryPfn,
1005     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
1006 );
1007
1008 PMDL
1009 NTAPI
1010 MiAllocatePagesForMdl(
1011     IN PHYSICAL_ADDRESS LowAddress,
1012     IN PHYSICAL_ADDRESS HighAddress,
1013     IN PHYSICAL_ADDRESS SkipBytes,
1014     IN SIZE_T TotalBytes,
1015     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
1016     IN ULONG Flags
1017 );
1018
1019 PVOID
1020 NTAPI
1021 MiMapLockedPagesInUserSpace(
1022     IN PMDL Mdl,
1023     IN PVOID BaseVa,
1024     IN MEMORY_CACHING_TYPE CacheType,
1025     IN PVOID BaseAddress
1026 );
1027
1028 VOID
1029 NTAPI
1030 MiUnmapLockedPagesInUserSpace(
1031     IN PVOID BaseAddress,
1032     IN PMDL Mdl
1033 );
1034
1035 VOID
1036 NTAPI
1037 MiInsertPageInList(
1038     IN PMMPFNLIST ListHead,
1039     IN PFN_NUMBER PageFrameIndex
1040 );
1041
1042 VOID
1043 NTAPI
1044 MiUnlinkFreeOrZeroedPage(
1045     IN PMMPFN Entry
1046 );
1047
1048 PFN_NUMBER
1049 NTAPI
1050 MiAllocatePfn(
1051     IN PMMPTE PointerPte,
1052     IN ULONG Protection
1053 );
1054
1055 VOID
1056 NTAPI
1057 MiInitializePfn(
1058     IN PFN_NUMBER PageFrameIndex,
1059     IN PMMPTE PointerPte,
1060     IN BOOLEAN Modified
1061 );
1062
1063 VOID
1064 NTAPI
1065 MiInitializePfnForOtherProcess(
1066     IN PFN_NUMBER PageFrameIndex,
1067     IN PMMPTE PointerPte,
1068     IN PFN_NUMBER PteFrame
1069 );
1070
1071 VOID
1072 NTAPI
1073 MiDecrementShareCount(
1074     IN PMMPFN Pfn1,
1075     IN PFN_NUMBER PageFrameIndex
1076 );
1077
1078 VOID
1079 NTAPI
1080 MiDecrementReferenceCount(
1081     IN PMMPFN Pfn1,
1082     IN PFN_NUMBER PageFrameIndex
1083 );
1084
1085 PFN_NUMBER
1086 NTAPI
1087 MiRemoveAnyPage(
1088     IN ULONG Color
1089 );
1090
1091 PFN_NUMBER
1092 NTAPI
1093 MiRemoveZeroPage(
1094     IN ULONG Color
1095 );
1096
1097 VOID
1098 NTAPI
1099 MiZeroPhysicalPage(
1100     IN PFN_NUMBER PageFrameIndex
1101 );
1102
1103 VOID
1104 NTAPI
1105 MiInsertPageInFreeList(
1106     IN PFN_NUMBER PageFrameIndex
1107 );
1108
1109 PFN_NUMBER
1110 NTAPI
1111 MiDeleteSystemPageableVm(
1112     IN PMMPTE PointerPte,
1113     IN PFN_NUMBER PageCount,
1114     IN ULONG Flags,
1115     OUT PPFN_NUMBER ValidPages
1116 );
1117
1118 PLDR_DATA_TABLE_ENTRY
1119 NTAPI
1120 MiLookupDataTableEntry(
1121     IN PVOID Address
1122 );
1123
1124 VOID
1125 NTAPI
1126 MiInitializeDriverLargePageList(
1127     VOID
1128 );
1129
1130 VOID
1131 NTAPI
1132 MiInitializeLargePageSupport(
1133     VOID
1134 );
1135
1136 VOID
1137 NTAPI
1138 MiSyncCachedRanges(
1139     VOID
1140 );
1141
1142 BOOLEAN
1143 NTAPI
1144 MiIsPfnInUse(
1145     IN PMMPFN Pfn1
1146 );
1147
1148 PMMVAD
1149 NTAPI
1150 MiLocateAddress(
1151     IN PVOID VirtualAddress
1152 );
1153
1154 PMMADDRESS_NODE
1155 NTAPI
1156 MiCheckForConflictingNode(
1157     IN ULONG_PTR StartVpn,
1158     IN ULONG_PTR EndVpn,
1159     IN PMM_AVL_TABLE Table
1160 );
1161
1162 TABLE_SEARCH_RESULT
1163 NTAPI
1164 MiFindEmptyAddressRangeDownTree(
1165     IN SIZE_T Length,
1166     IN ULONG_PTR BoundaryAddress,
1167     IN ULONG_PTR Alignment,
1168     IN PMM_AVL_TABLE Table,
1169     OUT PULONG_PTR Base,
1170     OUT PMMADDRESS_NODE *Parent
1171 );
1172
1173 NTSTATUS
1174 NTAPI
1175 MiFindEmptyAddressRangeInTree(
1176     IN SIZE_T Length,
1177     IN ULONG_PTR Alignment,
1178     IN PMM_AVL_TABLE Table,
1179     OUT PMMADDRESS_NODE *PreviousVad,
1180     OUT PULONG_PTR Base
1181 );
1182
1183 VOID
1184 NTAPI
1185 MiInsertVad(
1186     IN PMMVAD Vad,
1187     IN PEPROCESS Process
1188 );
1189
1190 VOID
1191 NTAPI
1192 MiInsertNode(
1193     IN PMM_AVL_TABLE Table,
1194     IN PMMADDRESS_NODE NewNode,
1195     PMMADDRESS_NODE Parent,
1196     TABLE_SEARCH_RESULT Result
1197 );
1198
1199 VOID
1200 NTAPI
1201 MiRemoveNode(
1202     IN PMMADDRESS_NODE Node,
1203     IN PMM_AVL_TABLE Table
1204 );
1205
1206 PMMADDRESS_NODE
1207 NTAPI
1208 MiGetPreviousNode(
1209     IN PMMADDRESS_NODE Node
1210 );
1211
1212 PMMADDRESS_NODE
1213 NTAPI
1214 MiGetNextNode(
1215     IN PMMADDRESS_NODE Node
1216 );
1217
1218 BOOLEAN
1219 NTAPI
1220 MiInitializeSystemSpaceMap(
1221     IN PVOID InputSession OPTIONAL
1222 );
1223
1224 ULONG
1225 NTAPI
1226 MiMakeProtectionMask(
1227     IN ULONG Protect
1228 );
1229
1230 VOID
1231 NTAPI
1232 MiDeleteVirtualAddresses(
1233     IN ULONG_PTR Va,
1234     IN ULONG_PTR EndingAddress,
1235     IN PMMVAD Vad
1236 );
1237
1238 ULONG
1239 NTAPI
1240 MiMakeSystemAddressValid(
1241     IN PVOID PageTableVirtualAddress,
1242     IN PEPROCESS CurrentProcess
1243 );
1244
1245 ULONG
1246 NTAPI
1247 MiMakeSystemAddressValidPfn(
1248     IN PVOID VirtualAddress,
1249     IN KIRQL OldIrql
1250 );
1251
1252 VOID
1253 NTAPI
1254 MiRemoveMappedView(
1255     IN PEPROCESS CurrentProcess,
1256     IN PMMVAD Vad
1257 );
1258
1259 PSUBSECTION
1260 NTAPI
1261 MiLocateSubsection(
1262     IN PMMVAD Vad,
1263     IN ULONG_PTR Vpn
1264 );
1265
1266 //
1267 // MiRemoveZeroPage will use inline code to zero out the page manually if only
1268 // free pages are available. In some scenarios, we don't/can't run that piece of
1269 // code and would rather only have a real zero page. If we can't have a zero page,
1270 // then we'd like to have our own code to grab a free page and zero it out, by
1271 // using MiRemoveAnyPage. This macro implements this.
1272 //
1273 PFN_NUMBER
1274 FORCEINLINE
1275 MiRemoveZeroPageSafe(IN ULONG Color)
1276 {
1277     if (MmFreePagesByColor[ZeroedPageList][Color].Flink != LIST_HEAD) return MiRemoveZeroPage(Color);
1278     return 0;
1279 }
1280
1281 //
1282 // New ARM3<->RosMM PAGE Architecture
1283 //
1284 #define MI_GET_ROS_DATA(x)   ((PMMROSPFN)(x->RosMmData))
1285 #define MI_IS_ROS_PFN(x)     (((x)->u4.AweAllocation == TRUE) && (MI_GET_ROS_DATA(x) != NULL))
1286 #define ASSERT_IS_ROS_PFN(x) ASSERT(MI_IS_ROS_PFN(x) == TRUE);
1287 typedef struct _MMROSPFN
1288 {
1289     PMM_RMAP_ENTRY RmapListHead;
1290     SWAPENTRY SwapEntry;
1291 } MMROSPFN, *PMMROSPFN;
1292
1293 #define RosMmData            AweReferenceCount
1294
1295 /* EOF */