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c79b31d4e07b2f11d2f408e06e1ac732191c2af4
[reactos.git] / reactos / ntoskrnl / mm / ARM3 / mminit.c
1 /*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/mminit.c
5 * PURPOSE: ARM Memory Manager Initialization
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9 /* INCLUDES *******************************************************************/
10
11 #include <ntoskrnl.h>
12 #define NDEBUG
13 #include <debug.h>
14
15 #line 15 "ARM³::INIT"
16 #define MODULE_INVOLVED_IN_ARM3
17 #include "miarm.h"
18
19 /* GLOBALS ********************************************************************/
20
21 //
22 // These are all registry-configurable, but by default, the memory manager will
23 // figure out the most appropriate values.
24 //
25 ULONG MmMaximumNonPagedPoolPercent;
26 ULONG MmSizeOfNonPagedPoolInBytes;
27 ULONG MmMaximumNonPagedPoolInBytes;
28
29 /* Some of the same values, in pages */
30 PFN_NUMBER MmMaximumNonPagedPoolInPages;
31
32 //
33 // These numbers describe the discrete equation components of the nonpaged
34 // pool sizing algorithm.
35 //
36 // They are described on http://support.microsoft.com/default.aspx/kb/126402/ja
37 // along with the algorithm that uses them, which is implemented later below.
38 //
39 ULONG MmMinimumNonPagedPoolSize = 256 * 1024;
40 ULONG MmMinAdditionNonPagedPoolPerMb = 32 * 1024;
41 ULONG MmDefaultMaximumNonPagedPool = 1024 * 1024;
42 ULONG MmMaxAdditionNonPagedPoolPerMb = 400 * 1024;
43
44 //
45 // The memory layout (and especially variable names) of the NT kernel mode
46 // components can be a bit hard to twig, especially when it comes to the non
47 // paged area.
48 //
49 // There are really two components to the non-paged pool:
50 //
51 // - The initial nonpaged pool, sized dynamically up to a maximum.
52 // - The expansion nonpaged pool, sized dynamically up to a maximum.
53 //
54 // The initial nonpaged pool is physically continuous for performance, and
55 // immediately follows the PFN database, typically sharing the same PDE. It is
56 // a very small resource (32MB on a 1GB system), and capped at 128MB.
57 //
58 // Right now we call this the "ARM³ Nonpaged Pool" and it begins somewhere after
59 // the PFN database (which starts at 0xB0000000).
60 //
61 // The expansion nonpaged pool, on the other hand, can grow much bigger (400MB
62 // for a 1GB system). On ARM³ however, it is currently capped at 128MB.
63 //
64 // The address where the initial nonpaged pool starts is aptly named
65 // MmNonPagedPoolStart, and it describes a range of MmSizeOfNonPagedPoolInBytes
66 // bytes.
67 //
68 // Expansion nonpaged pool starts at an address described by the variable called
69 // MmNonPagedPoolExpansionStart, and it goes on for MmMaximumNonPagedPoolInBytes
70 // minus MmSizeOfNonPagedPoolInBytes bytes, always reaching MmNonPagedPoolEnd
71 // (because of the way it's calculated) at 0xFFBE0000.
72 //
73 // Initial nonpaged pool is allocated and mapped early-on during boot, but what
74 // about the expansion nonpaged pool? It is instead composed of special pages
75 // which belong to what are called System PTEs. These PTEs are the matter of a
76 // later discussion, but they are also considered part of the "nonpaged" OS, due
77 // to the fact that they are never paged out -- once an address is described by
78 // a System PTE, it is always valid, until the System PTE is torn down.
79 //
80 // System PTEs are actually composed of two "spaces", the system space proper,
81 // and the nonpaged pool expansion space. The latter, as we've already seen,
82 // begins at MmNonPagedPoolExpansionStart. Based on the number of System PTEs
83 // that the system will support, the remaining address space below this address
84 // is used to hold the system space PTEs. This address, in turn, is held in the
85 // variable named MmNonPagedSystemStart, which itself is never allowed to go
86 // below 0xEB000000 (thus creating an upper bound on the number of System PTEs).
87 //
88 // This means that 330MB are reserved for total nonpaged system VA, on top of
89 // whatever the initial nonpaged pool allocation is.
90 //
91 // The following URLs, valid as of April 23rd, 2008, support this evidence:
92 //
93 // http://www.cs.miami.edu/~burt/journal/NT/memory.html
94 // http://www.ditii.com/2007/09/28/windows-memory-management-x86-virtual-address-space/
95 //
96 PVOID MmNonPagedSystemStart;
97 PVOID MmNonPagedPoolStart;
98 PVOID MmNonPagedPoolExpansionStart;
99 PVOID MmNonPagedPoolEnd = MI_NONPAGED_POOL_END;
100
101 //
102 // This is where paged pool starts by default
103 //
104 PVOID MmPagedPoolStart = MI_PAGED_POOL_START;
105 PVOID MmPagedPoolEnd;
106
107 //
108 // And this is its default size
109 //
110 ULONG MmSizeOfPagedPoolInBytes = MI_MIN_INIT_PAGED_POOLSIZE;
111 PFN_NUMBER MmSizeOfPagedPoolInPages = MI_MIN_INIT_PAGED_POOLSIZE / PAGE_SIZE;
112
113 //
114 // Session space starts at 0xBFFFFFFF and grows downwards
115 // By default, it includes an 8MB image area where we map win32k and video card
116 // drivers, followed by a 4MB area containing the session's working set. This is
117 // then followed by a 20MB mapped view area and finally by the session's paged
118 // pool, by default 16MB.
119 //
120 // On a normal system, this results in session space occupying the region from
121 // 0xBD000000 to 0xC0000000
122 //
123 // See miarm.h for the defines that determine the sizing of this region. On an
124 // NT system, some of these can be configured through the registry, but we don't
125 // support that yet.
126 //
127 PVOID MiSessionSpaceEnd; // 0xC0000000
128 PVOID MiSessionImageEnd; // 0xC0000000
129 PVOID MiSessionImageStart; // 0xBF800000
130 PVOID MiSessionViewStart; // 0xBE000000
131 PVOID MiSessionPoolEnd; // 0xBE000000
132 PVOID MiSessionPoolStart; // 0xBD000000
133 PVOID MmSessionBase; // 0xBD000000
134 ULONG MmSessionSize;
135 ULONG MmSessionViewSize;
136 ULONG MmSessionPoolSize;
137 ULONG MmSessionImageSize;
138
139 /*
140 * These are the PTE addresses of the boundaries carved out above
141 */
142 PMMPTE MiSessionImagePteStart;
143 PMMPTE MiSessionImagePteEnd;
144 PMMPTE MiSessionBasePte;
145 PMMPTE MiSessionLastPte;
146
147 //
148 // The system view space, on the other hand, is where sections that are memory
149 // mapped into "system space" end up.
150 //
151 // By default, it is a 16MB region.
152 //
153 PVOID MiSystemViewStart;
154 ULONG MmSystemViewSize;
155
156 //
157 // A copy of the system page directory (the page directory associated with the
158 // System process) is kept (double-mapped) by the manager in order to lazily
159 // map paged pool PDEs into external processes when they fault on a paged pool
160 // address.
161 //
162 PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
163 PMMPTE MmSystemPagePtes;
164
165 //
166 // The system cache starts right after hyperspace. The first few pages are for
167 // keeping track of the system working set list.
168 //
169 // This should be 0xC0C00000 -- the cache itself starts at 0xC1000000
170 //
171 PMMWSL MmSystemCacheWorkingSetList = MI_SYSTEM_CACHE_WS_START;
172
173 //
174 // Windows NT seems to choose between 7000, 11000 and 50000
175 // On systems with more than 32MB, this number is then doubled, and further
176 // aligned up to a PDE boundary (4MB).
177 //
178 ULONG MmNumberOfSystemPtes;
179
180 //
181 // This is how many pages the PFN database will take up
182 // In Windows, this includes the Quark Color Table, but not in ARM³
183 //
184 ULONG MxPfnAllocation;
185
186 //
187 // Unlike the old ReactOS Memory Manager, ARM³ (and Windows) does not keep track
188 // of pages that are not actually valid physical memory, such as ACPI reserved
189 // regions, BIOS address ranges, or holes in physical memory address space which
190 // could indicate device-mapped I/O memory.
191 //
192 // In fact, the lack of a PFN entry for a page usually indicates that this is
193 // I/O space instead.
194 //
195 // A bitmap, called the PFN bitmap, keeps track of all page frames by assigning
196 // a bit to each. If the bit is set, then the page is valid physical RAM.
197 //
198 RTL_BITMAP MiPfnBitMap;
199
200 //
201 // This structure describes the different pieces of RAM-backed address space
202 //
203 PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
204
205 //
206 // This is where we keep track of the most basic physical layout markers
207 //
208 ULONG MmNumberOfPhysicalPages, MmHighestPhysicalPage, MmLowestPhysicalPage = -1;
209
210 //
211 // The total number of pages mapped by the boot loader, which include the kernel
212 // HAL, boot drivers, registry, NLS files and other loader data structures is
213 // kept track of here. This depends on "LoaderPagesSpanned" being correct when
214 // coming from the loader.
215 //
216 // This number is later aligned up to a PDE boundary.
217 //
218 ULONG MmBootImageSize;
219
220 //
221 // These three variables keep track of the core separation of address space that
222 // exists between kernel mode and user mode.
223 //
224 ULONG MmUserProbeAddress;
225 PVOID MmHighestUserAddress;
226 PVOID MmSystemRangeStart;
227
228 /* And these store the respective highest PTE/PDE address */
229 PMMPTE MiHighestUserPte;
230 PMMPDE MiHighestUserPde;
231
232 /* These variables define the system cache address space */
233 PVOID MmSystemCacheStart;
234 PVOID MmSystemCacheEnd;
235 MMSUPPORT MmSystemCacheWs;
236
237 //
238 // This is where hyperspace ends (followed by the system cache working set)
239 //
240 PVOID MmHyperSpaceEnd;
241
242 //
243 // Page coloring algorithm data
244 //
245 ULONG MmSecondaryColors;
246 ULONG MmSecondaryColorMask;
247
248 //
249 // Actual (registry-configurable) size of a GUI thread's stack
250 //
251 ULONG MmLargeStackSize = KERNEL_LARGE_STACK_SIZE;
252
253 //
254 // Before we have a PFN database, memory comes straight from our physical memory
255 // blocks, which is nice because it's guaranteed contiguous and also because once
256 // we take a page from here, the system doesn't see it anymore.
257 // However, once the fun is over, those pages must be re-integrated back into
258 // PFN society life, and that requires us keeping a copy of the original layout
259 // so that we can parse it later.
260 //
261 PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
262 MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
263
264 /*
265 * For each page's worth bytes of L2 cache in a given set/way line, the zero and
266 * free lists are organized in what is called a "color".
267 *
268 * This array points to the two lists, so it can be thought of as a multi-dimensional
269 * array of MmFreePagesByColor[2][MmSecondaryColors]. Since the number is dynamic,
270 * we describe the array in pointer form instead.
271 *
272 * On a final note, the color tables themselves are right after the PFN database.
273 */
274 C_ASSERT(FreePageList == 1);
275 PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
276
277 /* An event used in Phase 0 before the rest of the system is ready to go */
278 KEVENT MiTempEvent;
279
280 /* All the events used for memory threshold notifications */
281 PKEVENT MiLowMemoryEvent;
282 PKEVENT MiHighMemoryEvent;
283 PKEVENT MiLowPagedPoolEvent;
284 PKEVENT MiHighPagedPoolEvent;
285 PKEVENT MiLowNonPagedPoolEvent;
286 PKEVENT MiHighNonPagedPoolEvent;
287
288 /* The actual thresholds themselves, in page numbers */
289 PFN_NUMBER MmLowMemoryThreshold;
290 PFN_NUMBER MmHighMemoryThreshold;
291 PFN_NUMBER MiLowPagedPoolThreshold;
292 PFN_NUMBER MiHighPagedPoolThreshold;
293 PFN_NUMBER MiLowNonPagedPoolThreshold;
294 PFN_NUMBER MiHighNonPagedPoolThreshold;
295
296 /*
297 * This number determines how many free pages must exist, at minimum, until we
298 * start trimming working sets and flushing modified pages to obtain more free
299 * pages.
300 *
301 * This number changes if the system detects that this is a server product
302 */
303 PFN_NUMBER MmMinimumFreePages = 26;
304
305 /*
306 * This number indicates how many pages we consider to be a low limit of having
307 * "plenty" of free memory.
308 *
309 * It is doubled on systems that have more than 63MB of memory
310 */
311 PFN_NUMBER MmPlentyFreePages = 400;
312
313 /* These values store the type of system this is (small, med, large) and if server */
314 ULONG MmProductType;
315 MM_SYSTEMSIZE MmSystemSize;
316
317 /*
318 * These values store the cache working set minimums and maximums, in pages
319 *
320 * The minimum value is boosted on systems with more than 24MB of RAM, and cut
321 * down to only 32 pages on embedded (<24MB RAM) systems.
322 *
323 * An extra boost of 2MB is given on systems with more than 33MB of RAM.
324 */
325 PFN_NUMBER MmSystemCacheWsMinimum = 288;
326 PFN_NUMBER MmSystemCacheWsMaximum = 350;
327
328 /* FIXME: Move to cache/working set code later */
329 BOOLEAN MmLargeSystemCache;
330
331 /* PRIVATE FUNCTIONS **********************************************************/
332
333 //
334 // In Bavaria, this is probably a hate crime
335 //
336 VOID
337 FASTCALL
338 MiSyncARM3WithROS(IN PVOID AddressStart,
339 IN PVOID AddressEnd)
340 {
341 //
342 // Puerile piece of junk-grade carbonized horseshit puss sold to the lowest bidder
343 //
344 ULONG Pde = ADDR_TO_PDE_OFFSET(AddressStart);
345 while (Pde <= ADDR_TO_PDE_OFFSET(AddressEnd))
346 {
347 //
348 // This both odious and heinous
349 //
350 extern ULONG MmGlobalKernelPageDirectory[1024];
351 MmGlobalKernelPageDirectory[Pde] = ((PULONG)PDE_BASE)[Pde];
352 Pde++;
353 }
354 }
355
356 PFN_NUMBER
357 NTAPI
358 MxGetNextPage(IN PFN_NUMBER PageCount)
359 {
360 PFN_NUMBER Pfn;
361
362 /* Make sure we have enough pages */
363 if (PageCount > MxFreeDescriptor->PageCount)
364 {
365 /* Crash the system */
366 KeBugCheckEx(INSTALL_MORE_MEMORY,
367 MmNumberOfPhysicalPages,
368 MxFreeDescriptor->PageCount,
369 MxOldFreeDescriptor.PageCount,
370 PageCount);
371 }
372
373 /* Use our lowest usable free pages */
374 Pfn = MxFreeDescriptor->BasePage;
375 MxFreeDescriptor->BasePage += PageCount;
376 MxFreeDescriptor->PageCount -= PageCount;
377 return Pfn;
378 }
379
380 VOID
381 NTAPI
382 MiComputeColorInformation(VOID)
383 {
384 ULONG L2Associativity;
385
386 /* Check if no setting was provided already */
387 if (!MmSecondaryColors)
388 {
389 /* Get L2 cache information */
390 L2Associativity = KeGetPcr()->SecondLevelCacheAssociativity;
391
392 /* The number of colors is the number of cache bytes by set/way */
393 MmSecondaryColors = KeGetPcr()->SecondLevelCacheSize;
394 if (L2Associativity) MmSecondaryColors /= L2Associativity;
395 }
396
397 /* Now convert cache bytes into pages */
398 MmSecondaryColors >>= PAGE_SHIFT;
399 if (!MmSecondaryColors)
400 {
401 /* If there was no cache data from the KPCR, use the default colors */
402 MmSecondaryColors = MI_SECONDARY_COLORS;
403 }
404 else
405 {
406 /* Otherwise, make sure there aren't too many colors */
407 if (MmSecondaryColors > MI_MAX_SECONDARY_COLORS)
408 {
409 /* Set the maximum */
410 MmSecondaryColors = MI_MAX_SECONDARY_COLORS;
411 }
412
413 /* Make sure there aren't too little colors */
414 if (MmSecondaryColors < MI_MIN_SECONDARY_COLORS)
415 {
416 /* Set the default */
417 MmSecondaryColors = MI_SECONDARY_COLORS;
418 }
419
420 /* Finally make sure the colors are a power of two */
421 if (MmSecondaryColors & (MmSecondaryColors - 1))
422 {
423 /* Set the default */
424 MmSecondaryColors = MI_SECONDARY_COLORS;
425 }
426 }
427
428 /* Compute the mask and store it */
429 MmSecondaryColorMask = MmSecondaryColors - 1;
430 KeGetCurrentPrcb()->SecondaryColorMask = MmSecondaryColorMask;
431 }
432
433 VOID
434 NTAPI
435 MiInitializeColorTables(VOID)
436 {
437 ULONG i;
438 PMMPTE PointerPte, LastPte;
439 MMPTE TempPte = ValidKernelPte;
440
441 /* The color table starts after the ARM3 PFN database */
442 MmFreePagesByColor[0] = (PMMCOLOR_TABLES)&MmPfnDatabase[MmHighestPhysicalPage + 1];
443
444 /* Loop the PTEs. We have two color tables for each secondary color */
445 PointerPte = MiAddressToPte(&MmFreePagesByColor[0][0]);
446 LastPte = MiAddressToPte((ULONG_PTR)MmFreePagesByColor[0] +
447 (2 * MmSecondaryColors * sizeof(MMCOLOR_TABLES))
448 - 1);
449 while (PointerPte <= LastPte)
450 {
451 /* Check for valid PTE */
452 if (PointerPte->u.Hard.Valid == 0)
453 {
454 /* Get a page and map it */
455 TempPte.u.Hard.PageFrameNumber = MxGetNextPage(1);
456 ASSERT(TempPte.u.Hard.Valid == 1);
457 *PointerPte = TempPte;
458
459 /* Zero out the page */
460 RtlZeroMemory(MiPteToAddress(PointerPte), PAGE_SIZE);
461 }
462
463 /* Next */
464 PointerPte++;
465 }
466
467 /* Now set the address of the next list, right after this one */
468 MmFreePagesByColor[1] = &MmFreePagesByColor[0][MmSecondaryColors];
469
470 /* Now loop the lists to set them up */
471 for (i = 0; i < MmSecondaryColors; i++)
472 {
473 /* Set both free and zero lists for each color */
474 MmFreePagesByColor[ZeroedPageList][i].Flink = 0xFFFFFFFF;
475 MmFreePagesByColor[ZeroedPageList][i].Blink = (PVOID)0xFFFFFFFF;
476 MmFreePagesByColor[ZeroedPageList][i].Count = 0;
477 MmFreePagesByColor[FreePageList][i].Flink = 0xFFFFFFFF;
478 MmFreePagesByColor[FreePageList][i].Blink = (PVOID)0xFFFFFFFF;
479 MmFreePagesByColor[FreePageList][i].Count = 0;
480 }
481 }
482
483 BOOLEAN
484 NTAPI
485 MiIsRegularMemory(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
486 IN PFN_NUMBER Pfn)
487 {
488 PLIST_ENTRY NextEntry;
489 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock;
490
491 /* Loop the memory descriptors */
492 NextEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
493 while (NextEntry != &LoaderBlock->MemoryDescriptorListHead)
494 {
495 /* Get the memory descriptor */
496 MdBlock = CONTAINING_RECORD(NextEntry,
497 MEMORY_ALLOCATION_DESCRIPTOR,
498 ListEntry);
499
500 /* Check if this PFN could be part of the block */
501 if (Pfn >= (MdBlock->BasePage))
502 {
503 /* Check if it really is part of the block */
504 if (Pfn < (MdBlock->BasePage + MdBlock->PageCount))
505 {
506 /* Check if the block is actually memory we don't map */
507 if ((MdBlock->MemoryType == LoaderFirmwarePermanent) ||
508 (MdBlock->MemoryType == LoaderBBTMemory) ||
509 (MdBlock->MemoryType == LoaderSpecialMemory))
510 {
511 /* We don't need PFN database entries for this memory */
512 break;
513 }
514
515 /* This is memory we want to map */
516 return TRUE;
517 }
518 }
519 else
520 {
521 /* Blocks are ordered, so if it's not here, it doesn't exist */
522 break;
523 }
524
525 /* Get to the next descriptor */
526 NextEntry = MdBlock->ListEntry.Flink;
527 }
528
529 /* Check if this PFN is actually from our free memory descriptor */
530 if ((Pfn >= MxOldFreeDescriptor.BasePage) &&
531 (Pfn < MxOldFreeDescriptor.BasePage + MxOldFreeDescriptor.PageCount))
532 {
533 /* We use these pages for initial mappings, so we do want to count them */
534 return TRUE;
535 }
536
537 /* Otherwise this isn't memory that we describe or care about */
538 return FALSE;
539 }
540
541 VOID
542 NTAPI
543 MiMapPfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
544 {
545 ULONG FreePage, FreePageCount, PagesLeft, BasePage, PageCount;
546 PLIST_ENTRY NextEntry;
547 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock;
548 PMMPTE PointerPte, LastPte;
549 MMPTE TempPte = ValidKernelPte;
550
551 /* Get current page data, since we won't be using MxGetNextPage as it would corrupt our state */
552 FreePage = MxFreeDescriptor->BasePage;
553 FreePageCount = MxFreeDescriptor->PageCount;
554 PagesLeft = 0;
555
556 /* Loop the memory descriptors */
557 NextEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
558 while (NextEntry != &LoaderBlock->MemoryDescriptorListHead)
559 {
560 /* Get the descriptor */
561 MdBlock = CONTAINING_RECORD(NextEntry,
562 MEMORY_ALLOCATION_DESCRIPTOR,
563 ListEntry);
564 if ((MdBlock->MemoryType == LoaderFirmwarePermanent) ||
565 (MdBlock->MemoryType == LoaderBBTMemory) ||
566 (MdBlock->MemoryType == LoaderSpecialMemory))
567 {
568 /* These pages are not part of the PFN database */
569 NextEntry = MdBlock->ListEntry.Flink;
570 continue;
571 }
572
573 /* Next, check if this is our special free descriptor we've found */
574 if (MdBlock == MxFreeDescriptor)
575 {
576 /* Use the real numbers instead */
577 BasePage = MxOldFreeDescriptor.BasePage;
578 PageCount = MxOldFreeDescriptor.PageCount;
579 }
580 else
581 {
582 /* Use the descriptor's numbers */
583 BasePage = MdBlock->BasePage;
584 PageCount = MdBlock->PageCount;
585 }
586
587 /* Get the PTEs for this range */
588 PointerPte = MiAddressToPte(&MmPfnDatabase[BasePage]);
589 LastPte = MiAddressToPte(((ULONG_PTR)&MmPfnDatabase[BasePage + PageCount]) - 1);
590 DPRINT("MD Type: %lx Base: %lx Count: %lx\n", MdBlock->MemoryType, BasePage, PageCount);
591
592 /* Loop them */
593 while (PointerPte <= LastPte)
594 {
595 /* We'll only touch PTEs that aren't already valid */
596 if (PointerPte->u.Hard.Valid == 0)
597 {
598 /* Use the next free page */
599 TempPte.u.Hard.PageFrameNumber = FreePage;
600 ASSERT(FreePageCount != 0);
601
602 /* Consume free pages */
603 FreePage++;
604 FreePageCount--;
605 if (!FreePageCount)
606 {
607 /* Out of memory */
608 KeBugCheckEx(INSTALL_MORE_MEMORY,
609 MmNumberOfPhysicalPages,
610 FreePageCount,
611 MxOldFreeDescriptor.PageCount,
612 1);
613 }
614
615 /* Write out this PTE */
616 PagesLeft++;
617 ASSERT(PointerPte->u.Hard.Valid == 0);
618 ASSERT(TempPte.u.Hard.Valid == 1);
619 *PointerPte = TempPte;
620
621 /* Zero this page */
622 RtlZeroMemory(MiPteToAddress(PointerPte), PAGE_SIZE);
623 }
624
625 /* Next! */
626 PointerPte++;
627 }
628
629 /* Do the next address range */
630 NextEntry = MdBlock->ListEntry.Flink;
631 }
632
633 /* Now update the free descriptors to consume the pages we used up during the PFN allocation loop */
634 MxFreeDescriptor->BasePage = FreePage;
635 MxFreeDescriptor->PageCount = FreePageCount;
636 }
637
638 VOID
639 NTAPI
640 MiBuildPfnDatabaseFromPages(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
641 {
642 PMMPDE PointerPde;
643 PMMPTE PointerPte;
644 ULONG i, Count, j;
645 PFN_NUMBER PageFrameIndex, StartupPdIndex, PtePageIndex;
646 PMMPFN Pfn1, Pfn2;
647 ULONG_PTR BaseAddress = 0;
648
649 /* PFN of the startup page directory */
650 StartupPdIndex = PFN_FROM_PTE(MiAddressToPde(PDE_BASE));
651
652 /* Start with the first PDE and scan them all */
653 PointerPde = MiAddressToPde(NULL);
654 Count = PD_COUNT * PDE_COUNT;
655 for (i = 0; i < Count; i++)
656 {
657 /* Check for valid PDE */
658 if (PointerPde->u.Hard.Valid == 1)
659 {
660 /* Get the PFN from it */
661 PageFrameIndex = PFN_FROM_PTE(PointerPde);
662
663 /* Do we want a PFN entry for this page? */
664 if (MiIsRegularMemory(LoaderBlock, PageFrameIndex))
665 {
666 /* Yes we do, set it up */
667 Pfn1 = MiGetPfnEntry(PageFrameIndex);
668 Pfn1->u4.PteFrame = StartupPdIndex;
669 Pfn1->PteAddress = PointerPde;
670 Pfn1->u2.ShareCount++;
671 Pfn1->u3.e2.ReferenceCount = 1;
672 Pfn1->u3.e1.PageLocation = ActiveAndValid;
673 Pfn1->u3.e1.CacheAttribute = MiNonCached;
674 }
675 else
676 {
677 /* No PFN entry */
678 Pfn1 = NULL;
679 }
680
681 /* Now get the PTE and scan the pages */
682 PointerPte = MiAddressToPte(BaseAddress);
683 for (j = 0; j < PTE_COUNT; j++)
684 {
685 /* Check for a valid PTE */
686 if (PointerPte->u.Hard.Valid == 1)
687 {
688 /* Increase the shared count of the PFN entry for the PDE */
689 ASSERT(Pfn1 != NULL);
690 Pfn1->u2.ShareCount++;
691
692 /* Now check if the PTE is valid memory too */
693 PtePageIndex = PFN_FROM_PTE(PointerPte);
694 if (MiIsRegularMemory(LoaderBlock, PtePageIndex))
695 {
696 /*
697 * Only add pages above the end of system code or pages
698 * that are part of nonpaged pool
699 */
700 if ((BaseAddress >= 0xA0000000) ||
701 ((BaseAddress >= (ULONG_PTR)MmNonPagedPoolStart) &&
702 (BaseAddress < (ULONG_PTR)MmNonPagedPoolStart +
703 MmSizeOfNonPagedPoolInBytes)))
704 {
705 /* Get the PFN entry and make sure it too is valid */
706 Pfn2 = MiGetPfnEntry(PtePageIndex);
707 if ((MmIsAddressValid(Pfn2)) &&
708 (MmIsAddressValid(Pfn2 + 1)))
709 {
710 /* Setup the PFN entry */
711 Pfn2->u4.PteFrame = PageFrameIndex;
712 Pfn2->PteAddress = PointerPte;
713 Pfn2->u2.ShareCount++;
714 Pfn2->u3.e2.ReferenceCount = 1;
715 Pfn2->u3.e1.PageLocation = ActiveAndValid;
716 Pfn2->u3.e1.CacheAttribute = MiNonCached;
717 }
718 }
719 }
720 }
721
722 /* Next PTE */
723 PointerPte++;
724 BaseAddress += PAGE_SIZE;
725 }
726 }
727 else
728 {
729 /* Next PDE mapped address */
730 BaseAddress += PDE_MAPPED_VA;
731 }
732
733 /* Next PTE */
734 PointerPde++;
735 }
736 }
737
738 VOID
739 NTAPI
740 MiBuildPfnDatabaseZeroPage(VOID)
741 {
742 PMMPFN Pfn1;
743 PMMPDE PointerPde;
744
745 /* Grab the lowest page and check if it has no real references */
746 Pfn1 = MiGetPfnEntry(MmLowestPhysicalPage);
747 if (!(MmLowestPhysicalPage) && !(Pfn1->u3.e2.ReferenceCount))
748 {
749 /* Make it a bogus page to catch errors */
750 PointerPde = MiAddressToPde(0xFFFFFFFF);
751 Pfn1->u4.PteFrame = PFN_FROM_PTE(PointerPde);
752 Pfn1->PteAddress = PointerPde;
753 Pfn1->u2.ShareCount++;
754 Pfn1->u3.e2.ReferenceCount = 0xFFF0;
755 Pfn1->u3.e1.PageLocation = ActiveAndValid;
756 Pfn1->u3.e1.CacheAttribute = MiNonCached;
757 }
758 }
759
760 VOID
761 NTAPI
762 MiBuildPfnDatabaseFromLoaderBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
763 {
764 PLIST_ENTRY NextEntry;
765 PFN_NUMBER PageCount = 0;
766 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock;
767 PFN_NUMBER PageFrameIndex;
768 PMMPFN Pfn1;
769 PMMPTE PointerPte;
770 PMMPDE PointerPde;
771 KIRQL OldIrql;
772
773 /* Now loop through the descriptors */
774 NextEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
775 while (NextEntry != &LoaderBlock->MemoryDescriptorListHead)
776 {
777 /* Get the current descriptor */
778 MdBlock = CONTAINING_RECORD(NextEntry,
779 MEMORY_ALLOCATION_DESCRIPTOR,
780 ListEntry);
781
782 /* Read its data */
783 PageCount = MdBlock->PageCount;
784 PageFrameIndex = MdBlock->BasePage;
785
786 /* Don't allow memory above what the PFN database is mapping */
787 if (PageFrameIndex > MmHighestPhysicalPage)
788 {
789 /* Since they are ordered, everything past here will be larger */
790 break;
791 }
792
793 /* On the other hand, the end page might be higher up... */
794 if ((PageFrameIndex + PageCount) > (MmHighestPhysicalPage + 1))
795 {
796 /* In which case we'll trim the descriptor to go as high as we can */
797 PageCount = MmHighestPhysicalPage + 1 - PageFrameIndex;
798 MdBlock->PageCount = PageCount;
799
800 /* But if there's nothing left to trim, we got too high, so quit */
801 if (!PageCount) break;
802 }
803
804 /* Now check the descriptor type */
805 switch (MdBlock->MemoryType)
806 {
807 /* Check for bad RAM */
808 case LoaderBad:
809
810 DPRINT1("You have damaged RAM modules. Stopping boot\n");
811 while (TRUE);
812 break;
813
814 /* Check for free RAM */
815 case LoaderFree:
816 case LoaderLoadedProgram:
817 case LoaderFirmwareTemporary:
818 case LoaderOsloaderStack:
819
820 /* Get the last page of this descriptor. Note we loop backwards */
821 PageFrameIndex += PageCount - 1;
822 Pfn1 = MiGetPfnEntry(PageFrameIndex);
823
824 /* Lock the PFN Database */
825 OldIrql = KeAcquireQueuedSpinLock(LockQueuePfnLock);
826 while (PageCount--)
827 {
828 /* If the page really has no references, mark it as free */
829 if (!Pfn1->u3.e2.ReferenceCount)
830 {
831 /* Add it to the free list */
832 Pfn1->u3.e1.CacheAttribute = MiNonCached;
833 MiInsertPageInFreeList(PageFrameIndex);
834 }
835
836 /* Go to the next page */
837 Pfn1--;
838 PageFrameIndex--;
839 }
840
841 /* Release PFN database */
842 KeReleaseQueuedSpinLock(LockQueuePfnLock, OldIrql);
843
844 /* Done with this block */
845 break;
846
847 /* Check for pages that are invisible to us */
848 case LoaderFirmwarePermanent:
849 case LoaderSpecialMemory:
850 case LoaderBBTMemory:
851
852 /* And skip them */
853 break;
854
855 default:
856
857 /* Map these pages with the KSEG0 mapping that adds 0x80000000 */
858 PointerPte = MiAddressToPte(KSEG0_BASE + (PageFrameIndex << PAGE_SHIFT));
859 Pfn1 = MiGetPfnEntry(PageFrameIndex);
860 while (PageCount--)
861 {
862 /* Check if the page is really unused */
863 PointerPde = MiAddressToPde(KSEG0_BASE + (PageFrameIndex << PAGE_SHIFT));
864 if (!Pfn1->u3.e2.ReferenceCount)
865 {
866 /* Mark it as being in-use */
867 Pfn1->u4.PteFrame = PFN_FROM_PTE(PointerPde);
868 Pfn1->PteAddress = PointerPte;
869 Pfn1->u2.ShareCount++;
870 Pfn1->u3.e2.ReferenceCount = 1;
871 Pfn1->u3.e1.PageLocation = ActiveAndValid;
872 Pfn1->u3.e1.CacheAttribute = MiNonCached;
873
874 /* Check for RAM disk page */
875 if (MdBlock->MemoryType == LoaderXIPRom)
876 {
877 /* Make it a pseudo-I/O ROM mapping */
878 Pfn1->u1.Flink = 0;
879 Pfn1->u2.ShareCount = 0;
880 Pfn1->u3.e2.ReferenceCount = 0;
881 Pfn1->u3.e1.PageLocation = 0;
882 Pfn1->u3.e1.Rom = 1;
883 Pfn1->u4.InPageError = 0;
884 Pfn1->u3.e1.PrototypePte = 1;
885 }
886 }
887
888 /* Advance page structures */
889 Pfn1++;
890 PageFrameIndex++;
891 PointerPte++;
892 }
893 break;
894 }
895
896 /* Next descriptor entry */
897 NextEntry = MdBlock->ListEntry.Flink;
898 }
899 }
900
901 VOID
902 NTAPI
903 MiBuildPfnDatabaseSelf(VOID)
904 {
905 PMMPTE PointerPte, LastPte;
906 PMMPFN Pfn1;
907
908 /* Loop the PFN database page */
909 PointerPte = MiAddressToPte(MiGetPfnEntry(MmLowestPhysicalPage));
910 LastPte = MiAddressToPte(MiGetPfnEntry(MmHighestPhysicalPage));
911 while (PointerPte <= LastPte)
912 {
913 /* Make sure the page is valid */
914 if (PointerPte->u.Hard.Valid == 1)
915 {
916 /* Get the PFN entry and just mark it referenced */
917 Pfn1 = MiGetPfnEntry(PointerPte->u.Hard.PageFrameNumber);
918 Pfn1->u2.ShareCount = 1;
919 Pfn1->u3.e2.ReferenceCount = 1;
920 }
921
922 /* Next */
923 PointerPte++;
924 }
925 }
926
927 VOID
928 NTAPI
929 MiInitializePfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
930 {
931 /* Scan memory and start setting up PFN entries */
932 MiBuildPfnDatabaseFromPages(LoaderBlock);
933
934 /* Add the zero page */
935 MiBuildPfnDatabaseZeroPage();
936
937 /* Scan the loader block and build the rest of the PFN database */
938 MiBuildPfnDatabaseFromLoaderBlock(LoaderBlock);
939
940 /* Finally add the pages for the PFN database itself */
941 MiBuildPfnDatabaseSelf();
942 }
943
944 VOID
945 NTAPI
946 MiAdjustWorkingSetManagerParameters(IN BOOLEAN Client)
947 {
948 /* This function needs to do more work, for now, we tune page minimums */
949
950 /* Check for a system with around 64MB RAM or more */
951 if (MmNumberOfPhysicalPages >= (63 * _1MB) / PAGE_SIZE)
952 {
953 /* Double the minimum amount of pages we consider for a "plenty free" scenario */
954 MmPlentyFreePages *= 2;
955 }
956 }
957
958 VOID
959 NTAPI
960 MiNotifyMemoryEvents(VOID)
961 {
962 /* Are we in a low-memory situation? */
963 if (MmAvailablePages < MmLowMemoryThreshold)
964 {
965 /* Clear high, set low */
966 if (KeReadStateEvent(MiHighMemoryEvent)) KeClearEvent(MiHighMemoryEvent);
967 if (!KeReadStateEvent(MiLowMemoryEvent)) KeSetEvent(MiLowMemoryEvent, 0, FALSE);
968 }
969 else if (MmAvailablePages < MmHighMemoryThreshold)
970 {
971 /* We are in between, clear both */
972 if (KeReadStateEvent(MiHighMemoryEvent)) KeClearEvent(MiHighMemoryEvent);
973 if (KeReadStateEvent(MiLowMemoryEvent)) KeClearEvent(MiLowMemoryEvent);
974 }
975 else
976 {
977 /* Clear low, set high */
978 if (KeReadStateEvent(MiLowMemoryEvent)) KeClearEvent(MiLowMemoryEvent);
979 if (!KeReadStateEvent(MiHighMemoryEvent)) KeSetEvent(MiHighMemoryEvent, 0, FALSE);
980 }
981 }
982
983 NTSTATUS
984 NTAPI
985 MiCreateMemoryEvent(IN PUNICODE_STRING Name,
986 OUT PKEVENT *Event)
987 {
988 PACL Dacl;
989 HANDLE EventHandle;
990 ULONG DaclLength;
991 NTSTATUS Status;
992 OBJECT_ATTRIBUTES ObjectAttributes;
993 SECURITY_DESCRIPTOR SecurityDescriptor;
994
995 /* Create the SD */
996 Status = RtlCreateSecurityDescriptor(&SecurityDescriptor,
997 SECURITY_DESCRIPTOR_REVISION);
998 if (!NT_SUCCESS(Status)) return Status;
999
1000 /* One ACL with 3 ACEs, containing each one SID */
1001 DaclLength = sizeof(ACL) +
1002 3 * sizeof(ACCESS_ALLOWED_ACE) +
1003 RtlLengthSid(SeLocalSystemSid) +
1004 RtlLengthSid(SeAliasAdminsSid) +
1005 RtlLengthSid(SeWorldSid);
1006
1007 /* Allocate space for the DACL */
1008 Dacl = ExAllocatePoolWithTag(PagedPool, DaclLength, 'lcaD');
1009 if (!Dacl) return STATUS_INSUFFICIENT_RESOURCES;
1010
1011 /* Setup the ACL inside it */
1012 Status = RtlCreateAcl(Dacl, DaclLength, ACL_REVISION);
1013 if (!NT_SUCCESS(Status)) goto CleanUp;
1014
1015 /* Add query rights for everyone */
1016 Status = RtlAddAccessAllowedAce(Dacl,
1017 ACL_REVISION,
1018 SYNCHRONIZE | EVENT_QUERY_STATE | READ_CONTROL,
1019 SeWorldSid);
1020 if (!NT_SUCCESS(Status)) goto CleanUp;
1021
1022 /* Full rights for the admin */
1023 Status = RtlAddAccessAllowedAce(Dacl,
1024 ACL_REVISION,
1025 EVENT_ALL_ACCESS,
1026 SeAliasAdminsSid);
1027 if (!NT_SUCCESS(Status)) goto CleanUp;
1028
1029 /* As well as full rights for the system */
1030 Status = RtlAddAccessAllowedAce(Dacl,
1031 ACL_REVISION,
1032 EVENT_ALL_ACCESS,
1033 SeLocalSystemSid);
1034 if (!NT_SUCCESS(Status)) goto CleanUp;
1035
1036 /* Set this DACL inside the SD */
1037 Status = RtlSetDaclSecurityDescriptor(&SecurityDescriptor,
1038 TRUE,
1039 Dacl,
1040 FALSE);
1041 if (!NT_SUCCESS(Status)) goto CleanUp;
1042
1043 /* Setup the event attributes, making sure it's a permanent one */
1044 InitializeObjectAttributes(&ObjectAttributes,
1045 Name,
1046 OBJ_KERNEL_HANDLE | OBJ_PERMANENT,
1047 NULL,
1048 &SecurityDescriptor);
1049
1050 /* Create the event */
1051 Status = ZwCreateEvent(&EventHandle,
1052 EVENT_ALL_ACCESS,
1053 &ObjectAttributes,
1054 NotificationEvent,
1055 FALSE);
1056 CleanUp:
1057 /* Free the DACL */
1058 ExFreePool(Dacl);
1059
1060 /* Check if this is the success path */
1061 if (NT_SUCCESS(Status))
1062 {
1063 /* Add a reference to the object, then close the handle we had */
1064 Status = ObReferenceObjectByHandle(EventHandle,
1065 EVENT_MODIFY_STATE,
1066 ExEventObjectType,
1067 KernelMode,
1068 (PVOID*)Event,
1069 NULL);
1070 ZwClose (EventHandle);
1071 }
1072
1073 /* Return status */
1074 return Status;
1075 }
1076
1077 BOOLEAN
1078 NTAPI
1079 MiInitializeMemoryEvents(VOID)
1080 {
1081 UNICODE_STRING LowString = RTL_CONSTANT_STRING(L"\\KernelObjects\\LowMemoryCondition");
1082 UNICODE_STRING HighString = RTL_CONSTANT_STRING(L"\\KernelObjects\\HighMemoryCondition");
1083 UNICODE_STRING LowPagedPoolString = RTL_CONSTANT_STRING(L"\\KernelObjects\\LowPagedPoolCondition");
1084 UNICODE_STRING HighPagedPoolString = RTL_CONSTANT_STRING(L"\\KernelObjects\\HighPagedPoolCondition");
1085 UNICODE_STRING LowNonPagedPoolString = RTL_CONSTANT_STRING(L"\\KernelObjects\\LowNonPagedPoolCondition");
1086 UNICODE_STRING HighNonPagedPoolString = RTL_CONSTANT_STRING(L"\\KernelObjects\\HighNonPagedPoolCondition");
1087 NTSTATUS Status;
1088
1089 /* Check if we have a registry setting */
1090 if (MmLowMemoryThreshold)
1091 {
1092 /* Convert it to pages */
1093 MmLowMemoryThreshold *= (_1MB / PAGE_SIZE);
1094 }
1095 else
1096 {
1097 /* The low memory threshold is hit when we don't consider that we have "plenty" of free pages anymore */
1098 MmLowMemoryThreshold = MmPlentyFreePages;
1099
1100 /* More than one GB of memory? */
1101 if (MmNumberOfPhysicalPages > 0x40000)
1102 {
1103 /* Start at 32MB, and add another 16MB for each GB */
1104 MmLowMemoryThreshold = (32 * _1MB) / PAGE_SIZE;
1105 MmLowMemoryThreshold += ((MmNumberOfPhysicalPages - 0x40000) >> 7);
1106 }
1107 else if (MmNumberOfPhysicalPages > 0x8000)
1108 {
1109 /* For systems with > 128MB RAM, add another 4MB for each 128MB */
1110 MmLowMemoryThreshold += ((MmNumberOfPhysicalPages - 0x8000) >> 5);
1111 }
1112
1113 /* Don't let the minimum threshold go past 64MB */
1114 MmLowMemoryThreshold = min(MmLowMemoryThreshold, (64 * _1MB) / PAGE_SIZE);
1115 }
1116
1117 /* Check if we have a registry setting */
1118 if (MmHighMemoryThreshold)
1119 {
1120 /* Convert it into pages */
1121 MmHighMemoryThreshold *= (_1MB / PAGE_SIZE);
1122 }
1123 else
1124 {
1125 /* Otherwise, the default is three times the low memory threshold */
1126 MmHighMemoryThreshold = 3 * MmLowMemoryThreshold;
1127 ASSERT(MmHighMemoryThreshold > MmLowMemoryThreshold);
1128 }
1129
1130 /* Make sure high threshold is actually higher than the low */
1131 MmHighMemoryThreshold = max(MmHighMemoryThreshold, MmLowMemoryThreshold);
1132
1133 /* Create the memory events for all the thresholds */
1134 Status = MiCreateMemoryEvent(&LowString, &MiLowMemoryEvent);
1135 if (!NT_SUCCESS(Status)) return FALSE;
1136 Status = MiCreateMemoryEvent(&HighString, &MiHighMemoryEvent);
1137 if (!NT_SUCCESS(Status)) return FALSE;
1138 Status = MiCreateMemoryEvent(&LowPagedPoolString, &MiLowPagedPoolEvent);
1139 if (!NT_SUCCESS(Status)) return FALSE;
1140 Status = MiCreateMemoryEvent(&HighPagedPoolString, &MiHighPagedPoolEvent);
1141 if (!NT_SUCCESS(Status)) return FALSE;
1142 Status = MiCreateMemoryEvent(&LowNonPagedPoolString, &MiLowNonPagedPoolEvent);
1143 if (!NT_SUCCESS(Status)) return FALSE;
1144 Status = MiCreateMemoryEvent(&HighNonPagedPoolString, &MiHighNonPagedPoolEvent);
1145 if (!NT_SUCCESS(Status)) return FALSE;
1146
1147 /* Now setup the pool events */
1148 MiInitializePoolEvents();
1149
1150 /* Set the initial event state */
1151 MiNotifyMemoryEvents();
1152 return TRUE;
1153 }
1154
1155 VOID
1156 NTAPI
1157 MiAddHalIoMappings(VOID)
1158 {
1159 PVOID BaseAddress;
1160 PMMPTE PointerPde;
1161 PMMPTE PointerPte;
1162 ULONG i, j, PdeCount;
1163 PFN_NUMBER PageFrameIndex;
1164
1165 /* HAL Heap address -- should be on a PDE boundary */
1166 BaseAddress = (PVOID)0xFFC00000;
1167 ASSERT(MiAddressToPteOffset(BaseAddress) == 0);
1168
1169 /* Check how many PDEs the heap has */
1170 PointerPde = MiAddressToPde(BaseAddress);
1171 PdeCount = PDE_COUNT - ADDR_TO_PDE_OFFSET(BaseAddress);
1172 for (i = 0; i < PdeCount; i++)
1173 {
1174 /* Does the HAL own this mapping? */
1175 if ((PointerPde->u.Hard.Valid == 1) &&
1176 (PointerPde->u.Hard.LargePage == 0))
1177 {
1178 /* Get the PTE for it and scan each page */
1179 PointerPte = MiAddressToPte(BaseAddress);
1180 for (j = 0 ; j < PTE_COUNT; j++)
1181 {
1182 /* Does the HAL own this page? */
1183 if (PointerPte->u.Hard.Valid == 1)
1184 {
1185 /* Is the HAL using it for device or I/O mapped memory? */
1186 PageFrameIndex = PFN_FROM_PTE(PointerPte);
1187 if (!MiGetPfnEntry(PageFrameIndex))
1188 {
1189 /* FIXME: For PAT, we need to track I/O cache attributes for coherency */
1190 DPRINT1("HAL I/O Mapping at %p is unsafe\n", BaseAddress);
1191 }
1192 }
1193
1194 /* Move to the next page */
1195 BaseAddress = (PVOID)((ULONG_PTR)BaseAddress + PAGE_SIZE);
1196 PointerPte++;
1197 }
1198 }
1199 else
1200 {
1201 /* Move to the next address */
1202 BaseAddress = (PVOID)((ULONG_PTR)BaseAddress + PDE_MAPPED_VA);
1203 }
1204
1205 /* Move to the next PDE */
1206 PointerPde++;
1207 }
1208 }
1209
1210 VOID
1211 NTAPI
1212 MmDumpArmPfnDatabase(VOID)
1213 {
1214 ULONG i;
1215 PMMPFN Pfn1;
1216 PCHAR Consumer = "Unknown";
1217 KIRQL OldIrql;
1218 ULONG ActivePages = 0, FreePages = 0, OtherPages = 0;
1219
1220 KeRaiseIrql(HIGH_LEVEL, &OldIrql);
1221
1222 //
1223 // Loop the PFN database
1224 //
1225 for (i = 0; i <= MmHighestPhysicalPage; i++)
1226 {
1227 Pfn1 = MiGetPfnEntry(i);
1228 if (!Pfn1) continue;
1229
1230 //
1231 // Get the page location
1232 //
1233 switch (Pfn1->u3.e1.PageLocation)
1234 {
1235 case ActiveAndValid:
1236
1237 Consumer = "Active and Valid";
1238 ActivePages++;
1239 break;
1240
1241 case FreePageList:
1242
1243 Consumer = "Free Page List";
1244 FreePages++;
1245 break;
1246
1247 default:
1248
1249 Consumer = "Other (ASSERT!)";
1250 OtherPages++;
1251 break;
1252 }
1253
1254 //
1255 // Pretty-print the page
1256 //
1257 DbgPrint("0x%08p:\t%20s\t(%02d.%02d) [%08p-%08p])\n",
1258 i << PAGE_SHIFT,
1259 Consumer,
1260 Pfn1->u3.e2.ReferenceCount,
1261 Pfn1->u2.ShareCount,
1262 Pfn1->PteAddress,
1263 Pfn1->u4.PteFrame);
1264 }
1265
1266 DbgPrint("Active: %d pages\t[%d KB]\n", ActivePages, (ActivePages << PAGE_SHIFT) / 1024);
1267 DbgPrint("Free: %d pages\t[%d KB]\n", FreePages, (FreePages << PAGE_SHIFT) / 1024);
1268 DbgPrint("Other: %d pages\t[%d KB]\n", OtherPages, (OtherPages << PAGE_SHIFT) / 1024);
1269
1270 KeLowerIrql(OldIrql);
1271 }
1272
1273 PFN_NUMBER
1274 NTAPI
1275 MiPagesInLoaderBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
1276 IN PBOOLEAN IncludeType)
1277 {
1278 PLIST_ENTRY NextEntry;
1279 PFN_NUMBER PageCount = 0;
1280 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock;
1281
1282 //
1283 // Now loop through the descriptors
1284 //
1285 NextEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
1286 while (NextEntry != &LoaderBlock->MemoryDescriptorListHead)
1287 {
1288 //
1289 // Grab each one, and check if it's one we should include
1290 //
1291 MdBlock = CONTAINING_RECORD(NextEntry,
1292 MEMORY_ALLOCATION_DESCRIPTOR,
1293 ListEntry);
1294 if ((MdBlock->MemoryType < LoaderMaximum) &&
1295 (IncludeType[MdBlock->MemoryType]))
1296 {
1297 //
1298 // Add this to our running total
1299 //
1300 PageCount += MdBlock->PageCount;
1301 }
1302
1303 //
1304 // Try the next descriptor
1305 //
1306 NextEntry = MdBlock->ListEntry.Flink;
1307 }
1308
1309 //
1310 // Return the total
1311 //
1312 return PageCount;
1313 }
1314
1315 PPHYSICAL_MEMORY_DESCRIPTOR
1316 NTAPI
1317 MmInitializeMemoryLimits(IN PLOADER_PARAMETER_BLOCK LoaderBlock,
1318 IN PBOOLEAN IncludeType)
1319 {
1320 PLIST_ENTRY NextEntry;
1321 ULONG Run = 0, InitialRuns = 0;
1322 PFN_NUMBER NextPage = -1, PageCount = 0;
1323 PPHYSICAL_MEMORY_DESCRIPTOR Buffer, NewBuffer;
1324 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock;
1325
1326 //
1327 // Scan the memory descriptors
1328 //
1329 NextEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
1330 while (NextEntry != &LoaderBlock->MemoryDescriptorListHead)
1331 {
1332 //
1333 // For each one, increase the memory allocation estimate
1334 //
1335 InitialRuns++;
1336 NextEntry = NextEntry->Flink;
1337 }
1338
1339 //
1340 // Allocate the maximum we'll ever need
1341 //
1342 Buffer = ExAllocatePoolWithTag(NonPagedPool,
1343 sizeof(PHYSICAL_MEMORY_DESCRIPTOR) +
1344 sizeof(PHYSICAL_MEMORY_RUN) *
1345 (InitialRuns - 1),
1346 'lMmM');
1347 if (!Buffer) return NULL;
1348
1349 //
1350 // For now that's how many runs we have
1351 //
1352 Buffer->NumberOfRuns = InitialRuns;
1353
1354 //
1355 // Now loop through the descriptors again
1356 //
1357 NextEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
1358 while (NextEntry != &LoaderBlock->MemoryDescriptorListHead)
1359 {
1360 //
1361 // Grab each one, and check if it's one we should include
1362 //
1363 MdBlock = CONTAINING_RECORD(NextEntry,
1364 MEMORY_ALLOCATION_DESCRIPTOR,
1365 ListEntry);
1366 if ((MdBlock->MemoryType < LoaderMaximum) &&
1367 (IncludeType[MdBlock->MemoryType]))
1368 {
1369 //
1370 // Add this to our running total
1371 //
1372 PageCount += MdBlock->PageCount;
1373
1374 //
1375 // Check if the next page is described by the next descriptor
1376 //
1377 if (MdBlock->BasePage == NextPage)
1378 {
1379 //
1380 // Combine it into the same physical run
1381 //
1382 ASSERT(MdBlock->PageCount != 0);
1383 Buffer->Run[Run - 1].PageCount += MdBlock->PageCount;
1384 NextPage += MdBlock->PageCount;
1385 }
1386 else
1387 {
1388 //
1389 // Otherwise just duplicate the descriptor's contents
1390 //
1391 Buffer->Run[Run].BasePage = MdBlock->BasePage;
1392 Buffer->Run[Run].PageCount = MdBlock->PageCount;
1393 NextPage = Buffer->Run[Run].BasePage + Buffer->Run[Run].PageCount;
1394
1395 //
1396 // And in this case, increase the number of runs
1397 //
1398 Run++;
1399 }
1400 }
1401
1402 //
1403 // Try the next descriptor
1404 //
1405 NextEntry = MdBlock->ListEntry.Flink;
1406 }
1407
1408 //
1409 // We should not have been able to go past our initial estimate
1410 //
1411 ASSERT(Run <= Buffer->NumberOfRuns);
1412
1413 //
1414 // Our guess was probably exaggerated...
1415 //
1416 if (InitialRuns > Run)
1417 {
1418 //
1419 // Allocate a more accurately sized buffer
1420 //
1421 NewBuffer = ExAllocatePoolWithTag(NonPagedPool,
1422 sizeof(PHYSICAL_MEMORY_DESCRIPTOR) +
1423 sizeof(PHYSICAL_MEMORY_RUN) *
1424 (Run - 1),
1425 'lMmM');
1426 if (NewBuffer)
1427 {
1428 //
1429 // Copy the old buffer into the new, then free it
1430 //
1431 RtlCopyMemory(NewBuffer->Run,
1432 Buffer->Run,
1433 sizeof(PHYSICAL_MEMORY_RUN) * Run);
1434 ExFreePool(Buffer);
1435
1436 //
1437 // Now use the new buffer
1438 //
1439 Buffer = NewBuffer;
1440 }
1441 }
1442
1443 //
1444 // Write the final numbers, and return it
1445 //
1446 Buffer->NumberOfRuns = Run;
1447 Buffer->NumberOfPages = PageCount;
1448 return Buffer;
1449 }
1450
1451 VOID
1452 NTAPI
1453 MiBuildPagedPool(VOID)
1454 {
1455 PMMPTE PointerPte, PointerPde;
1456 MMPTE TempPte = ValidKernelPte;
1457 PFN_NUMBER PageFrameIndex;
1458 KIRQL OldIrql;
1459 ULONG Size, BitMapSize;
1460
1461 //
1462 // Get the page frame number for the system page directory
1463 //
1464 PointerPte = MiAddressToPte(PDE_BASE);
1465 ASSERT(PD_COUNT == 1);
1466 MmSystemPageDirectory[0] = PFN_FROM_PTE(PointerPte);
1467
1468 //
1469 // Allocate a system PTE which will hold a copy of the page directory
1470 //
1471 PointerPte = MiReserveSystemPtes(1, SystemPteSpace);
1472 ASSERT(PointerPte);
1473 MmSystemPagePtes = MiPteToAddress(PointerPte);
1474
1475 //
1476 // Make this system PTE point to the system page directory.
1477 // It is now essentially double-mapped. This will be used later for lazy
1478 // evaluation of PDEs accross process switches, similarly to how the Global
1479 // page directory array in the old ReactOS Mm is used (but in a less hacky
1480 // way).
1481 //
1482 TempPte = ValidKernelPte;
1483 ASSERT(PD_COUNT == 1);
1484 TempPte.u.Hard.PageFrameNumber = MmSystemPageDirectory[0];
1485 ASSERT(PointerPte->u.Hard.Valid == 0);
1486 ASSERT(TempPte.u.Hard.Valid == 1);
1487 *PointerPte = TempPte;
1488
1489 //
1490 // Let's get back to paged pool work: size it up.
1491 // By default, it should be twice as big as nonpaged pool.
1492 //
1493 MmSizeOfPagedPoolInBytes = 2 * MmMaximumNonPagedPoolInBytes;
1494 if (MmSizeOfPagedPoolInBytes > ((ULONG_PTR)MmNonPagedSystemStart -
1495 (ULONG_PTR)MmPagedPoolStart))
1496 {
1497 //
1498 // On the other hand, we have limited VA space, so make sure that the VA
1499 // for paged pool doesn't overflow into nonpaged pool VA. Otherwise, set
1500 // whatever maximum is possible.
1501 //
1502 MmSizeOfPagedPoolInBytes = (ULONG_PTR)MmNonPagedSystemStart -
1503 (ULONG_PTR)MmPagedPoolStart;
1504 }
1505
1506 //
1507 // Get the size in pages and make sure paged pool is at least 32MB.
1508 //
1509 Size = MmSizeOfPagedPoolInBytes;
1510 if (Size < MI_MIN_INIT_PAGED_POOLSIZE) Size = MI_MIN_INIT_PAGED_POOLSIZE;
1511 Size = BYTES_TO_PAGES(Size);
1512
1513 //
1514 // Now check how many PTEs will be required for these many pages.
1515 //
1516 Size = (Size + (1024 - 1)) / 1024;
1517
1518 //
1519 // Recompute the page-aligned size of the paged pool, in bytes and pages.
1520 //
1521 MmSizeOfPagedPoolInBytes = Size * PAGE_SIZE * 1024;
1522 MmSizeOfPagedPoolInPages = MmSizeOfPagedPoolInBytes >> PAGE_SHIFT;
1523
1524 //
1525 // Let's be really sure this doesn't overflow into nonpaged system VA
1526 //
1527 ASSERT((MmSizeOfPagedPoolInBytes + (ULONG_PTR)MmPagedPoolStart) <=
1528 (ULONG_PTR)MmNonPagedSystemStart);
1529
1530 //
1531 // This is where paged pool ends
1532 //
1533 MmPagedPoolEnd = (PVOID)(((ULONG_PTR)MmPagedPoolStart +
1534 MmSizeOfPagedPoolInBytes) - 1);
1535
1536 //
1537 // So now get the PDE for paged pool and zero it out
1538 //
1539 PointerPde = MiAddressToPde(MmPagedPoolStart);
1540 RtlZeroMemory(PointerPde,
1541 (1 + MiAddressToPde(MmPagedPoolEnd) - PointerPde) * sizeof(MMPTE));
1542
1543 //
1544 // Next, get the first and last PTE
1545 //
1546 PointerPte = MiAddressToPte(MmPagedPoolStart);
1547 MmPagedPoolInfo.FirstPteForPagedPool = PointerPte;
1548 MmPagedPoolInfo.LastPteForPagedPool = MiAddressToPte(MmPagedPoolEnd);
1549
1550 //
1551 // Lock the PFN database
1552 //
1553 OldIrql = KeAcquireQueuedSpinLock(LockQueuePfnLock);
1554
1555 /* Allocate a page and map the first paged pool PDE */
1556 PageFrameIndex = MiRemoveZeroPage(0);
1557 TempPte.u.Hard.PageFrameNumber = PageFrameIndex;
1558 ASSERT(PointerPde->u.Hard.Valid == 0);
1559 ASSERT(TempPte.u.Hard.Valid == 1);
1560 *PointerPde = TempPte;
1561
1562 /* Initialize the PFN entry for it */
1563 MiInitializePfnForOtherProcess(PageFrameIndex,
1564 PointerPde,
1565 MmSystemPageDirectory[(PointerPde - (PMMPTE)PDE_BASE) / PDE_COUNT]);
1566
1567 //
1568 // Release the PFN database lock
1569 //
1570 KeReleaseQueuedSpinLock(LockQueuePfnLock, OldIrql);
1571
1572 //
1573 // We only have one PDE mapped for now... at fault time, additional PDEs
1574 // will be allocated to handle paged pool growth. This is where they'll have
1575 // to start.
1576 //
1577 MmPagedPoolInfo.NextPdeForPagedPoolExpansion = PointerPde + 1;
1578
1579 //
1580 // We keep track of each page via a bit, so check how big the bitmap will
1581 // have to be (make sure to align our page count such that it fits nicely
1582 // into a 4-byte aligned bitmap.
1583 //
1584 // We'll also allocate the bitmap header itself part of the same buffer.
1585 //
1586 Size = Size * 1024;
1587 ASSERT(Size == MmSizeOfPagedPoolInPages);
1588 BitMapSize = Size;
1589 Size = sizeof(RTL_BITMAP) + (((Size + 31) / 32) * sizeof(ULONG));
1590
1591 //
1592 // Allocate the allocation bitmap, which tells us which regions have not yet
1593 // been mapped into memory
1594 //
1595 MmPagedPoolInfo.PagedPoolAllocationMap = ExAllocatePoolWithTag(NonPagedPool,
1596 Size,
1597 ' mM');
1598 ASSERT(MmPagedPoolInfo.PagedPoolAllocationMap);
1599
1600 //
1601 // Initialize it such that at first, only the first page's worth of PTEs is
1602 // marked as allocated (incidentially, the first PDE we allocated earlier).
1603 //
1604 RtlInitializeBitMap(MmPagedPoolInfo.PagedPoolAllocationMap,
1605 (PULONG)(MmPagedPoolInfo.PagedPoolAllocationMap + 1),
1606 BitMapSize);
1607 RtlSetAllBits(MmPagedPoolInfo.PagedPoolAllocationMap);
1608 RtlClearBits(MmPagedPoolInfo.PagedPoolAllocationMap, 0, 1024);
1609
1610 //
1611 // We have a second bitmap, which keeps track of where allocations end.
1612 // Given the allocation bitmap and a base address, we can therefore figure
1613 // out which page is the last page of that allocation, and thus how big the
1614 // entire allocation is.
1615 //
1616 MmPagedPoolInfo.EndOfPagedPoolBitmap = ExAllocatePoolWithTag(NonPagedPool,
1617 Size,
1618 ' mM');
1619 ASSERT(MmPagedPoolInfo.EndOfPagedPoolBitmap);
1620 RtlInitializeBitMap(MmPagedPoolInfo.EndOfPagedPoolBitmap,
1621 (PULONG)(MmPagedPoolInfo.EndOfPagedPoolBitmap + 1),
1622 BitMapSize);
1623
1624 //
1625 // Since no allocations have been made yet, there are no bits set as the end
1626 //
1627 RtlClearAllBits(MmPagedPoolInfo.EndOfPagedPoolBitmap);
1628
1629 //
1630 // Initialize paged pool.
1631 //
1632 InitializePool(PagedPool, 0);
1633
1634 /* Default low threshold of 30MB or one fifth of paged pool */
1635 MiLowPagedPoolThreshold = (30 * _1MB) >> PAGE_SHIFT;
1636 MiLowPagedPoolThreshold = min(MiLowPagedPoolThreshold, Size / 5);
1637
1638 /* Default high threshold of 60MB or 25% */
1639 MiHighPagedPoolThreshold = (60 * _1MB) >> PAGE_SHIFT;
1640 MiHighPagedPoolThreshold = min(MiHighPagedPoolThreshold, (Size * 2) / 5);
1641 ASSERT(MiLowPagedPoolThreshold < MiHighPagedPoolThreshold);
1642 }
1643
1644 NTSTATUS
1645 NTAPI
1646 MmArmInitSystem(IN ULONG Phase,
1647 IN PLOADER_PARAMETER_BLOCK LoaderBlock)
1648 {
1649 ULONG i;
1650 BOOLEAN IncludeType[LoaderMaximum];
1651 PVOID Bitmap;
1652 PPHYSICAL_MEMORY_RUN Run;
1653 PFN_NUMBER PageCount;
1654
1655 //
1656 // Instantiate memory that we don't consider RAM/usable
1657 // We use the same exclusions that Windows does, in order to try to be
1658 // compatible with WinLDR-style booting
1659 //
1660 for (i = 0; i < LoaderMaximum; i++) IncludeType[i] = TRUE;
1661 IncludeType[LoaderBad] = FALSE;
1662 IncludeType[LoaderFirmwarePermanent] = FALSE;
1663 IncludeType[LoaderSpecialMemory] = FALSE;
1664 IncludeType[LoaderBBTMemory] = FALSE;
1665 if (Phase == 0)
1666 {
1667 /* Initialize the phase 0 temporary event */
1668 KeInitializeEvent(&MiTempEvent, NotificationEvent, FALSE);
1669
1670 /* Set all the events to use the temporary event for now */
1671 MiLowMemoryEvent = &MiTempEvent;
1672 MiHighMemoryEvent = &MiTempEvent;
1673 MiLowPagedPoolEvent = &MiTempEvent;
1674 MiHighPagedPoolEvent = &MiTempEvent;
1675 MiLowNonPagedPoolEvent = &MiTempEvent;
1676 MiHighNonPagedPoolEvent = &MiTempEvent;
1677
1678 //
1679 // Define the basic user vs. kernel address space separation
1680 //
1681 MmSystemRangeStart = (PVOID)KSEG0_BASE;
1682 MmUserProbeAddress = (ULONG_PTR)MmSystemRangeStart - 0x10000;
1683 MmHighestUserAddress = (PVOID)(MmUserProbeAddress - 1);
1684
1685 /* Highest PTE and PDE based on the addresses above */
1686 MiHighestUserPte = MiAddressToPte(MmHighestUserAddress);
1687 MiHighestUserPde = MiAddressToPde(MmHighestUserAddress);
1688
1689 //
1690 // Get the size of the boot loader's image allocations and then round
1691 // that region up to a PDE size, so that any PDEs we might create for
1692 // whatever follows are separate from the PDEs that boot loader might've
1693 // already created (and later, we can blow all that away if we want to).
1694 //
1695 MmBootImageSize = KeLoaderBlock->Extension->LoaderPagesSpanned;
1696 MmBootImageSize *= PAGE_SIZE;
1697 MmBootImageSize = (MmBootImageSize + PDE_MAPPED_VA - 1) & ~(PDE_MAPPED_VA - 1);
1698 ASSERT((MmBootImageSize % PDE_MAPPED_VA) == 0);
1699
1700 //
1701 // Set the size of session view, pool, and image
1702 //
1703 MmSessionSize = MI_SESSION_SIZE;
1704 MmSessionViewSize = MI_SESSION_VIEW_SIZE;
1705 MmSessionPoolSize = MI_SESSION_POOL_SIZE;
1706 MmSessionImageSize = MI_SESSION_IMAGE_SIZE;
1707
1708 //
1709 // Set the size of system view
1710 //
1711 MmSystemViewSize = MI_SYSTEM_VIEW_SIZE;
1712
1713 //
1714 // This is where it all ends
1715 //
1716 MiSessionImageEnd = (PVOID)PTE_BASE;
1717
1718 //
1719 // This is where we will load Win32k.sys and the video driver
1720 //
1721 MiSessionImageStart = (PVOID)((ULONG_PTR)MiSessionImageEnd -
1722 MmSessionImageSize);
1723
1724 //
1725 // So the view starts right below the session working set (itself below
1726 // the image area)
1727 //
1728 MiSessionViewStart = (PVOID)((ULONG_PTR)MiSessionImageEnd -
1729 MmSessionImageSize -
1730 MI_SESSION_WORKING_SET_SIZE -
1731 MmSessionViewSize);
1732
1733 //
1734 // Session pool follows
1735 //
1736 MiSessionPoolEnd = MiSessionViewStart;
1737 MiSessionPoolStart = (PVOID)((ULONG_PTR)MiSessionPoolEnd -
1738 MmSessionPoolSize);
1739
1740 //
1741 // And it all begins here
1742 //
1743 MmSessionBase = MiSessionPoolStart;
1744
1745 //
1746 // Sanity check that our math is correct
1747 //
1748 ASSERT((ULONG_PTR)MmSessionBase + MmSessionSize == PTE_BASE);
1749
1750 //
1751 // Session space ends wherever image session space ends
1752 //
1753 MiSessionSpaceEnd = MiSessionImageEnd;
1754
1755 //
1756 // System view space ends at session space, so now that we know where
1757 // this is, we can compute the base address of system view space itself.
1758 //
1759 MiSystemViewStart = (PVOID)((ULONG_PTR)MmSessionBase -
1760 MmSystemViewSize);
1761
1762 /* Compute the PTE addresses for all the addresses we carved out */
1763 MiSessionImagePteStart = MiAddressToPte(MiSessionImageStart);
1764 MiSessionImagePteEnd = MiAddressToPte(MiSessionImageEnd);
1765 MiSessionBasePte = MiAddressToPte(MmSessionBase);
1766 MiSessionLastPte = MiAddressToPte(MiSessionSpaceEnd);
1767
1768 /* Initialize the user mode image list */
1769 InitializeListHead(&MmLoadedUserImageList);
1770
1771 /* Initialize the paged pool mutex */
1772 KeInitializeGuardedMutex(&MmPagedPoolMutex);
1773
1774 /* Initialize the Loader Lock */
1775 KeInitializeMutant(&MmSystemLoadLock, FALSE);
1776
1777 //
1778 // Count physical pages on the system
1779 //
1780 PageCount = MiPagesInLoaderBlock(LoaderBlock, IncludeType);
1781
1782 //
1783 // Check if this is a machine with less than 19MB of RAM
1784 //
1785 if (PageCount < MI_MIN_PAGES_FOR_SYSPTE_TUNING)
1786 {
1787 //
1788 // Use the very minimum of system PTEs
1789 //
1790 MmNumberOfSystemPtes = 7000;
1791 }
1792 else
1793 {
1794 //
1795 // Use the default, but check if we have more than 32MB of RAM
1796 //
1797 MmNumberOfSystemPtes = 11000;
1798 if (PageCount > MI_MIN_PAGES_FOR_SYSPTE_BOOST)
1799 {
1800 //
1801 // Double the amount of system PTEs
1802 //
1803 MmNumberOfSystemPtes <<= 1;
1804 }
1805 }
1806
1807 DPRINT("System PTE count has been tuned to %d (%d bytes)\n",
1808 MmNumberOfSystemPtes, MmNumberOfSystemPtes * PAGE_SIZE);
1809
1810 /* Initialize the platform-specific parts */
1811 MiInitMachineDependent(LoaderBlock);
1812
1813 //
1814 // Sync us up with ReactOS Mm
1815 //
1816 MiSyncARM3WithROS(MmNonPagedSystemStart, (PVOID)((ULONG_PTR)MmNonPagedPoolEnd - 1));
1817 MiSyncARM3WithROS(MmPfnDatabase, (PVOID)((ULONG_PTR)MmNonPagedPoolStart + MmSizeOfNonPagedPoolInBytes - 1));
1818 MiSyncARM3WithROS((PVOID)HYPER_SPACE, (PVOID)(HYPER_SPACE + PAGE_SIZE - 1));
1819
1820 //
1821 // Build the physical memory block
1822 //
1823 MmPhysicalMemoryBlock = MmInitializeMemoryLimits(LoaderBlock,
1824 IncludeType);
1825
1826 //
1827 // Allocate enough buffer for the PFN bitmap
1828 // Align it up to a 32-bit boundary
1829 //
1830 Bitmap = ExAllocatePoolWithTag(NonPagedPool,
1831 (((MmHighestPhysicalPage + 1) + 31) / 32) * 4,
1832 ' mM');
1833 if (!Bitmap)
1834 {
1835 //
1836 // This is critical
1837 //
1838 KeBugCheckEx(INSTALL_MORE_MEMORY,
1839 MmNumberOfPhysicalPages,
1840 MmLowestPhysicalPage,
1841 MmHighestPhysicalPage,
1842 0x101);
1843 }
1844
1845 //
1846 // Initialize it and clear all the bits to begin with
1847 //
1848 RtlInitializeBitMap(&MiPfnBitMap,
1849 Bitmap,
1850 MmHighestPhysicalPage + 1);
1851 RtlClearAllBits(&MiPfnBitMap);
1852
1853 //
1854 // Loop physical memory runs
1855 //
1856 for (i = 0; i < MmPhysicalMemoryBlock->NumberOfRuns; i++)
1857 {
1858 //
1859 // Get the run
1860 //
1861 Run = &MmPhysicalMemoryBlock->Run[i];
1862 DPRINT("PHYSICAL RAM [0x%08p to 0x%08p]\n",
1863 Run->BasePage << PAGE_SHIFT,
1864 (Run->BasePage + Run->PageCount) << PAGE_SHIFT);
1865
1866 //
1867 // Make sure it has pages inside it
1868 //
1869 if (Run->PageCount)
1870 {
1871 //
1872 // Set the bits in the PFN bitmap
1873 //
1874 RtlSetBits(&MiPfnBitMap, Run->BasePage, Run->PageCount);
1875 }
1876 }
1877
1878 /* Look for large page cache entries that need caching */
1879 MiSyncCachedRanges();
1880
1881 /* Loop for HAL Heap I/O device mappings that need coherency tracking */
1882 MiAddHalIoMappings();
1883
1884 /* Set the initial resident page count */
1885 MmResidentAvailablePages = MmAvailablePages - 32;
1886
1887 /* Initialize large page structures on PAE/x64, and MmProcessList on x86 */
1888 MiInitializeLargePageSupport();
1889
1890 /* Check if the registry says any drivers should be loaded with large pages */
1891 MiInitializeDriverLargePageList();
1892
1893 /* Relocate the boot drivers into system PTE space and fixup their PFNs */
1894 MiReloadBootLoadedDrivers(LoaderBlock);
1895
1896 /* FIXME: Call out into Driver Verifier for initialization */
1897
1898 /* Check how many pages the system has */
1899 if (MmNumberOfPhysicalPages <= (13 * _1MB))
1900 {
1901 /* Set small system */
1902 MmSystemSize = MmSmallSystem;
1903 }
1904 else if (MmNumberOfPhysicalPages <= (19 * _1MB))
1905 {
1906 /* Set small system and add 100 pages for the cache */
1907 MmSystemSize = MmSmallSystem;
1908 MmSystemCacheWsMinimum += 100;
1909 }
1910 else
1911 {
1912 /* Set medium system and add 400 pages for the cache */
1913 MmSystemSize = MmMediumSystem;
1914 MmSystemCacheWsMinimum += 400;
1915 }
1916
1917 /* Check for less than 24MB */
1918 if (MmNumberOfPhysicalPages < ((24 * _1MB) / PAGE_SIZE))
1919 {
1920 /* No more than 32 pages */
1921 MmSystemCacheWsMinimum = 32;
1922 }
1923
1924 /* Check for more than 32MB */
1925 if (MmNumberOfPhysicalPages >= ((32 * _1MB) / PAGE_SIZE))
1926 {
1927 /* Check for product type being "Wi" for WinNT */
1928 if (MmProductType == '\0i\0W')
1929 {
1930 /* Then this is a large system */
1931 MmSystemSize = MmLargeSystem;
1932 }
1933 else
1934 {
1935 /* For servers, we need 64MB to consider this as being large */
1936 if (MmNumberOfPhysicalPages >= ((64 * _1MB) / PAGE_SIZE))
1937 {
1938 /* Set it as large */
1939 MmSystemSize = MmLargeSystem;
1940 }
1941 }
1942 }
1943
1944 /* Check for more than 33 MB */
1945 if (MmNumberOfPhysicalPages > ((33 * _1MB) / PAGE_SIZE))
1946 {
1947 /* Add another 500 pages to the cache */
1948 MmSystemCacheWsMinimum += 500;
1949 }
1950
1951 /* Now setup the shared user data fields */
1952 ASSERT(SharedUserData->NumberOfPhysicalPages == 0);
1953 SharedUserData->NumberOfPhysicalPages = MmNumberOfPhysicalPages;
1954 SharedUserData->LargePageMinimum = 0;
1955
1956 /* Check for workstation (Wi for WinNT) */
1957 if (MmProductType == '\0i\0W')
1958 {
1959 /* Set Windows NT Workstation product type */
1960 SharedUserData->NtProductType = NtProductWinNt;
1961 MmProductType = 0;
1962 }
1963 else
1964 {
1965 /* Check for LanMan server */
1966 if (MmProductType == '\0a\0L')
1967 {
1968 /* This is a domain controller */
1969 SharedUserData->NtProductType = NtProductLanManNt;
1970 }
1971 else
1972 {
1973 /* Otherwise it must be a normal server */
1974 SharedUserData->NtProductType = NtProductServer;
1975 }
1976
1977 /* Set the product type, and make the system more aggressive with low memory */
1978 MmProductType = 1;
1979 MmMinimumFreePages = 81;
1980 }
1981
1982 /* Update working set tuning parameters */
1983 MiAdjustWorkingSetManagerParameters(!MmProductType);
1984
1985 /* Finetune the page count by removing working set and NP expansion */
1986 MmResidentAvailablePages -= MiExpansionPoolPagesInitialCharge;
1987 MmResidentAvailablePages -= MmSystemCacheWsMinimum;
1988 MmResidentAvailableAtInit = MmResidentAvailablePages;
1989 if (MmResidentAvailablePages <= 0)
1990 {
1991 /* This should not happen */
1992 DPRINT1("System cache working set too big\n");
1993 return FALSE;
1994 }
1995
1996 /* Size up paged pool and build the shadow system page directory */
1997 MiBuildPagedPool();
1998
1999 /* Debugger physical memory support is now ready to be used */
2000 MiDbgReadyForPhysical = TRUE;
2001
2002 /* Initialize the loaded module list */
2003 MiInitializeLoadedModuleList(LoaderBlock);
2004 }
2005
2006 //
2007 // Always return success for now
2008 //
2009 return STATUS_SUCCESS;
2010 }
2011
2012 /* EOF */
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