2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/mminit.c
5 * PURPOSE: ARM Memory Manager Initialization
6 * PROGRAMMERS: ReactOS Portable Systems Group
9 /* INCLUDES *******************************************************************/
16 #define MODULE_INVOLVED_IN_ARM3
19 /* GLOBALS ********************************************************************/
22 // These are all registry-configurable, but by default, the memory manager will
23 // figure out the most appropriate values.
25 ULONG MmMaximumNonPagedPoolPercent
;
26 ULONG MmSizeOfNonPagedPoolInBytes
;
27 ULONG MmMaximumNonPagedPoolInBytes
;
29 /* Some of the same values, in pages */
30 PFN_NUMBER MmMaximumNonPagedPoolInPages
;
33 // These numbers describe the discrete equation components of the nonpaged
34 // pool sizing algorithm.
36 // They are described on http://support.microsoft.com/default.aspx/kb/126402/ja
37 // along with the algorithm that uses them, which is implemented later below.
39 ULONG MmMinimumNonPagedPoolSize
= 256 * 1024;
40 ULONG MmMinAdditionNonPagedPoolPerMb
= 32 * 1024;
41 ULONG MmDefaultMaximumNonPagedPool
= 1024 * 1024;
42 ULONG MmMaxAdditionNonPagedPoolPerMb
= 400 * 1024;
45 // The memory layout (and especially variable names) of the NT kernel mode
46 // components can be a bit hard to twig, especially when it comes to the non
49 // There are really two components to the non-paged pool:
51 // - The initial nonpaged pool, sized dynamically up to a maximum.
52 // - The expansion nonpaged pool, sized dynamically up to a maximum.
54 // The initial nonpaged pool is physically continuous for performance, and
55 // immediately follows the PFN database, typically sharing the same PDE. It is
56 // a very small resource (32MB on a 1GB system), and capped at 128MB.
58 // Right now we call this the "ARM³ Nonpaged Pool" and it begins somewhere after
59 // the PFN database (which starts at 0xB0000000).
61 // The expansion nonpaged pool, on the other hand, can grow much bigger (400MB
62 // for a 1GB system). On ARM³ however, it is currently capped at 128MB.
64 // The address where the initial nonpaged pool starts is aptly named
65 // MmNonPagedPoolStart, and it describes a range of MmSizeOfNonPagedPoolInBytes
68 // Expansion nonpaged pool starts at an address described by the variable called
69 // MmNonPagedPoolExpansionStart, and it goes on for MmMaximumNonPagedPoolInBytes
70 // minus MmSizeOfNonPagedPoolInBytes bytes, always reaching MmNonPagedPoolEnd
71 // (because of the way it's calculated) at 0xFFBE0000.
73 // Initial nonpaged pool is allocated and mapped early-on during boot, but what
74 // about the expansion nonpaged pool? It is instead composed of special pages
75 // which belong to what are called System PTEs. These PTEs are the matter of a
76 // later discussion, but they are also considered part of the "nonpaged" OS, due
77 // to the fact that they are never paged out -- once an address is described by
78 // a System PTE, it is always valid, until the System PTE is torn down.
80 // System PTEs are actually composed of two "spaces", the system space proper,
81 // and the nonpaged pool expansion space. The latter, as we've already seen,
82 // begins at MmNonPagedPoolExpansionStart. Based on the number of System PTEs
83 // that the system will support, the remaining address space below this address
84 // is used to hold the system space PTEs. This address, in turn, is held in the
85 // variable named MmNonPagedSystemStart, which itself is never allowed to go
86 // below 0xEB000000 (thus creating an upper bound on the number of System PTEs).
88 // This means that 330MB are reserved for total nonpaged system VA, on top of
89 // whatever the initial nonpaged pool allocation is.
91 // The following URLs, valid as of April 23rd, 2008, support this evidence:
93 // http://www.cs.miami.edu/~burt/journal/NT/memory.html
94 // http://www.ditii.com/2007/09/28/windows-memory-management-x86-virtual-address-space/
96 PVOID MmNonPagedSystemStart
;
97 PVOID MmNonPagedPoolStart
;
98 PVOID MmNonPagedPoolExpansionStart
;
99 PVOID MmNonPagedPoolEnd
= MI_NONPAGED_POOL_END
;
102 // This is where paged pool starts by default
104 PVOID MmPagedPoolStart
= MI_PAGED_POOL_START
;
105 PVOID MmPagedPoolEnd
;
108 // And this is its default size
110 ULONG MmSizeOfPagedPoolInBytes
= MI_MIN_INIT_PAGED_POOLSIZE
;
111 PFN_NUMBER MmSizeOfPagedPoolInPages
= MI_MIN_INIT_PAGED_POOLSIZE
/ PAGE_SIZE
;
114 // Session space starts at 0xBFFFFFFF and grows downwards
115 // By default, it includes an 8MB image area where we map win32k and video card
116 // drivers, followed by a 4MB area containing the session's working set. This is
117 // then followed by a 20MB mapped view area and finally by the session's paged
118 // pool, by default 16MB.
120 // On a normal system, this results in session space occupying the region from
121 // 0xBD000000 to 0xC0000000
123 // See miarm.h for the defines that determine the sizing of this region. On an
124 // NT system, some of these can be configured through the registry, but we don't
127 PVOID MiSessionSpaceEnd
; // 0xC0000000
128 PVOID MiSessionImageEnd
; // 0xC0000000
129 PVOID MiSessionImageStart
; // 0xBF800000
130 PVOID MiSessionViewStart
; // 0xBE000000
131 PVOID MiSessionPoolEnd
; // 0xBE000000
132 PVOID MiSessionPoolStart
; // 0xBD000000
133 PVOID MmSessionBase
; // 0xBD000000
135 ULONG MmSessionViewSize
;
136 ULONG MmSessionPoolSize
;
137 ULONG MmSessionImageSize
;
140 * These are the PTE addresses of the boundaries carved out above
142 PMMPTE MiSessionImagePteStart
;
143 PMMPTE MiSessionImagePteEnd
;
144 PMMPTE MiSessionBasePte
;
145 PMMPTE MiSessionLastPte
;
148 // The system view space, on the other hand, is where sections that are memory
149 // mapped into "system space" end up.
151 // By default, it is a 16MB region.
153 PVOID MiSystemViewStart
;
154 ULONG MmSystemViewSize
;
157 // A copy of the system page directory (the page directory associated with the
158 // System process) is kept (double-mapped) by the manager in order to lazily
159 // map paged pool PDEs into external processes when they fault on a paged pool
162 PFN_NUMBER MmSystemPageDirectory
[PD_COUNT
];
163 PMMPTE MmSystemPagePtes
;
166 // The system cache starts right after hyperspace. The first few pages are for
167 // keeping track of the system working set list.
169 // This should be 0xC0C00000 -- the cache itself starts at 0xC1000000
171 PMMWSL MmSystemCacheWorkingSetList
= MI_SYSTEM_CACHE_WS_START
;
174 // Windows NT seems to choose between 7000, 11000 and 50000
175 // On systems with more than 32MB, this number is then doubled, and further
176 // aligned up to a PDE boundary (4MB).
178 ULONG MmNumberOfSystemPtes
;
181 // This is how many pages the PFN database will take up
182 // In Windows, this includes the Quark Color Table, but not in ARM³
184 ULONG MxPfnAllocation
;
187 // Unlike the old ReactOS Memory Manager, ARM³ (and Windows) does not keep track
188 // of pages that are not actually valid physical memory, such as ACPI reserved
189 // regions, BIOS address ranges, or holes in physical memory address space which
190 // could indicate device-mapped I/O memory.
192 // In fact, the lack of a PFN entry for a page usually indicates that this is
193 // I/O space instead.
195 // A bitmap, called the PFN bitmap, keeps track of all page frames by assigning
196 // a bit to each. If the bit is set, then the page is valid physical RAM.
198 RTL_BITMAP MiPfnBitMap
;
201 // This structure describes the different pieces of RAM-backed address space
203 PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock
;
206 // This is where we keep track of the most basic physical layout markers
208 ULONG MmNumberOfPhysicalPages
, MmHighestPhysicalPage
, MmLowestPhysicalPage
= -1;
211 // The total number of pages mapped by the boot loader, which include the kernel
212 // HAL, boot drivers, registry, NLS files and other loader data structures is
213 // kept track of here. This depends on "LoaderPagesSpanned" being correct when
214 // coming from the loader.
216 // This number is later aligned up to a PDE boundary.
218 ULONG MmBootImageSize
;
221 // These three variables keep track of the core separation of address space that
222 // exists between kernel mode and user mode.
224 ULONG MmUserProbeAddress
;
225 PVOID MmHighestUserAddress
;
226 PVOID MmSystemRangeStart
;
228 /* And these store the respective highest PTE/PDE address */
229 PMMPTE MiHighestUserPte
;
230 PMMPDE MiHighestUserPde
;
232 /* These variables define the system cache address space */
233 PVOID MmSystemCacheStart
;
234 PVOID MmSystemCacheEnd
;
235 MMSUPPORT MmSystemCacheWs
;
238 // This is where hyperspace ends (followed by the system cache working set)
240 PVOID MmHyperSpaceEnd
;
243 // Page coloring algorithm data
245 ULONG MmSecondaryColors
;
246 ULONG MmSecondaryColorMask
;
249 // Actual (registry-configurable) size of a GUI thread's stack
251 ULONG MmLargeStackSize
= KERNEL_LARGE_STACK_SIZE
;
254 // Before we have a PFN database, memory comes straight from our physical memory
255 // blocks, which is nice because it's guaranteed contiguous and also because once
256 // we take a page from here, the system doesn't see it anymore.
257 // However, once the fun is over, those pages must be re-integrated back into
258 // PFN society life, and that requires us keeping a copy of the original layout
259 // so that we can parse it later.
261 PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor
;
262 MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor
;
265 * For each page's worth bytes of L2 cache in a given set/way line, the zero and
266 * free lists are organized in what is called a "color".
268 * This array points to the two lists, so it can be thought of as a multi-dimensional
269 * array of MmFreePagesByColor[2][MmSecondaryColors]. Since the number is dynamic,
270 * we describe the array in pointer form instead.
272 * On a final note, the color tables themselves are right after the PFN database.
274 C_ASSERT(FreePageList
== 1);
275 PMMCOLOR_TABLES MmFreePagesByColor
[FreePageList
+ 1];
277 /* An event used in Phase 0 before the rest of the system is ready to go */
280 /* All the events used for memory threshold notifications */
281 PKEVENT MiLowMemoryEvent
;
282 PKEVENT MiHighMemoryEvent
;
283 PKEVENT MiLowPagedPoolEvent
;
284 PKEVENT MiHighPagedPoolEvent
;
285 PKEVENT MiLowNonPagedPoolEvent
;
286 PKEVENT MiHighNonPagedPoolEvent
;
288 /* The actual thresholds themselves, in page numbers */
289 PFN_NUMBER MmLowMemoryThreshold
;
290 PFN_NUMBER MmHighMemoryThreshold
;
291 PFN_NUMBER MiLowPagedPoolThreshold
;
292 PFN_NUMBER MiHighPagedPoolThreshold
;
293 PFN_NUMBER MiLowNonPagedPoolThreshold
;
294 PFN_NUMBER MiHighNonPagedPoolThreshold
;
297 * This number determines how many free pages must exist, at minimum, until we
298 * start trimming working sets and flushing modified pages to obtain more free
301 * This number changes if the system detects that this is a server product
303 PFN_NUMBER MmMinimumFreePages
= 26;
306 * This number indicates how many pages we consider to be a low limit of having
307 * "plenty" of free memory.
309 * It is doubled on systems that have more than 63MB of memory
311 PFN_NUMBER MmPlentyFreePages
= 400;
313 /* These values store the type of system this is (small, med, large) and if server */
315 MM_SYSTEMSIZE MmSystemSize
;
318 * These values store the cache working set minimums and maximums, in pages
320 * The minimum value is boosted on systems with more than 24MB of RAM, and cut
321 * down to only 32 pages on embedded (<24MB RAM) systems.
323 * An extra boost of 2MB is given on systems with more than 33MB of RAM.
325 PFN_NUMBER MmSystemCacheWsMinimum
= 288;
326 PFN_NUMBER MmSystemCacheWsMaximum
= 350;
328 /* FIXME: Move to cache/working set code later */
329 BOOLEAN MmLargeSystemCache
;
331 /* PRIVATE FUNCTIONS **********************************************************/
334 // In Bavaria, this is probably a hate crime
338 MiSyncARM3WithROS(IN PVOID AddressStart
,
342 // Puerile piece of junk-grade carbonized horseshit puss sold to the lowest bidder
344 ULONG Pde
= ADDR_TO_PDE_OFFSET(AddressStart
);
345 while (Pde
<= ADDR_TO_PDE_OFFSET(AddressEnd
))
348 // This both odious and heinous
350 extern ULONG MmGlobalKernelPageDirectory
[1024];
351 MmGlobalKernelPageDirectory
[Pde
] = ((PULONG
)PDE_BASE
)[Pde
];
358 MxGetNextPage(IN PFN_NUMBER PageCount
)
362 /* Make sure we have enough pages */
363 if (PageCount
> MxFreeDescriptor
->PageCount
)
365 /* Crash the system */
366 KeBugCheckEx(INSTALL_MORE_MEMORY
,
367 MmNumberOfPhysicalPages
,
368 MxFreeDescriptor
->PageCount
,
369 MxOldFreeDescriptor
.PageCount
,
373 /* Use our lowest usable free pages */
374 Pfn
= MxFreeDescriptor
->BasePage
;
375 MxFreeDescriptor
->BasePage
+= PageCount
;
376 MxFreeDescriptor
->PageCount
-= PageCount
;
382 MiComputeColorInformation(VOID
)
384 ULONG L2Associativity
;
386 /* Check if no setting was provided already */
387 if (!MmSecondaryColors
)
389 /* Get L2 cache information */
390 L2Associativity
= KeGetPcr()->SecondLevelCacheAssociativity
;
392 /* The number of colors is the number of cache bytes by set/way */
393 MmSecondaryColors
= KeGetPcr()->SecondLevelCacheSize
;
394 if (L2Associativity
) MmSecondaryColors
/= L2Associativity
;
397 /* Now convert cache bytes into pages */
398 MmSecondaryColors
>>= PAGE_SHIFT
;
399 if (!MmSecondaryColors
)
401 /* If there was no cache data from the KPCR, use the default colors */
402 MmSecondaryColors
= MI_SECONDARY_COLORS
;
406 /* Otherwise, make sure there aren't too many colors */
407 if (MmSecondaryColors
> MI_MAX_SECONDARY_COLORS
)
409 /* Set the maximum */
410 MmSecondaryColors
= MI_MAX_SECONDARY_COLORS
;
413 /* Make sure there aren't too little colors */
414 if (MmSecondaryColors
< MI_MIN_SECONDARY_COLORS
)
416 /* Set the default */
417 MmSecondaryColors
= MI_SECONDARY_COLORS
;
420 /* Finally make sure the colors are a power of two */
421 if (MmSecondaryColors
& (MmSecondaryColors
- 1))
423 /* Set the default */
424 MmSecondaryColors
= MI_SECONDARY_COLORS
;
428 /* Compute the mask and store it */
429 MmSecondaryColorMask
= MmSecondaryColors
- 1;
430 KeGetCurrentPrcb()->SecondaryColorMask
= MmSecondaryColorMask
;
435 MiInitializeColorTables(VOID
)
438 PMMPTE PointerPte
, LastPte
;
439 MMPTE TempPte
= ValidKernelPte
;
441 /* The color table starts after the ARM3 PFN database */
442 MmFreePagesByColor
[0] = (PMMCOLOR_TABLES
)&MmPfnDatabase
[MmHighestPhysicalPage
+ 1];
444 /* Loop the PTEs. We have two color tables for each secondary color */
445 PointerPte
= MiAddressToPte(&MmFreePagesByColor
[0][0]);
446 LastPte
= MiAddressToPte((ULONG_PTR
)MmFreePagesByColor
[0] +
447 (2 * MmSecondaryColors
* sizeof(MMCOLOR_TABLES
))
449 while (PointerPte
<= LastPte
)
451 /* Check for valid PTE */
452 if (PointerPte
->u
.Hard
.Valid
== 0)
454 /* Get a page and map it */
455 TempPte
.u
.Hard
.PageFrameNumber
= MxGetNextPage(1);
456 ASSERT(TempPte
.u
.Hard
.Valid
== 1);
457 *PointerPte
= TempPte
;
459 /* Zero out the page */
460 RtlZeroMemory(MiPteToAddress(PointerPte
), PAGE_SIZE
);
467 /* Now set the address of the next list, right after this one */
468 MmFreePagesByColor
[1] = &MmFreePagesByColor
[0][MmSecondaryColors
];
470 /* Now loop the lists to set them up */
471 for (i
= 0; i
< MmSecondaryColors
; i
++)
473 /* Set both free and zero lists for each color */
474 MmFreePagesByColor
[ZeroedPageList
][i
].Flink
= 0xFFFFFFFF;
475 MmFreePagesByColor
[ZeroedPageList
][i
].Blink
= (PVOID
)0xFFFFFFFF;
476 MmFreePagesByColor
[ZeroedPageList
][i
].Count
= 0;
477 MmFreePagesByColor
[FreePageList
][i
].Flink
= 0xFFFFFFFF;
478 MmFreePagesByColor
[FreePageList
][i
].Blink
= (PVOID
)0xFFFFFFFF;
479 MmFreePagesByColor
[FreePageList
][i
].Count
= 0;
485 MiIsRegularMemory(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
488 PLIST_ENTRY NextEntry
;
489 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
491 /* Loop the memory descriptors */
492 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
493 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
495 /* Get the memory descriptor */
496 MdBlock
= CONTAINING_RECORD(NextEntry
,
497 MEMORY_ALLOCATION_DESCRIPTOR
,
500 /* Check if this PFN could be part of the block */
501 if (Pfn
>= (MdBlock
->BasePage
))
503 /* Check if it really is part of the block */
504 if (Pfn
< (MdBlock
->BasePage
+ MdBlock
->PageCount
))
506 /* Check if the block is actually memory we don't map */
507 if ((MdBlock
->MemoryType
== LoaderFirmwarePermanent
) ||
508 (MdBlock
->MemoryType
== LoaderBBTMemory
) ||
509 (MdBlock
->MemoryType
== LoaderSpecialMemory
))
511 /* We don't need PFN database entries for this memory */
515 /* This is memory we want to map */
521 /* Blocks are ordered, so if it's not here, it doesn't exist */
525 /* Get to the next descriptor */
526 NextEntry
= MdBlock
->ListEntry
.Flink
;
529 /* Check if this PFN is actually from our free memory descriptor */
530 if ((Pfn
>= MxOldFreeDescriptor
.BasePage
) &&
531 (Pfn
< MxOldFreeDescriptor
.BasePage
+ MxOldFreeDescriptor
.PageCount
))
533 /* We use these pages for initial mappings, so we do want to count them */
537 /* Otherwise this isn't memory that we describe or care about */
543 MiMapPfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
545 ULONG FreePage
, FreePageCount
, PagesLeft
, BasePage
, PageCount
;
546 PLIST_ENTRY NextEntry
;
547 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
548 PMMPTE PointerPte
, LastPte
;
549 MMPTE TempPte
= ValidKernelPte
;
551 /* Get current page data, since we won't be using MxGetNextPage as it would corrupt our state */
552 FreePage
= MxFreeDescriptor
->BasePage
;
553 FreePageCount
= MxFreeDescriptor
->PageCount
;
556 /* Loop the memory descriptors */
557 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
558 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
560 /* Get the descriptor */
561 MdBlock
= CONTAINING_RECORD(NextEntry
,
562 MEMORY_ALLOCATION_DESCRIPTOR
,
564 if ((MdBlock
->MemoryType
== LoaderFirmwarePermanent
) ||
565 (MdBlock
->MemoryType
== LoaderBBTMemory
) ||
566 (MdBlock
->MemoryType
== LoaderSpecialMemory
))
568 /* These pages are not part of the PFN database */
569 NextEntry
= MdBlock
->ListEntry
.Flink
;
573 /* Next, check if this is our special free descriptor we've found */
574 if (MdBlock
== MxFreeDescriptor
)
576 /* Use the real numbers instead */
577 BasePage
= MxOldFreeDescriptor
.BasePage
;
578 PageCount
= MxOldFreeDescriptor
.PageCount
;
582 /* Use the descriptor's numbers */
583 BasePage
= MdBlock
->BasePage
;
584 PageCount
= MdBlock
->PageCount
;
587 /* Get the PTEs for this range */
588 PointerPte
= MiAddressToPte(&MmPfnDatabase
[BasePage
]);
589 LastPte
= MiAddressToPte(((ULONG_PTR
)&MmPfnDatabase
[BasePage
+ PageCount
]) - 1);
590 DPRINT("MD Type: %lx Base: %lx Count: %lx\n", MdBlock
->MemoryType
, BasePage
, PageCount
);
593 while (PointerPte
<= LastPte
)
595 /* We'll only touch PTEs that aren't already valid */
596 if (PointerPte
->u
.Hard
.Valid
== 0)
598 /* Use the next free page */
599 TempPte
.u
.Hard
.PageFrameNumber
= FreePage
;
600 ASSERT(FreePageCount
!= 0);
602 /* Consume free pages */
608 KeBugCheckEx(INSTALL_MORE_MEMORY
,
609 MmNumberOfPhysicalPages
,
611 MxOldFreeDescriptor
.PageCount
,
615 /* Write out this PTE */
617 ASSERT(PointerPte
->u
.Hard
.Valid
== 0);
618 ASSERT(TempPte
.u
.Hard
.Valid
== 1);
619 *PointerPte
= TempPte
;
622 RtlZeroMemory(MiPteToAddress(PointerPte
), PAGE_SIZE
);
629 /* Do the next address range */
630 NextEntry
= MdBlock
->ListEntry
.Flink
;
633 /* Now update the free descriptors to consume the pages we used up during the PFN allocation loop */
634 MxFreeDescriptor
->BasePage
= FreePage
;
635 MxFreeDescriptor
->PageCount
= FreePageCount
;
640 MiBuildPfnDatabaseFromPages(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
645 PFN_NUMBER PageFrameIndex
, StartupPdIndex
, PtePageIndex
;
647 ULONG_PTR BaseAddress
= 0;
649 /* PFN of the startup page directory */
650 StartupPdIndex
= PFN_FROM_PTE(MiAddressToPde(PDE_BASE
));
652 /* Start with the first PDE and scan them all */
653 PointerPde
= MiAddressToPde(NULL
);
654 Count
= PD_COUNT
* PDE_COUNT
;
655 for (i
= 0; i
< Count
; i
++)
657 /* Check for valid PDE */
658 if (PointerPde
->u
.Hard
.Valid
== 1)
660 /* Get the PFN from it */
661 PageFrameIndex
= PFN_FROM_PTE(PointerPde
);
663 /* Do we want a PFN entry for this page? */
664 if (MiIsRegularMemory(LoaderBlock
, PageFrameIndex
))
666 /* Yes we do, set it up */
667 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
668 Pfn1
->u4
.PteFrame
= StartupPdIndex
;
669 Pfn1
->PteAddress
= PointerPde
;
670 Pfn1
->u2
.ShareCount
++;
671 Pfn1
->u3
.e2
.ReferenceCount
= 1;
672 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
673 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
681 /* Now get the PTE and scan the pages */
682 PointerPte
= MiAddressToPte(BaseAddress
);
683 for (j
= 0; j
< PTE_COUNT
; j
++)
685 /* Check for a valid PTE */
686 if (PointerPte
->u
.Hard
.Valid
== 1)
688 /* Increase the shared count of the PFN entry for the PDE */
689 ASSERT(Pfn1
!= NULL
);
690 Pfn1
->u2
.ShareCount
++;
692 /* Now check if the PTE is valid memory too */
693 PtePageIndex
= PFN_FROM_PTE(PointerPte
);
694 if (MiIsRegularMemory(LoaderBlock
, PtePageIndex
))
697 * Only add pages above the end of system code or pages
698 * that are part of nonpaged pool
700 if ((BaseAddress
>= 0xA0000000) ||
701 ((BaseAddress
>= (ULONG_PTR
)MmNonPagedPoolStart
) &&
702 (BaseAddress
< (ULONG_PTR
)MmNonPagedPoolStart
+
703 MmSizeOfNonPagedPoolInBytes
)))
705 /* Get the PFN entry and make sure it too is valid */
706 Pfn2
= MiGetPfnEntry(PtePageIndex
);
707 if ((MmIsAddressValid(Pfn2
)) &&
708 (MmIsAddressValid(Pfn2
+ 1)))
710 /* Setup the PFN entry */
711 Pfn2
->u4
.PteFrame
= PageFrameIndex
;
712 Pfn2
->PteAddress
= PointerPte
;
713 Pfn2
->u2
.ShareCount
++;
714 Pfn2
->u3
.e2
.ReferenceCount
= 1;
715 Pfn2
->u3
.e1
.PageLocation
= ActiveAndValid
;
716 Pfn2
->u3
.e1
.CacheAttribute
= MiNonCached
;
724 BaseAddress
+= PAGE_SIZE
;
729 /* Next PDE mapped address */
730 BaseAddress
+= PDE_MAPPED_VA
;
740 MiBuildPfnDatabaseZeroPage(VOID
)
745 /* Grab the lowest page and check if it has no real references */
746 Pfn1
= MiGetPfnEntry(MmLowestPhysicalPage
);
747 if (!(MmLowestPhysicalPage
) && !(Pfn1
->u3
.e2
.ReferenceCount
))
749 /* Make it a bogus page to catch errors */
750 PointerPde
= MiAddressToPde(0xFFFFFFFF);
751 Pfn1
->u4
.PteFrame
= PFN_FROM_PTE(PointerPde
);
752 Pfn1
->PteAddress
= PointerPde
;
753 Pfn1
->u2
.ShareCount
++;
754 Pfn1
->u3
.e2
.ReferenceCount
= 0xFFF0;
755 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
756 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
762 MiBuildPfnDatabaseFromLoaderBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
764 PLIST_ENTRY NextEntry
;
765 PFN_NUMBER PageCount
= 0;
766 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
767 PFN_NUMBER PageFrameIndex
;
773 /* Now loop through the descriptors */
774 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
775 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
777 /* Get the current descriptor */
778 MdBlock
= CONTAINING_RECORD(NextEntry
,
779 MEMORY_ALLOCATION_DESCRIPTOR
,
783 PageCount
= MdBlock
->PageCount
;
784 PageFrameIndex
= MdBlock
->BasePage
;
786 /* Don't allow memory above what the PFN database is mapping */
787 if (PageFrameIndex
> MmHighestPhysicalPage
)
789 /* Since they are ordered, everything past here will be larger */
793 /* On the other hand, the end page might be higher up... */
794 if ((PageFrameIndex
+ PageCount
) > (MmHighestPhysicalPage
+ 1))
796 /* In which case we'll trim the descriptor to go as high as we can */
797 PageCount
= MmHighestPhysicalPage
+ 1 - PageFrameIndex
;
798 MdBlock
->PageCount
= PageCount
;
800 /* But if there's nothing left to trim, we got too high, so quit */
801 if (!PageCount
) break;
804 /* Now check the descriptor type */
805 switch (MdBlock
->MemoryType
)
807 /* Check for bad RAM */
810 DPRINT1("You have damaged RAM modules. Stopping boot\n");
814 /* Check for free RAM */
816 case LoaderLoadedProgram
:
817 case LoaderFirmwareTemporary
:
818 case LoaderOsloaderStack
:
820 /* Get the last page of this descriptor. Note we loop backwards */
821 PageFrameIndex
+= PageCount
- 1;
822 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
824 /* Lock the PFN Database */
825 OldIrql
= KeAcquireQueuedSpinLock(LockQueuePfnLock
);
828 /* If the page really has no references, mark it as free */
829 if (!Pfn1
->u3
.e2
.ReferenceCount
)
831 /* Add it to the free list */
832 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
833 MiInsertPageInFreeList(PageFrameIndex
);
836 /* Go to the next page */
841 /* Release PFN database */
842 KeReleaseQueuedSpinLock(LockQueuePfnLock
, OldIrql
);
844 /* Done with this block */
847 /* Check for pages that are invisible to us */
848 case LoaderFirmwarePermanent
:
849 case LoaderSpecialMemory
:
850 case LoaderBBTMemory
:
857 /* Map these pages with the KSEG0 mapping that adds 0x80000000 */
858 PointerPte
= MiAddressToPte(KSEG0_BASE
+ (PageFrameIndex
<< PAGE_SHIFT
));
859 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
862 /* Check if the page is really unused */
863 PointerPde
= MiAddressToPde(KSEG0_BASE
+ (PageFrameIndex
<< PAGE_SHIFT
));
864 if (!Pfn1
->u3
.e2
.ReferenceCount
)
866 /* Mark it as being in-use */
867 Pfn1
->u4
.PteFrame
= PFN_FROM_PTE(PointerPde
);
868 Pfn1
->PteAddress
= PointerPte
;
869 Pfn1
->u2
.ShareCount
++;
870 Pfn1
->u3
.e2
.ReferenceCount
= 1;
871 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
872 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
874 /* Check for RAM disk page */
875 if (MdBlock
->MemoryType
== LoaderXIPRom
)
877 /* Make it a pseudo-I/O ROM mapping */
879 Pfn1
->u2
.ShareCount
= 0;
880 Pfn1
->u3
.e2
.ReferenceCount
= 0;
881 Pfn1
->u3
.e1
.PageLocation
= 0;
883 Pfn1
->u4
.InPageError
= 0;
884 Pfn1
->u3
.e1
.PrototypePte
= 1;
888 /* Advance page structures */
896 /* Next descriptor entry */
897 NextEntry
= MdBlock
->ListEntry
.Flink
;
903 MiBuildPfnDatabaseSelf(VOID
)
905 PMMPTE PointerPte
, LastPte
;
908 /* Loop the PFN database page */
909 PointerPte
= MiAddressToPte(MiGetPfnEntry(MmLowestPhysicalPage
));
910 LastPte
= MiAddressToPte(MiGetPfnEntry(MmHighestPhysicalPage
));
911 while (PointerPte
<= LastPte
)
913 /* Make sure the page is valid */
914 if (PointerPte
->u
.Hard
.Valid
== 1)
916 /* Get the PFN entry and just mark it referenced */
917 Pfn1
= MiGetPfnEntry(PointerPte
->u
.Hard
.PageFrameNumber
);
918 Pfn1
->u2
.ShareCount
= 1;
919 Pfn1
->u3
.e2
.ReferenceCount
= 1;
929 MiInitializePfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
931 /* Scan memory and start setting up PFN entries */
932 MiBuildPfnDatabaseFromPages(LoaderBlock
);
934 /* Add the zero page */
935 MiBuildPfnDatabaseZeroPage();
937 /* Scan the loader block and build the rest of the PFN database */
938 MiBuildPfnDatabaseFromLoaderBlock(LoaderBlock
);
940 /* Finally add the pages for the PFN database itself */
941 MiBuildPfnDatabaseSelf();
946 MiAdjustWorkingSetManagerParameters(IN BOOLEAN Client
)
948 /* This function needs to do more work, for now, we tune page minimums */
950 /* Check for a system with around 64MB RAM or more */
951 if (MmNumberOfPhysicalPages
>= (63 * _1MB
) / PAGE_SIZE
)
953 /* Double the minimum amount of pages we consider for a "plenty free" scenario */
954 MmPlentyFreePages
*= 2;
960 MiNotifyMemoryEvents(VOID
)
962 /* Are we in a low-memory situation? */
963 if (MmAvailablePages
< MmLowMemoryThreshold
)
965 /* Clear high, set low */
966 if (KeReadStateEvent(MiHighMemoryEvent
)) KeClearEvent(MiHighMemoryEvent
);
967 if (!KeReadStateEvent(MiLowMemoryEvent
)) KeSetEvent(MiLowMemoryEvent
, 0, FALSE
);
969 else if (MmAvailablePages
< MmHighMemoryThreshold
)
971 /* We are in between, clear both */
972 if (KeReadStateEvent(MiHighMemoryEvent
)) KeClearEvent(MiHighMemoryEvent
);
973 if (KeReadStateEvent(MiLowMemoryEvent
)) KeClearEvent(MiLowMemoryEvent
);
977 /* Clear low, set high */
978 if (KeReadStateEvent(MiLowMemoryEvent
)) KeClearEvent(MiLowMemoryEvent
);
979 if (!KeReadStateEvent(MiHighMemoryEvent
)) KeSetEvent(MiHighMemoryEvent
, 0, FALSE
);
985 MiCreateMemoryEvent(IN PUNICODE_STRING Name
,
992 OBJECT_ATTRIBUTES ObjectAttributes
;
993 SECURITY_DESCRIPTOR SecurityDescriptor
;
996 Status
= RtlCreateSecurityDescriptor(&SecurityDescriptor
,
997 SECURITY_DESCRIPTOR_REVISION
);
998 if (!NT_SUCCESS(Status
)) return Status
;
1000 /* One ACL with 3 ACEs, containing each one SID */
1001 DaclLength
= sizeof(ACL
) +
1002 3 * sizeof(ACCESS_ALLOWED_ACE
) +
1003 RtlLengthSid(SeLocalSystemSid
) +
1004 RtlLengthSid(SeAliasAdminsSid
) +
1005 RtlLengthSid(SeWorldSid
);
1007 /* Allocate space for the DACL */
1008 Dacl
= ExAllocatePoolWithTag(PagedPool
, DaclLength
, 'lcaD');
1009 if (!Dacl
) return STATUS_INSUFFICIENT_RESOURCES
;
1011 /* Setup the ACL inside it */
1012 Status
= RtlCreateAcl(Dacl
, DaclLength
, ACL_REVISION
);
1013 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1015 /* Add query rights for everyone */
1016 Status
= RtlAddAccessAllowedAce(Dacl
,
1018 SYNCHRONIZE
| EVENT_QUERY_STATE
| READ_CONTROL
,
1020 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1022 /* Full rights for the admin */
1023 Status
= RtlAddAccessAllowedAce(Dacl
,
1027 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1029 /* As well as full rights for the system */
1030 Status
= RtlAddAccessAllowedAce(Dacl
,
1034 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1036 /* Set this DACL inside the SD */
1037 Status
= RtlSetDaclSecurityDescriptor(&SecurityDescriptor
,
1041 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1043 /* Setup the event attributes, making sure it's a permanent one */
1044 InitializeObjectAttributes(&ObjectAttributes
,
1046 OBJ_KERNEL_HANDLE
| OBJ_PERMANENT
,
1048 &SecurityDescriptor
);
1050 /* Create the event */
1051 Status
= ZwCreateEvent(&EventHandle
,
1060 /* Check if this is the success path */
1061 if (NT_SUCCESS(Status
))
1063 /* Add a reference to the object, then close the handle we had */
1064 Status
= ObReferenceObjectByHandle(EventHandle
,
1070 ZwClose (EventHandle
);
1079 MiInitializeMemoryEvents(VOID
)
1081 UNICODE_STRING LowString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowMemoryCondition");
1082 UNICODE_STRING HighString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighMemoryCondition");
1083 UNICODE_STRING LowPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowPagedPoolCondition");
1084 UNICODE_STRING HighPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighPagedPoolCondition");
1085 UNICODE_STRING LowNonPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowNonPagedPoolCondition");
1086 UNICODE_STRING HighNonPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighNonPagedPoolCondition");
1089 /* Check if we have a registry setting */
1090 if (MmLowMemoryThreshold
)
1092 /* Convert it to pages */
1093 MmLowMemoryThreshold
*= (_1MB
/ PAGE_SIZE
);
1097 /* The low memory threshold is hit when we don't consider that we have "plenty" of free pages anymore */
1098 MmLowMemoryThreshold
= MmPlentyFreePages
;
1100 /* More than one GB of memory? */
1101 if (MmNumberOfPhysicalPages
> 0x40000)
1103 /* Start at 32MB, and add another 16MB for each GB */
1104 MmLowMemoryThreshold
= (32 * _1MB
) / PAGE_SIZE
;
1105 MmLowMemoryThreshold
+= ((MmNumberOfPhysicalPages
- 0x40000) >> 7);
1107 else if (MmNumberOfPhysicalPages
> 0x8000)
1109 /* For systems with > 128MB RAM, add another 4MB for each 128MB */
1110 MmLowMemoryThreshold
+= ((MmNumberOfPhysicalPages
- 0x8000) >> 5);
1113 /* Don't let the minimum threshold go past 64MB */
1114 MmLowMemoryThreshold
= min(MmLowMemoryThreshold
, (64 * _1MB
) / PAGE_SIZE
);
1117 /* Check if we have a registry setting */
1118 if (MmHighMemoryThreshold
)
1120 /* Convert it into pages */
1121 MmHighMemoryThreshold
*= (_1MB
/ PAGE_SIZE
);
1125 /* Otherwise, the default is three times the low memory threshold */
1126 MmHighMemoryThreshold
= 3 * MmLowMemoryThreshold
;
1127 ASSERT(MmHighMemoryThreshold
> MmLowMemoryThreshold
);
1130 /* Make sure high threshold is actually higher than the low */
1131 MmHighMemoryThreshold
= max(MmHighMemoryThreshold
, MmLowMemoryThreshold
);
1133 /* Create the memory events for all the thresholds */
1134 Status
= MiCreateMemoryEvent(&LowString
, &MiLowMemoryEvent
);
1135 if (!NT_SUCCESS(Status
)) return FALSE
;
1136 Status
= MiCreateMemoryEvent(&HighString
, &MiHighMemoryEvent
);
1137 if (!NT_SUCCESS(Status
)) return FALSE
;
1138 Status
= MiCreateMemoryEvent(&LowPagedPoolString
, &MiLowPagedPoolEvent
);
1139 if (!NT_SUCCESS(Status
)) return FALSE
;
1140 Status
= MiCreateMemoryEvent(&HighPagedPoolString
, &MiHighPagedPoolEvent
);
1141 if (!NT_SUCCESS(Status
)) return FALSE
;
1142 Status
= MiCreateMemoryEvent(&LowNonPagedPoolString
, &MiLowNonPagedPoolEvent
);
1143 if (!NT_SUCCESS(Status
)) return FALSE
;
1144 Status
= MiCreateMemoryEvent(&HighNonPagedPoolString
, &MiHighNonPagedPoolEvent
);
1145 if (!NT_SUCCESS(Status
)) return FALSE
;
1147 /* Now setup the pool events */
1148 MiInitializePoolEvents();
1150 /* Set the initial event state */
1151 MiNotifyMemoryEvents();
1157 MiAddHalIoMappings(VOID
)
1162 ULONG i
, j
, PdeCount
;
1163 PFN_NUMBER PageFrameIndex
;
1165 /* HAL Heap address -- should be on a PDE boundary */
1166 BaseAddress
= (PVOID
)0xFFC00000;
1167 ASSERT(MiAddressToPteOffset(BaseAddress
) == 0);
1169 /* Check how many PDEs the heap has */
1170 PointerPde
= MiAddressToPde(BaseAddress
);
1171 PdeCount
= PDE_COUNT
- ADDR_TO_PDE_OFFSET(BaseAddress
);
1172 for (i
= 0; i
< PdeCount
; i
++)
1174 /* Does the HAL own this mapping? */
1175 if ((PointerPde
->u
.Hard
.Valid
== 1) &&
1176 (PointerPde
->u
.Hard
.LargePage
== 0))
1178 /* Get the PTE for it and scan each page */
1179 PointerPte
= MiAddressToPte(BaseAddress
);
1180 for (j
= 0 ; j
< PTE_COUNT
; j
++)
1182 /* Does the HAL own this page? */
1183 if (PointerPte
->u
.Hard
.Valid
== 1)
1185 /* Is the HAL using it for device or I/O mapped memory? */
1186 PageFrameIndex
= PFN_FROM_PTE(PointerPte
);
1187 if (!MiGetPfnEntry(PageFrameIndex
))
1189 /* FIXME: For PAT, we need to track I/O cache attributes for coherency */
1190 DPRINT1("HAL I/O Mapping at %p is unsafe\n", BaseAddress
);
1194 /* Move to the next page */
1195 BaseAddress
= (PVOID
)((ULONG_PTR
)BaseAddress
+ PAGE_SIZE
);
1201 /* Move to the next address */
1202 BaseAddress
= (PVOID
)((ULONG_PTR
)BaseAddress
+ PDE_MAPPED_VA
);
1205 /* Move to the next PDE */
1212 MmDumpArmPfnDatabase(VOID
)
1216 PCHAR Consumer
= "Unknown";
1218 ULONG ActivePages
= 0, FreePages
= 0, OtherPages
= 0;
1220 KeRaiseIrql(HIGH_LEVEL
, &OldIrql
);
1223 // Loop the PFN database
1225 for (i
= 0; i
<= MmHighestPhysicalPage
; i
++)
1227 Pfn1
= MiGetPfnEntry(i
);
1228 if (!Pfn1
) continue;
1231 // Get the page location
1233 switch (Pfn1
->u3
.e1
.PageLocation
)
1235 case ActiveAndValid
:
1237 Consumer
= "Active and Valid";
1243 Consumer
= "Free Page List";
1249 Consumer
= "Other (ASSERT!)";
1255 // Pretty-print the page
1257 DbgPrint("0x%08p:\t%20s\t(%02d.%02d) [%08p-%08p])\n",
1260 Pfn1
->u3
.e2
.ReferenceCount
,
1261 Pfn1
->u2
.ShareCount
,
1266 DbgPrint("Active: %d pages\t[%d KB]\n", ActivePages
, (ActivePages
<< PAGE_SHIFT
) / 1024);
1267 DbgPrint("Free: %d pages\t[%d KB]\n", FreePages
, (FreePages
<< PAGE_SHIFT
) / 1024);
1268 DbgPrint("Other: %d pages\t[%d KB]\n", OtherPages
, (OtherPages
<< PAGE_SHIFT
) / 1024);
1270 KeLowerIrql(OldIrql
);
1275 MiPagesInLoaderBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
1276 IN PBOOLEAN IncludeType
)
1278 PLIST_ENTRY NextEntry
;
1279 PFN_NUMBER PageCount
= 0;
1280 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
1283 // Now loop through the descriptors
1285 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1286 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1289 // Grab each one, and check if it's one we should include
1291 MdBlock
= CONTAINING_RECORD(NextEntry
,
1292 MEMORY_ALLOCATION_DESCRIPTOR
,
1294 if ((MdBlock
->MemoryType
< LoaderMaximum
) &&
1295 (IncludeType
[MdBlock
->MemoryType
]))
1298 // Add this to our running total
1300 PageCount
+= MdBlock
->PageCount
;
1304 // Try the next descriptor
1306 NextEntry
= MdBlock
->ListEntry
.Flink
;
1315 PPHYSICAL_MEMORY_DESCRIPTOR
1317 MmInitializeMemoryLimits(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
1318 IN PBOOLEAN IncludeType
)
1320 PLIST_ENTRY NextEntry
;
1321 ULONG Run
= 0, InitialRuns
= 0;
1322 PFN_NUMBER NextPage
= -1, PageCount
= 0;
1323 PPHYSICAL_MEMORY_DESCRIPTOR Buffer
, NewBuffer
;
1324 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
1327 // Scan the memory descriptors
1329 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1330 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1333 // For each one, increase the memory allocation estimate
1336 NextEntry
= NextEntry
->Flink
;
1340 // Allocate the maximum we'll ever need
1342 Buffer
= ExAllocatePoolWithTag(NonPagedPool
,
1343 sizeof(PHYSICAL_MEMORY_DESCRIPTOR
) +
1344 sizeof(PHYSICAL_MEMORY_RUN
) *
1347 if (!Buffer
) return NULL
;
1350 // For now that's how many runs we have
1352 Buffer
->NumberOfRuns
= InitialRuns
;
1355 // Now loop through the descriptors again
1357 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1358 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1361 // Grab each one, and check if it's one we should include
1363 MdBlock
= CONTAINING_RECORD(NextEntry
,
1364 MEMORY_ALLOCATION_DESCRIPTOR
,
1366 if ((MdBlock
->MemoryType
< LoaderMaximum
) &&
1367 (IncludeType
[MdBlock
->MemoryType
]))
1370 // Add this to our running total
1372 PageCount
+= MdBlock
->PageCount
;
1375 // Check if the next page is described by the next descriptor
1377 if (MdBlock
->BasePage
== NextPage
)
1380 // Combine it into the same physical run
1382 ASSERT(MdBlock
->PageCount
!= 0);
1383 Buffer
->Run
[Run
- 1].PageCount
+= MdBlock
->PageCount
;
1384 NextPage
+= MdBlock
->PageCount
;
1389 // Otherwise just duplicate the descriptor's contents
1391 Buffer
->Run
[Run
].BasePage
= MdBlock
->BasePage
;
1392 Buffer
->Run
[Run
].PageCount
= MdBlock
->PageCount
;
1393 NextPage
= Buffer
->Run
[Run
].BasePage
+ Buffer
->Run
[Run
].PageCount
;
1396 // And in this case, increase the number of runs
1403 // Try the next descriptor
1405 NextEntry
= MdBlock
->ListEntry
.Flink
;
1409 // We should not have been able to go past our initial estimate
1411 ASSERT(Run
<= Buffer
->NumberOfRuns
);
1414 // Our guess was probably exaggerated...
1416 if (InitialRuns
> Run
)
1419 // Allocate a more accurately sized buffer
1421 NewBuffer
= ExAllocatePoolWithTag(NonPagedPool
,
1422 sizeof(PHYSICAL_MEMORY_DESCRIPTOR
) +
1423 sizeof(PHYSICAL_MEMORY_RUN
) *
1429 // Copy the old buffer into the new, then free it
1431 RtlCopyMemory(NewBuffer
->Run
,
1433 sizeof(PHYSICAL_MEMORY_RUN
) * Run
);
1437 // Now use the new buffer
1444 // Write the final numbers, and return it
1446 Buffer
->NumberOfRuns
= Run
;
1447 Buffer
->NumberOfPages
= PageCount
;
1453 MiBuildPagedPool(VOID
)
1455 PMMPTE PointerPte
, PointerPde
;
1456 MMPTE TempPte
= ValidKernelPte
;
1457 PFN_NUMBER PageFrameIndex
;
1459 ULONG Size
, BitMapSize
;
1462 // Get the page frame number for the system page directory
1464 PointerPte
= MiAddressToPte(PDE_BASE
);
1465 ASSERT(PD_COUNT
== 1);
1466 MmSystemPageDirectory
[0] = PFN_FROM_PTE(PointerPte
);
1469 // Allocate a system PTE which will hold a copy of the page directory
1471 PointerPte
= MiReserveSystemPtes(1, SystemPteSpace
);
1473 MmSystemPagePtes
= MiPteToAddress(PointerPte
);
1476 // Make this system PTE point to the system page directory.
1477 // It is now essentially double-mapped. This will be used later for lazy
1478 // evaluation of PDEs accross process switches, similarly to how the Global
1479 // page directory array in the old ReactOS Mm is used (but in a less hacky
1482 TempPte
= ValidKernelPte
;
1483 ASSERT(PD_COUNT
== 1);
1484 TempPte
.u
.Hard
.PageFrameNumber
= MmSystemPageDirectory
[0];
1485 ASSERT(PointerPte
->u
.Hard
.Valid
== 0);
1486 ASSERT(TempPte
.u
.Hard
.Valid
== 1);
1487 *PointerPte
= TempPte
;
1490 // Let's get back to paged pool work: size it up.
1491 // By default, it should be twice as big as nonpaged pool.
1493 MmSizeOfPagedPoolInBytes
= 2 * MmMaximumNonPagedPoolInBytes
;
1494 if (MmSizeOfPagedPoolInBytes
> ((ULONG_PTR
)MmNonPagedSystemStart
-
1495 (ULONG_PTR
)MmPagedPoolStart
))
1498 // On the other hand, we have limited VA space, so make sure that the VA
1499 // for paged pool doesn't overflow into nonpaged pool VA. Otherwise, set
1500 // whatever maximum is possible.
1502 MmSizeOfPagedPoolInBytes
= (ULONG_PTR
)MmNonPagedSystemStart
-
1503 (ULONG_PTR
)MmPagedPoolStart
;
1507 // Get the size in pages and make sure paged pool is at least 32MB.
1509 Size
= MmSizeOfPagedPoolInBytes
;
1510 if (Size
< MI_MIN_INIT_PAGED_POOLSIZE
) Size
= MI_MIN_INIT_PAGED_POOLSIZE
;
1511 Size
= BYTES_TO_PAGES(Size
);
1514 // Now check how many PTEs will be required for these many pages.
1516 Size
= (Size
+ (1024 - 1)) / 1024;
1519 // Recompute the page-aligned size of the paged pool, in bytes and pages.
1521 MmSizeOfPagedPoolInBytes
= Size
* PAGE_SIZE
* 1024;
1522 MmSizeOfPagedPoolInPages
= MmSizeOfPagedPoolInBytes
>> PAGE_SHIFT
;
1525 // Let's be really sure this doesn't overflow into nonpaged system VA
1527 ASSERT((MmSizeOfPagedPoolInBytes
+ (ULONG_PTR
)MmPagedPoolStart
) <=
1528 (ULONG_PTR
)MmNonPagedSystemStart
);
1531 // This is where paged pool ends
1533 MmPagedPoolEnd
= (PVOID
)(((ULONG_PTR
)MmPagedPoolStart
+
1534 MmSizeOfPagedPoolInBytes
) - 1);
1537 // So now get the PDE for paged pool and zero it out
1539 PointerPde
= MiAddressToPde(MmPagedPoolStart
);
1540 RtlZeroMemory(PointerPde
,
1541 (1 + MiAddressToPde(MmPagedPoolEnd
) - PointerPde
) * sizeof(MMPTE
));
1544 // Next, get the first and last PTE
1546 PointerPte
= MiAddressToPte(MmPagedPoolStart
);
1547 MmPagedPoolInfo
.FirstPteForPagedPool
= PointerPte
;
1548 MmPagedPoolInfo
.LastPteForPagedPool
= MiAddressToPte(MmPagedPoolEnd
);
1551 // Lock the PFN database
1553 OldIrql
= KeAcquireQueuedSpinLock(LockQueuePfnLock
);
1555 /* Allocate a page and map the first paged pool PDE */
1556 PageFrameIndex
= MiRemoveZeroPage(0);
1557 TempPte
.u
.Hard
.PageFrameNumber
= PageFrameIndex
;
1558 ASSERT(PointerPde
->u
.Hard
.Valid
== 0);
1559 ASSERT(TempPte
.u
.Hard
.Valid
== 1);
1560 *PointerPde
= TempPte
;
1562 /* Initialize the PFN entry for it */
1563 MiInitializePfnForOtherProcess(PageFrameIndex
,
1565 MmSystemPageDirectory
[(PointerPde
- (PMMPTE
)PDE_BASE
) / PDE_COUNT
]);
1568 // Release the PFN database lock
1570 KeReleaseQueuedSpinLock(LockQueuePfnLock
, OldIrql
);
1573 // We only have one PDE mapped for now... at fault time, additional PDEs
1574 // will be allocated to handle paged pool growth. This is where they'll have
1577 MmPagedPoolInfo
.NextPdeForPagedPoolExpansion
= PointerPde
+ 1;
1580 // We keep track of each page via a bit, so check how big the bitmap will
1581 // have to be (make sure to align our page count such that it fits nicely
1582 // into a 4-byte aligned bitmap.
1584 // We'll also allocate the bitmap header itself part of the same buffer.
1587 ASSERT(Size
== MmSizeOfPagedPoolInPages
);
1589 Size
= sizeof(RTL_BITMAP
) + (((Size
+ 31) / 32) * sizeof(ULONG
));
1592 // Allocate the allocation bitmap, which tells us which regions have not yet
1593 // been mapped into memory
1595 MmPagedPoolInfo
.PagedPoolAllocationMap
= ExAllocatePoolWithTag(NonPagedPool
,
1598 ASSERT(MmPagedPoolInfo
.PagedPoolAllocationMap
);
1601 // Initialize it such that at first, only the first page's worth of PTEs is
1602 // marked as allocated (incidentially, the first PDE we allocated earlier).
1604 RtlInitializeBitMap(MmPagedPoolInfo
.PagedPoolAllocationMap
,
1605 (PULONG
)(MmPagedPoolInfo
.PagedPoolAllocationMap
+ 1),
1607 RtlSetAllBits(MmPagedPoolInfo
.PagedPoolAllocationMap
);
1608 RtlClearBits(MmPagedPoolInfo
.PagedPoolAllocationMap
, 0, 1024);
1611 // We have a second bitmap, which keeps track of where allocations end.
1612 // Given the allocation bitmap and a base address, we can therefore figure
1613 // out which page is the last page of that allocation, and thus how big the
1614 // entire allocation is.
1616 MmPagedPoolInfo
.EndOfPagedPoolBitmap
= ExAllocatePoolWithTag(NonPagedPool
,
1619 ASSERT(MmPagedPoolInfo
.EndOfPagedPoolBitmap
);
1620 RtlInitializeBitMap(MmPagedPoolInfo
.EndOfPagedPoolBitmap
,
1621 (PULONG
)(MmPagedPoolInfo
.EndOfPagedPoolBitmap
+ 1),
1625 // Since no allocations have been made yet, there are no bits set as the end
1627 RtlClearAllBits(MmPagedPoolInfo
.EndOfPagedPoolBitmap
);
1630 // Initialize paged pool.
1632 InitializePool(PagedPool
, 0);
1634 /* Default low threshold of 30MB or one fifth of paged pool */
1635 MiLowPagedPoolThreshold
= (30 * _1MB
) >> PAGE_SHIFT
;
1636 MiLowPagedPoolThreshold
= min(MiLowPagedPoolThreshold
, Size
/ 5);
1638 /* Default high threshold of 60MB or 25% */
1639 MiHighPagedPoolThreshold
= (60 * _1MB
) >> PAGE_SHIFT
;
1640 MiHighPagedPoolThreshold
= min(MiHighPagedPoolThreshold
, (Size
* 2) / 5);
1641 ASSERT(MiLowPagedPoolThreshold
< MiHighPagedPoolThreshold
);
1646 MmArmInitSystem(IN ULONG Phase
,
1647 IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
1650 BOOLEAN IncludeType
[LoaderMaximum
];
1652 PPHYSICAL_MEMORY_RUN Run
;
1653 PFN_NUMBER PageCount
;
1656 // Instantiate memory that we don't consider RAM/usable
1657 // We use the same exclusions that Windows does, in order to try to be
1658 // compatible with WinLDR-style booting
1660 for (i
= 0; i
< LoaderMaximum
; i
++) IncludeType
[i
] = TRUE
;
1661 IncludeType
[LoaderBad
] = FALSE
;
1662 IncludeType
[LoaderFirmwarePermanent
] = FALSE
;
1663 IncludeType
[LoaderSpecialMemory
] = FALSE
;
1664 IncludeType
[LoaderBBTMemory
] = FALSE
;
1667 /* Initialize the phase 0 temporary event */
1668 KeInitializeEvent(&MiTempEvent
, NotificationEvent
, FALSE
);
1670 /* Set all the events to use the temporary event for now */
1671 MiLowMemoryEvent
= &MiTempEvent
;
1672 MiHighMemoryEvent
= &MiTempEvent
;
1673 MiLowPagedPoolEvent
= &MiTempEvent
;
1674 MiHighPagedPoolEvent
= &MiTempEvent
;
1675 MiLowNonPagedPoolEvent
= &MiTempEvent
;
1676 MiHighNonPagedPoolEvent
= &MiTempEvent
;
1679 // Define the basic user vs. kernel address space separation
1681 MmSystemRangeStart
= (PVOID
)KSEG0_BASE
;
1682 MmUserProbeAddress
= (ULONG_PTR
)MmSystemRangeStart
- 0x10000;
1683 MmHighestUserAddress
= (PVOID
)(MmUserProbeAddress
- 1);
1685 /* Highest PTE and PDE based on the addresses above */
1686 MiHighestUserPte
= MiAddressToPte(MmHighestUserAddress
);
1687 MiHighestUserPde
= MiAddressToPde(MmHighestUserAddress
);
1690 // Get the size of the boot loader's image allocations and then round
1691 // that region up to a PDE size, so that any PDEs we might create for
1692 // whatever follows are separate from the PDEs that boot loader might've
1693 // already created (and later, we can blow all that away if we want to).
1695 MmBootImageSize
= KeLoaderBlock
->Extension
->LoaderPagesSpanned
;
1696 MmBootImageSize
*= PAGE_SIZE
;
1697 MmBootImageSize
= (MmBootImageSize
+ PDE_MAPPED_VA
- 1) & ~(PDE_MAPPED_VA
- 1);
1698 ASSERT((MmBootImageSize
% PDE_MAPPED_VA
) == 0);
1701 // Set the size of session view, pool, and image
1703 MmSessionSize
= MI_SESSION_SIZE
;
1704 MmSessionViewSize
= MI_SESSION_VIEW_SIZE
;
1705 MmSessionPoolSize
= MI_SESSION_POOL_SIZE
;
1706 MmSessionImageSize
= MI_SESSION_IMAGE_SIZE
;
1709 // Set the size of system view
1711 MmSystemViewSize
= MI_SYSTEM_VIEW_SIZE
;
1714 // This is where it all ends
1716 MiSessionImageEnd
= (PVOID
)PTE_BASE
;
1719 // This is where we will load Win32k.sys and the video driver
1721 MiSessionImageStart
= (PVOID
)((ULONG_PTR
)MiSessionImageEnd
-
1722 MmSessionImageSize
);
1725 // So the view starts right below the session working set (itself below
1728 MiSessionViewStart
= (PVOID
)((ULONG_PTR
)MiSessionImageEnd
-
1729 MmSessionImageSize
-
1730 MI_SESSION_WORKING_SET_SIZE
-
1734 // Session pool follows
1736 MiSessionPoolEnd
= MiSessionViewStart
;
1737 MiSessionPoolStart
= (PVOID
)((ULONG_PTR
)MiSessionPoolEnd
-
1741 // And it all begins here
1743 MmSessionBase
= MiSessionPoolStart
;
1746 // Sanity check that our math is correct
1748 ASSERT((ULONG_PTR
)MmSessionBase
+ MmSessionSize
== PTE_BASE
);
1751 // Session space ends wherever image session space ends
1753 MiSessionSpaceEnd
= MiSessionImageEnd
;
1756 // System view space ends at session space, so now that we know where
1757 // this is, we can compute the base address of system view space itself.
1759 MiSystemViewStart
= (PVOID
)((ULONG_PTR
)MmSessionBase
-
1762 /* Compute the PTE addresses for all the addresses we carved out */
1763 MiSessionImagePteStart
= MiAddressToPte(MiSessionImageStart
);
1764 MiSessionImagePteEnd
= MiAddressToPte(MiSessionImageEnd
);
1765 MiSessionBasePte
= MiAddressToPte(MmSessionBase
);
1766 MiSessionLastPte
= MiAddressToPte(MiSessionSpaceEnd
);
1768 /* Initialize the user mode image list */
1769 InitializeListHead(&MmLoadedUserImageList
);
1771 /* Initialize the paged pool mutex */
1772 KeInitializeGuardedMutex(&MmPagedPoolMutex
);
1774 /* Initialize the Loader Lock */
1775 KeInitializeMutant(&MmSystemLoadLock
, FALSE
);
1778 // Count physical pages on the system
1780 PageCount
= MiPagesInLoaderBlock(LoaderBlock
, IncludeType
);
1783 // Check if this is a machine with less than 19MB of RAM
1785 if (PageCount
< MI_MIN_PAGES_FOR_SYSPTE_TUNING
)
1788 // Use the very minimum of system PTEs
1790 MmNumberOfSystemPtes
= 7000;
1795 // Use the default, but check if we have more than 32MB of RAM
1797 MmNumberOfSystemPtes
= 11000;
1798 if (PageCount
> MI_MIN_PAGES_FOR_SYSPTE_BOOST
)
1801 // Double the amount of system PTEs
1803 MmNumberOfSystemPtes
<<= 1;
1807 DPRINT("System PTE count has been tuned to %d (%d bytes)\n",
1808 MmNumberOfSystemPtes
, MmNumberOfSystemPtes
* PAGE_SIZE
);
1810 /* Initialize the platform-specific parts */
1811 MiInitMachineDependent(LoaderBlock
);
1814 // Sync us up with ReactOS Mm
1816 MiSyncARM3WithROS(MmNonPagedSystemStart
, (PVOID
)((ULONG_PTR
)MmNonPagedPoolEnd
- 1));
1817 MiSyncARM3WithROS(MmPfnDatabase
, (PVOID
)((ULONG_PTR
)MmNonPagedPoolStart
+ MmSizeOfNonPagedPoolInBytes
- 1));
1818 MiSyncARM3WithROS((PVOID
)HYPER_SPACE
, (PVOID
)(HYPER_SPACE
+ PAGE_SIZE
- 1));
1821 // Build the physical memory block
1823 MmPhysicalMemoryBlock
= MmInitializeMemoryLimits(LoaderBlock
,
1827 // Allocate enough buffer for the PFN bitmap
1828 // Align it up to a 32-bit boundary
1830 Bitmap
= ExAllocatePoolWithTag(NonPagedPool
,
1831 (((MmHighestPhysicalPage
+ 1) + 31) / 32) * 4,
1838 KeBugCheckEx(INSTALL_MORE_MEMORY
,
1839 MmNumberOfPhysicalPages
,
1840 MmLowestPhysicalPage
,
1841 MmHighestPhysicalPage
,
1846 // Initialize it and clear all the bits to begin with
1848 RtlInitializeBitMap(&MiPfnBitMap
,
1850 MmHighestPhysicalPage
+ 1);
1851 RtlClearAllBits(&MiPfnBitMap
);
1854 // Loop physical memory runs
1856 for (i
= 0; i
< MmPhysicalMemoryBlock
->NumberOfRuns
; i
++)
1861 Run
= &MmPhysicalMemoryBlock
->Run
[i
];
1862 DPRINT("PHYSICAL RAM [0x%08p to 0x%08p]\n",
1863 Run
->BasePage
<< PAGE_SHIFT
,
1864 (Run
->BasePage
+ Run
->PageCount
) << PAGE_SHIFT
);
1867 // Make sure it has pages inside it
1872 // Set the bits in the PFN bitmap
1874 RtlSetBits(&MiPfnBitMap
, Run
->BasePage
, Run
->PageCount
);
1878 /* Look for large page cache entries that need caching */
1879 MiSyncCachedRanges();
1881 /* Loop for HAL Heap I/O device mappings that need coherency tracking */
1882 MiAddHalIoMappings();
1884 /* Set the initial resident page count */
1885 MmResidentAvailablePages
= MmAvailablePages
- 32;
1887 /* Initialize large page structures on PAE/x64, and MmProcessList on x86 */
1888 MiInitializeLargePageSupport();
1890 /* Check if the registry says any drivers should be loaded with large pages */
1891 MiInitializeDriverLargePageList();
1893 /* Relocate the boot drivers into system PTE space and fixup their PFNs */
1894 MiReloadBootLoadedDrivers(LoaderBlock
);
1896 /* FIXME: Call out into Driver Verifier for initialization */
1898 /* Check how many pages the system has */
1899 if (MmNumberOfPhysicalPages
<= (13 * _1MB
))
1901 /* Set small system */
1902 MmSystemSize
= MmSmallSystem
;
1904 else if (MmNumberOfPhysicalPages
<= (19 * _1MB
))
1906 /* Set small system and add 100 pages for the cache */
1907 MmSystemSize
= MmSmallSystem
;
1908 MmSystemCacheWsMinimum
+= 100;
1912 /* Set medium system and add 400 pages for the cache */
1913 MmSystemSize
= MmMediumSystem
;
1914 MmSystemCacheWsMinimum
+= 400;
1917 /* Check for less than 24MB */
1918 if (MmNumberOfPhysicalPages
< ((24 * _1MB
) / PAGE_SIZE
))
1920 /* No more than 32 pages */
1921 MmSystemCacheWsMinimum
= 32;
1924 /* Check for more than 32MB */
1925 if (MmNumberOfPhysicalPages
>= ((32 * _1MB
) / PAGE_SIZE
))
1927 /* Check for product type being "Wi" for WinNT */
1928 if (MmProductType
== '\0i\0W')
1930 /* Then this is a large system */
1931 MmSystemSize
= MmLargeSystem
;
1935 /* For servers, we need 64MB to consider this as being large */
1936 if (MmNumberOfPhysicalPages
>= ((64 * _1MB
) / PAGE_SIZE
))
1938 /* Set it as large */
1939 MmSystemSize
= MmLargeSystem
;
1944 /* Check for more than 33 MB */
1945 if (MmNumberOfPhysicalPages
> ((33 * _1MB
) / PAGE_SIZE
))
1947 /* Add another 500 pages to the cache */
1948 MmSystemCacheWsMinimum
+= 500;
1951 /* Now setup the shared user data fields */
1952 ASSERT(SharedUserData
->NumberOfPhysicalPages
== 0);
1953 SharedUserData
->NumberOfPhysicalPages
= MmNumberOfPhysicalPages
;
1954 SharedUserData
->LargePageMinimum
= 0;
1956 /* Check for workstation (Wi for WinNT) */
1957 if (MmProductType
== '\0i\0W')
1959 /* Set Windows NT Workstation product type */
1960 SharedUserData
->NtProductType
= NtProductWinNt
;
1965 /* Check for LanMan server */
1966 if (MmProductType
== '\0a\0L')
1968 /* This is a domain controller */
1969 SharedUserData
->NtProductType
= NtProductLanManNt
;
1973 /* Otherwise it must be a normal server */
1974 SharedUserData
->NtProductType
= NtProductServer
;
1977 /* Set the product type, and make the system more aggressive with low memory */
1979 MmMinimumFreePages
= 81;
1982 /* Update working set tuning parameters */
1983 MiAdjustWorkingSetManagerParameters(!MmProductType
);
1985 /* Finetune the page count by removing working set and NP expansion */
1986 MmResidentAvailablePages
-= MiExpansionPoolPagesInitialCharge
;
1987 MmResidentAvailablePages
-= MmSystemCacheWsMinimum
;
1988 MmResidentAvailableAtInit
= MmResidentAvailablePages
;
1989 if (MmResidentAvailablePages
<= 0)
1991 /* This should not happen */
1992 DPRINT1("System cache working set too big\n");
1996 /* Size up paged pool and build the shadow system page directory */
1999 /* Debugger physical memory support is now ready to be used */
2000 MiDbgReadyForPhysical
= TRUE
;
2002 /* Initialize the loaded module list */
2003 MiInitializeLoadedModuleList(LoaderBlock
);
2007 // Always return success for now
2009 return STATUS_SUCCESS
;