2 * COPYRIGHT: GPL - See COPYING in the top level directory
3 * PROJECT: ReactOS Virtual DOS Machine
5 * PURPOSE: SuperVGA hardware emulation (Cirrus Logic CL-GD5434 compatible)
6 * PROGRAMMERS: Aleksandar Andrejevic <theflash AT sdf DOT lonestar DOT org>
12 /* DEFINES ********************************************************************/
14 #define VGA_NUM_BANKS 4
15 #define VGA_BANK_SIZE 0x10000
16 #define VGA_MAX_COLORS 256
17 #define VGA_PALETTE_SIZE (VGA_MAX_COLORS * 3)
18 #define VGA_BITMAP_INFO_SIZE (sizeof(BITMAPINFOHEADER) + 2 * (VGA_PALETTE_SIZE / 3))
19 #define VGA_MINIMUM_WIDTH 400
20 #define VGA_MINIMUM_HEIGHT 300
21 #define VGA_DAC_TO_COLOR(x) (((x) << 2) | ((x) >> 4))
22 #define VGA_COLOR_TO_DAC(x) ((x) >> 2)
23 #define VGA_INTERLACE_HIGH_BIT (1 << 13)
24 #define VGA_FONT_BANK 2
25 #define VGA_FONT_CHARACTERS 256
26 #define VGA_MAX_FONT_HEIGHT 32
27 #define VGA_FONT_SIZE (VGA_FONT_CHARACTERS * VGA_MAX_FONT_HEIGHT)
28 #define VGA_CLOCK_BASE 14318181
30 #define SVGA_IS_UNLOCKED (VgaSeqRegisters[SVGA_SEQ_UNLOCK_REG] == SVGA_SEQ_UNLOCKED)
31 #define SVGA_BANK_SIZE 0x100000
33 #define SVGA_SEQ_MAX_UNLOCKED_REG (SVGA_IS_UNLOCKED ? SVGA_SEQ_MAX_REG : SVGA_SEQ_EXT_MODE_REG)
34 #define SVGA_CRTC_MAX_UNLOCKED_REG (SVGA_IS_UNLOCKED ? SVGA_CRTC_MAX_REG : VGA_CRTC_MAX_REG)
35 #define SVGA_GC_MAX_UNLOCKED_REG (SVGA_IS_UNLOCKED ? SVGA_GC_MAX_REG : VGA_GC_MAX_REG)
37 /* Register I/O ports */
39 #define VGA_MISC_READ 0x3CC
40 #define VGA_MISC_WRITE 0x3C2
42 #define VGA_INSTAT0_READ 0x3C2
44 #define VGA_INSTAT1_READ_MONO 0x3BA
45 #define VGA_INSTAT1_READ_COLOR 0x3DA
47 #define VGA_FEATURE_READ 0x3CA
48 #define VGA_FEATURE_WRITE_MONO 0x3BA
49 #define VGA_FEATURE_WRITE_COLOR 0x3DA
51 #define VGA_AC_INDEX 0x3C0
52 #define VGA_AC_WRITE 0x3C0
53 #define VGA_AC_READ 0x3C1
55 #define VGA_SEQ_INDEX 0x3C4
56 #define VGA_SEQ_DATA 0x3C5
58 #define VGA_DAC_MASK 0x3C6
59 #define VGA_DAC_READ_INDEX 0x3C7
60 #define VGA_DAC_WRITE_INDEX 0x3C8
61 #define VGA_DAC_DATA 0x3C9
63 #define VGA_CRTC_INDEX_MONO 0x3B4
64 #define VGA_CRTC_DATA_MONO 0x3B5
65 #define VGA_CRTC_INDEX_COLOR 0x3D4
66 #define VGA_CRTC_DATA_COLOR 0x3D5
68 #define VGA_GC_INDEX 0x3CE
69 #define VGA_GC_DATA 0x3CF
71 #define VGA_SEQ_INDEX_MASK 0x1F
72 #define VGA_GC_INDEX_MASK 0x3F
73 #define VGA_CRTC_INDEX_MASK 0x3F
78 // Miscellaneous and Status Registers
81 /* Miscellaneous register bits */
82 #define VGA_MISC_COLOR (1 << 0)
83 #define VGA_MISC_RAM_ENABLED (1 << 1)
84 // #define VGA_MISC_CSEL1 (1 << 2)
85 // #define VGA_MISC_CSEL2 (1 << 3)
86 #define VGA_MISC_OE_PAGESEL (1 << 5)
87 #define VGA_MISC_HSYNCP (1 << 6)
88 #define VGA_MISC_VSYNCP (1 << 7)
90 /* Status register flags */
91 #define VGA_STAT_DD (1 << 0)
92 #define VGA_STAT_VRETRACE (1 << 3)
96 // Sequencer Registers
99 /* Sequencer reset register bits */
100 #define VGA_SEQ_RESET_AR (1 << 0)
101 #define VGA_SEQ_RESET_SR (1 << 1)
103 /* Sequencer clock register bits */
104 #define VGA_SEQ_CLOCK_98DM (1 << 0)
105 #define VGA_SEQ_CLOCK_SLR (1 << 2)
106 #define VGA_SEQ_CLOCK_DCR (1 << 3)
107 #define VGA_SEQ_CLOCK_S4 (1 << 4)
108 #define VGA_SEQ_CLOCK_SD (1 << 5)
110 /* Sequencer memory register bits */
111 #define VGA_SEQ_MEM_EXT (1 << 1)
112 #define VGA_SEQ_MEM_OE_DIS (1 << 2)
113 #define VGA_SEQ_MEM_C4 (1 << 3)
115 #define SVGA_SEQ_LOCKED 0x0F
116 #define SVGA_SEQ_UNLOCK_MASK 0x17
117 #define SVGA_SEQ_UNLOCKED 0x12
119 /* Sequencer extended mode register bits */
120 #define SVGA_SEQ_EXT_MODE_HIGH_RES (1 << 0)
122 /* Sequencer extended control register bits */
123 #define SVGA_SEQ_EXT_CONTROL_MMIO (1 << 2)
124 #define SVGA_SEQ_EXT_CONTROL_MMIO_HIGH (1 << 6)
126 /* MCLK register bits */
127 #define SVGA_SEQ_MCLK_VCLK (1 << 6)
138 SVGA_SEQ_EXT_MODE_REG
,
140 SVGA_SEQ_SCRATCH_0_REG
,
141 SVGA_SEQ_SCRATCH_1_REG
,
142 SVGA_SEQ_VCLK0_NUMERATOR_REG
,
143 SVGA_SEQ_VCLK1_NUMERATOR_REG
,
144 SVGA_SEQ_VCLK2_NUMERATOR_REG
,
145 SVGA_SEQ_VCLK3_NUMERATOR_REG
,
147 SVGA_SEQ_CURSOR_X_REG
,
148 SVGA_SEQ_CURSOR_Y_REG
,
149 SVGA_SEQ_CURSOR_ATTR_REG
,
150 SVGA_SEQ_CURSOR_PATTERN_REG
,
151 SVGA_SEQ_SCRATCH_2_REG
,
152 SVGA_SEQ_SCRATCH_3_REG
,
153 SVGA_SEQ_PERFORMANCE_REG
,
154 SVGA_SEQ_EXT_CONTROL_REG
,
155 SVGA_SEQ_SIG_GEN_CONTROL_REG
,
156 SVGA_SEQ_SIG_GEN_RESULT_LOW_REG
,
157 SVGA_SEQ_SIG_GEN_RESULT_HIGH_REG
,
158 SVGA_SEQ_VCLK0_DENOMINATOR_REG
,
159 SVGA_SEQ_VCLK1_DENOMINATOR_REG
,
160 SVGA_SEQ_VCLK2_DENOMINATOR_REG
,
161 SVGA_SEQ_VCLK3_DENOMINATOR_REG
,
167 // CRT Controller Registers
170 /* CRTC overflow register bits */
171 #define VGA_CRTC_OVERFLOW_VT8 (1 << 0)
172 #define VGA_CRTC_OVERFLOW_VDE8 (1 << 1)
173 #define VGA_CRTC_OVERFLOW_VRS8 (1 << 2)
174 #define VGA_CRTC_OVERFLOW_SVB8 (1 << 3)
175 #define VGA_CRTC_OVERFLOW_LC8 (1 << 4)
176 #define VGA_CRTC_OVERFLOW_VT9 (1 << 5)
177 #define VGA_CRTC_OVERFLOW_VDE9 (1 << 6)
178 #define VGA_CRTC_OVERFLOW_VRS9 (1 << 7)
180 /* CRTC underline register bits */
181 #define VGA_CRTC_UNDERLINE_DWORD (1 << 6)
183 /* CRTC max scanline register bits */
184 #define VGA_CRTC_MAXSCANLINE_DOUBLE (1 << 7)
186 /* CRTC mode control register bits */
187 #define VGA_CRTC_MODE_CONTROL_WRAP (1 << 5)
188 #define VGA_CRTC_MODE_CONTROL_BYTE (1 << 6)
189 #define VGA_CRTC_MODE_CONTROL_SYNC (1 << 7)
193 VGA_CRTC_HORZ_TOTAL_REG
,
194 VGA_CRTC_END_HORZ_DISP_REG
,
195 VGA_CRTC_START_HORZ_BLANKING_REG
,
196 VGA_CRTC_END_HORZ_BLANKING_REG
,
197 VGA_CRTC_START_HORZ_RETRACE_REG
,
198 VGA_CRTC_END_HORZ_RETRACE_REG
,
199 VGA_CRTC_VERT_TOTAL_REG
,
200 VGA_CRTC_OVERFLOW_REG
,
201 VGA_CRTC_PRESET_ROW_SCAN_REG
,
202 VGA_CRTC_MAX_SCAN_LINE_REG
,
203 VGA_CRTC_CURSOR_START_REG
,
204 VGA_CRTC_CURSOR_END_REG
,
205 VGA_CRTC_START_ADDR_HIGH_REG
,
206 VGA_CRTC_START_ADDR_LOW_REG
,
207 VGA_CRTC_CURSOR_LOC_HIGH_REG
,
208 VGA_CRTC_CURSOR_LOC_LOW_REG
,
209 VGA_CRTC_VERT_RETRACE_START_REG
,
210 VGA_CRTC_VERT_RETRACE_END_REG
,
211 VGA_CRTC_VERT_DISP_END_REG
,
213 VGA_CRTC_UNDERLINE_REG
,
214 VGA_CRTC_START_VERT_BLANKING_REG
,
215 VGA_CRTC_END_VERT_BLANKING_REG
,
216 VGA_CRTC_MODE_CONTROL_REG
,
217 VGA_CRTC_LINE_COMPARE_REG
,
219 SVGA_CRTC_INTERLACE_END_REG
= VGA_CRTC_MAX_REG
,
220 SVGA_CRTC_MISC_CONTROL_REG
,
221 SVGA_CRTC_EXT_DISPLAY_REG
,
222 SVGA_CRTC_SYNC_ADJUST_REG
,
223 SVGA_CRTC_OVERLAY_REG
,
224 SVGA_CRTC_UNUSED0_REG
,
225 SVGA_CRTC_UNUSED1_REG
,
226 SVGA_CRTC_UNUSED2_REG
,
227 SVGA_CRTC_UNUSED3_REG
,
228 SVGA_CRTC_UNUSED4_REG
,
229 SVGA_CRTC_UNUSED5_REG
,
230 SVGA_CRTC_UNUSED6_REG
,
231 SVGA_CRTC_PART_STATUS_REG
,
232 SVGA_CRTC_UNUSED7_REG
,
239 // Graphics Controller Registers
242 /* Graphics controller mode register bits */
243 #define VGA_GC_MODE_READ (1 << 3)
244 #define VGA_GC_MODE_OE (1 << 4)
245 #define VGA_GC_MODE_SHIFTREG (1 << 5)
246 #define VGA_GC_MODE_SHIFT256 (1 << 6)
248 /* Graphics controller miscellaneous register bits */
249 #define VGA_GC_MISC_NOALPHA (1 << 0)
250 #define VGA_GC_MISC_OE (1 << 1)
255 VGA_GC_ENABLE_RESET_REG
,
256 VGA_GC_COLOR_COMPARE_REG
,
258 VGA_GC_READ_MAP_SEL_REG
,
261 VGA_GC_COLOR_IGNORE_REG
,
264 SVGA_GC_OFFSET_0_REG
= VGA_GC_MAX_REG
,
265 SVGA_GC_OFFSET_1_REG
,
266 SVGA_GC_EXT_MODE_REG
,
267 SVGA_GC_COLOR_COMPARE_REG
,
269 SVGA_GC_POWER_MANAGEMENT_REG
,
271 SVGA_GC_BACKGROUND_1_REG
,
272 SVGA_GC_FOREGROUND_1_REG
,
273 SVGA_GC_BACKGROUND_2_REG
,
274 SVGA_GC_FOREGROUND_2_REG
,
275 SVGA_GC_BACKGROUND_3_REG
,
276 SVGA_GC_FOREGROUND_3_REG
,
286 SVGA_GC_UNUSED10_REG
,
287 SVGA_GC_BLT_WIDTH_LOW_REG
,
288 SVGA_GC_BLT_WIDTH_HIGH_REG
,
289 SVGA_GC_BLT_HEIGHT_LOW_REG
,
290 SVGA_GC_BLT_HEIGHT_HIGH_REG
,
291 SVGA_GC_BLT_DEST_PITCH_LOW_REG
,
292 SVGA_GC_BLT_DEST_PITCH_HIGH_REG
,
293 SVGA_GC_BLT_SRC_PITCH_LOW_REG
,
294 SVGA_GC_BLT_SRC_PITCH_HIGH_REG
,
295 SVGA_GC_BLT_DEST_START_0_REG
,
296 SVGA_GC_BLT_DEST_START_1_REG
,
297 SVGA_GC_BLT_DEST_START_2_REG
,
298 SVGA_GC_UNUSED11_REG
,
299 SVGA_GC_BLT_SRC_START_0_REG
,
300 SVGA_GC_BLT_SRC_START_1_REG
,
301 SVGA_GC_BLT_SRC_START_2_REG
,
302 SVGA_GC_BLT_DEST_MASK_REG
,
303 SVGA_GC_BLT_MODE_REG
,
304 SVGA_GC_BLT_STATUS_REG
,
306 SVGA_GC_BLT_EXT_MODE_REG
,
312 // Attribute Controller Registers
313 // They are a relinquish of the CGA/EGA era.
316 /* AC mode control register bits */
317 #define VGA_AC_CONTROL_ATGE (1 << 0)
318 #define VGA_AC_CONTROL_MONO (1 << 1)
319 #define VGA_AC_CONTROL_LGE (1 << 2)
320 #define VGA_AC_CONTROL_BLINK (1 << 3)
321 #define VGA_AC_CONTROL_PPM (1 << 5)
322 #define VGA_AC_CONTROL_8BIT (1 << 6)
323 #define VGA_AC_CONTROL_P54S (1 << 7)
345 VGA_AC_COLOR_PLANE_REG
,
346 VGA_AC_HORZ_PANNING_REG
,
347 VGA_AC_COLOR_SEL_REG
,
352 typedef struct _VGA_REGISTERS
355 UCHAR Sequencer
[VGA_SEQ_MAX_REG
];
356 UCHAR CRT
[VGA_CRTC_MAX_REG
];
357 UCHAR Graphics
[VGA_GC_MAX_REG
];
358 UCHAR Attribute
[VGA_AC_MAX_REG
];
359 } VGA_REGISTERS
, *PVGA_REGISTERS
;
361 typedef struct _SVGA_REGISTERS
365 UCHAR Sequencer
[SVGA_SEQ_MAX_REG
];
366 UCHAR CRT
[SVGA_CRTC_MAX_REG
];
367 UCHAR Graphics
[SVGA_GC_MAX_REG
];
368 UCHAR Attribute
[VGA_AC_MAX_REG
];
369 } SVGA_REGISTERS
, *PSVGA_REGISTERS
;
371 /* FUNCTIONS ******************************************************************/
373 VOID
ScreenEventHandler(PWINDOW_BUFFER_SIZE_RECORD ScreenEvent
);
374 BOOL
VgaAttachToConsole(VOID
);
375 VOID
VgaDetachFromConsole(VOID
);
377 COORD
VgaGetDisplayResolution(VOID
);
378 VOID
VgaRefreshDisplay(VOID
);
379 VOID FASTCALL
VgaReadMemory(ULONG Address
, PVOID Buffer
, ULONG Size
);
380 BOOLEAN FASTCALL
VgaWriteMemory(ULONG Address
, PVOID Buffer
, ULONG Size
);
381 VOID
VgaWriteTextModeFont(UINT FontNumber
, CONST UCHAR
*FontData
, UINT Height
);
382 VOID
VgaClearMemory(VOID
);
383 BOOLEAN
VgaGetDoubleVisionState(PBOOLEAN Horizontal
, PBOOLEAN Vertical
);
385 BOOLEAN
VgaInitialize(HANDLE TextHandle
);
386 VOID
VgaCleanup(VOID
);