[VGA/VGA_NEW]
[reactos.git] / reactos / win32ss / drivers / miniport / vga_new / vga.h
1 /*
2 * PROJECT: ReactOS VGA Miniport Driver
3 * LICENSE: Microsoft NT4 DDK Sample Code License
4 * FILE: boot/drivers/video/miniport/vga/vga.h
5 * PURPOSE: Main Header File
6 * PROGRAMMERS: Copyright (c) 1992 Microsoft Corporation
7 * ReactOS Portable Systems Group
8 */
9
10 #include "ntdef.h"
11 #include "dderror.h"
12 #include "devioctl.h"
13 #include "miniport.h"
14 #include "ntddvdeo.h"
15 #include "video.h"
16 #include "cmdcnst.h"
17
18 //
19 // Base address of VGA memory range. Also used as base address of VGA
20 // memory when loading a font, which is done with the VGA mapped at A0000.
21 //
22
23 #define MEM_VGA 0xA0000
24 #define MEM_VGA_SIZE 0x20000
25
26 //
27 // For memory mapped IO
28 //
29
30 #define MEMORY_MAPPED_IO_OFFSET (0xB8000 - 0xA0000)
31
32 //
33 // Port definitions for filling the ACCESS_RANGES structure in the miniport
34 // information, defines the range of I/O ports the VGA spans.
35 // There is a break in the IO ports - a few ports are used for the parallel
36 // port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
37 // so all VGA ports are in one address range.
38 //
39
40 #define VGA_BASE_IO_PORT 0x000003B0
41 #define VGA_START_BREAK_PORT 0x000003BB
42 #define VGA_END_BREAK_PORT 0x000003C0
43 #define VGA_MAX_IO_PORT 0x000003DF
44
45 //
46 // VGA register definitions
47 //
48 // eVb: 3.1 [VGA] - Use offsets from the VGA Port Address instead of absolute
49 #define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and
50 #define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode
51 #define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port
52 // in mono mode
53 #define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read
54 // port in mono mode
55 #define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
56 // Register to read to reset
57 // Attribute Controller index/data
58
59 #define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and
60 #define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port
61 // for writes, but only Address is
62 // readable at 0x3C0
63 #define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is
64 // readable here
65 #define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write
66 // port
67 #define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read
68 // port
69 #define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the
70 // entire VGA subsystem
71 #define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and
72 #define SEQ_DATA_PORT 0x0015 // Data registers
73 #define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg
74 #define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg,
75 // write-only
76 #define DAC_STATE_PORT 0x0017 // DAC state (read/write),
77 // read-only
78 #define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg
79 #define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg
80 #define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port
81 #define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read
82 // port
83 #define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address
84 #define GRAPH_DATA_PORT 0x001F // and Data registers
85
86 #define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and
87 #define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode
88 #define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port
89 #define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read
90 // port in color mode
91 // eVb: 3.2 [END]
92 #define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
93 // Register to read to reset
94 // Attribute Controller index/data
95 // toggle in color mode
96
97 //
98 // Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
99 // VGA registers.
100 //
101
102 #define CRTC_ADDRESS_MONO_OFFSET 0x04
103 #define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
104 #define ATT_ADDRESS_OFFSET 0x10
105 #define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
106 #define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
107 #define SEQ_ADDRESS_OFFSET 0x14
108 #define DAC_PIXEL_MASK_OFFSET 0x16
109 #define DAC_STATE_OFFSET 0x17
110 #define DAC_ADDRESS_WRITE_OFFSET 0x18
111 #define GRAPH_ADDRESS_OFFSET 0x1E
112 #define CRTC_ADDRESS_COLOR_OFFSET 0x24
113 #define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
114
115 // toggle in color mode
116 //
117 // VGA indexed register indexes.
118 //
119
120 // CL-GD542x specific registers:
121 //
122 #define IND_CL_EXTS_ENB 0x06 // index in Sequencer to enable exts
123 #define IND_NORD_SCRATCH_PAD 0x09 // index in Seq of Nordic scratch pad
124 #define IND_CL_SCRATCH_PAD 0x0A // index in Seq of 542x scratch pad
125 #define IND_ALP_SCRATCH_PAD 0x15 // index in Seq of Alpine scratch pad
126 #define IND_CL_REV_REG 0x25 // index in CRTC of ID Register
127 #define IND_CL_ID_REG 0x27 // index in CRTC of ID Register
128 //
129 #define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
130 #define IND_CURSOR_END 0x0B // and End registers
131 #define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
132 #define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
133 #define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
134 // End register, which has the bit
135 // that protects/unprotects CRTC
136 // index registers 0-7
137 #define IND_CR2C 0x2C // Nordic LCD Interface Register
138 #define IND_CR2D 0x2D // Nordic LCD Display Control
139 #define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
140 #define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
141 #define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
142 #define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
143 #define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
144 #define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
145 #define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
146 #define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
147 #define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
148 #define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
149 // CRTC
150 #define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg
151 // in CRTC
152 #define IND_PERF_TUNING 0x16 // index of performance tuning in Seq
153 #define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
154 // synchronous reset
155 #define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
156 // synchronous reset
157
158 //
159 // Value to write to Extensions Control register values extensions.
160 //
161
162 #define CL64xx_EXTENSION_ENABLE_INDEX 0x0A // GR0A to be exact!
163 #define CL64xx_EXTENSION_ENABLE_VALUE 0xEC
164 #define CL64xx_EXTENSION_DISABLE_VALUE 0xCE
165 #define CL64xx_TRISTATE_CONTROL_REG 0xA1
166
167 #define CL6340_ENABLE_READBACK_REGISTER 0xE0
168 #define CL6340_ENABLE_READBACK_ALLSEL_VALUE 0xF0
169 #define CL6340_ENABLE_READBACK_OFF_VALUE 0x00
170 #define CL6340_IDENTIFICATION_REGISTER 0xE9
171 //
172 // Values for Attribute Controller Index register to turn video off
173 // and on, by setting bit 5 to 0 (off) or 1 (on).
174 //
175
176 #define VIDEO_DISABLE 0
177 #define VIDEO_ENABLE 0x20
178
179 #define INDEX_ENABLE_AUTO_START 0x31
180
181 // Masks to keep only the significant bits of the Graphics Controller and
182 // Sequencer Address registers. Masking is necessary because some VGAs, such
183 // as S3-based ones, don't return unused bits set to 0, and some SVGAs use
184 // these bits if extensions are enabled.
185 //
186
187 #define GRAPH_ADDR_MASK 0x0F
188 #define SEQ_ADDR_MASK 0x07
189
190 //
191 // Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
192 //
193
194 #define CHAIN4_MASK 0x08
195
196 //
197 // Value written to the Read Map register when identifying the existence of
198 // a VGA in VgaInitialize. This value must be different from the final test
199 // value written to the Bit Mask in that routine.
200 //
201
202 #define READ_MAP_TEST_SETTING 0x03
203
204 //
205 // Default text mode setting for various registers, used to restore their
206 // states if VGA detection fails after they've been modified.
207 //
208
209 #define MEMORY_MODE_TEXT_DEFAULT 0x02
210 #define BIT_MASK_DEFAULT 0xFF
211 #define READ_MAP_DEFAULT 0x00
212
213 \f
214 //
215 // Palette-related info.
216 //
217
218 //
219 // Highest valid DAC color register index.
220 //
221
222 #define VIDEO_MAX_COLOR_REGISTER 0xFF
223
224 //
225 // Highest valid palette register index
226 //
227
228 #define VIDEO_MAX_PALETTE_REGISTER 0x0F
229
230 //
231 // Driver Specific Attribute Flags
232 //
233
234 #define CAPS_NO_HOST_XFER 0x00000002 // Do not use host xfers to
235 // the blt engine.
236 #define CAPS_SW_POINTER 0x00000004 // Use software pointer.
237 #define CAPS_TRUE_COLOR 0x00000008 // Set upper color registers.
238 #define CAPS_MM_IO 0x00000010 // Use memory mapped IO.
239 #define CAPS_BLT_SUPPORT 0x00000020 // BLTs are supported
240 #define CAPS_IS_542x 0x00000040 // This is a 542x
241 #define CAPS_IS_5436 0x00000080 // This is a 5436
242 #define CAPS_CURSOR_VERT_EXP 0x00000100 // Flag set if 8x6 panel,
243 // but 6x4 resolution
244
245 //
246 // Structure used to describe each video mode in ModesVGA[].
247 //
248
249 typedef struct {
250 USHORT fbType; // color or monochrome, text or graphics, via
251 // VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
252 USHORT numPlanes; // # of video memory planes
253 USHORT bitsPerPlane; // # of bits of color in each plane
254 SHORT col; // # of text columns across screen with default font
255 SHORT row; // # of text rows down screen with default font
256 USHORT hres; // # of pixels across screen
257 USHORT vres; // # of scan lines down screen
258 // eVb: 3.2 [VGA] - Store frequency next to resolution data
259 ULONG Frequency; // Vertical Frequency
260 // eVb: 3.2 [END]
261 USHORT wbytes; // # of bytes from start of one scan line to start of next
262 ULONG sbytes; // total size of addressable display memory in bytes
263 // eVb: 3.3 [VBE] - Add VBE mode and bank flag
264 ULONG NoBankSwitch;
265 ULONG Mode;
266 // eVb: 3.3 [VBE]
267 PUSHORT CmdStream; // pointer to array of register-setting commands to
268 // set up mode
269 // eVb: 3.4 [VBE] - Add fields to track linear addresses/sizes and flags
270 ULONG PhysBase;
271 ULONG FrameBufferBase;
272 ULONG FrameBufferSize;
273 ULONG PhysSize;
274 ULONG LogicalWidth;
275 ULONG NonVgaMode;
276 ULONG Granularity;
277 // eVb: 3.4 [END]
278 } VIDEOMODE, *PVIDEOMODE;
279
280 //
281 // Mode into which to put the VGA before starting a VDM, so it's a plain
282 // vanilla VGA. (This is the mode's index in ModesVGA[], currently standard
283 // 80x25 text mode.)
284 //
285
286 #define DEFAULT_MODE 0
287
288 \f
289 //
290 // Info used by the Validator functions and save/restore code.
291 // Structure used to trap register accesses that must be done atomically.
292 //
293
294 #define VGA_MAX_VALIDATOR_DATA 100
295
296 #define VGA_VALIDATOR_UCHAR_ACCESS 1
297 #define VGA_VALIDATOR_USHORT_ACCESS 2
298 #define VGA_VALIDATOR_ULONG_ACCESS 3
299
300 typedef struct _VGA_VALIDATOR_DATA {
301 ULONG Port;
302 UCHAR AccessType;
303 ULONG Data;
304 } VGA_VALIDATOR_DATA, *PVGA_VALIDATOR_DATA;
305
306 //
307 // Number of bytes to save in each plane.
308 //
309
310 #define VGA_PLANE_SIZE 0x10000
311
312 //
313 // Number of each type of indexed register in a standard VGA, used by
314 // validator and state save/restore functions.
315 //
316 // Note: VDMs currently only support basic VGAs only.
317 //
318
319 #define VGA_NUM_SEQUENCER_PORTS 5
320 #define VGA_NUM_CRTC_PORTS 25
321 #define VGA_NUM_GRAPH_CONT_PORTS 9
322 #define VGA_NUM_ATTRIB_CONT_PORTS 21
323 #define VGA_NUM_DAC_ENTRIES 256
324
325 #define EXT_NUM_GRAPH_CONT_PORTS 0
326 #define EXT_NUM_SEQUENCER_PORTS 0
327 #define EXT_NUM_CRTC_PORTS 0
328 #define EXT_NUM_ATTRIB_CONT_PORTS 0
329 #define EXT_NUM_DAC_ENTRIES 0
330
331 //
332 // These constants determine the offsets within the
333 // VIDEO_HARDWARE_STATE_HEADER structure that are used to save and
334 // restore the VGA's state.
335 //
336
337 #define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER)
338
339 #define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0)
340 #define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \
341 VGA_NUM_SEQUENCER_PORTS)
342 #define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \
343 VGA_NUM_CRTC_PORTS)
344 #define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \
345 VGA_NUM_GRAPH_CONT_PORTS)
346 #define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \
347 VGA_NUM_ATTRIB_CONT_PORTS)
348 #define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \
349 (3 * VGA_NUM_DAC_ENTRIES))
350
351 #define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4)
352 #define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \
353 EXT_NUM_SEQUENCER_PORTS)
354 #define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \
355 EXT_NUM_CRTC_PORTS)
356 #define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET +\
357 EXT_NUM_GRAPH_CONT_PORTS)
358 #define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \
359 EXT_NUM_ATTRIB_CONT_PORTS)
360
361 #define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES)
362
363 #define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \
364 sizeof (VGA_VALIDATOR_DATA)) + \
365 sizeof (ULONG) + \
366 sizeof (ULONG) + \
367 sizeof (PVIDEO_ACCESS_RANGE)
368
369 #define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE
370
371 #define VGA_MISC_DATA_AREA_SIZE 0
372
373 #define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE
374
375 #define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE
376 #define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE
377 #define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE
378
379 //
380 // Space needed to store all state data.
381 //
382
383 #define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE
384
385 \f
386 //
387 // Device extension for the driver object. This data is only used
388 // locally, so this structure can be added to as needed.
389 //
390
391 typedef struct _HW_DEVICE_EXTENSION {
392
393 PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and
394 PHYSICAL_ADDRESS PhysicalFrameOffset; // physical memory address and
395 ULONG PhysicalVideoMemoryLength; // length of display memory
396 ULONG PhysicalFrameLength; // length of display memory for
397 // the current mode.
398
399 PUCHAR IOAddress; // base I/O address of VGA ports
400 PUCHAR VideoMemoryAddress; // base virtual memory address of VGA memory
401 ULONG ModeIndex; // index of current mode in ModesVGA[]
402 PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for
403 // current mode
404
405 VIDEO_CURSOR_POSITION CursorPosition; // current cursor position
406
407 UCHAR CursorEnable; // whether cursor is enabled or not
408 UCHAR CursorTopScanLine; // Cursor Start register setting (top scan)
409 UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan)
410 // eVb: 3.5 [VBE] - Add fields for VBE support and XP+ INT10 interface
411 VIDEO_PORT_INT10_INTERFACE Int10Interface;
412 BOOLEAN VesaBiosOk;
413 // eVb: 3.5 [END]
414 } HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
415
416 \f
417 //
418 // Function prototypes.
419 //
420
421 //
422 // Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[].
423 //
424
425
426 //
427 // Vga init scripts for font loading
428 //
429
430 extern USHORT EnableA000Data[];
431 extern USHORT DisableA000Color[];
432
433 //
434 // Mode Information
435 //
436
437 extern ULONG NumVideoModes;
438 extern VIDEOMODE ModesVGA[];
439 extern PVIDEOMODE VgaModeList;
440
441 // eVb: 3.5 [VGA] - Add ATI/Mach64 Access Range
442 #define NUM_VGA_ACCESS_RANGES 5
443 // eVb: 3.5 [END]
444 extern VIDEO_ACCESS_RANGE VgaAccessRange[];
445
446 /* VESA Bios Magic number */
447 #define VESA_MAGIC ('V' + ('E' << 8) + ('S' << 16) + ('A' << 24))
448
449 #include "vbe.h"