[VGA]
[reactos.git] / reactos / win32ss / drivers / miniport / vga_new / vga.h
1 /*
2 * PROJECT: ReactOS VGA Miniport Driver
3 * LICENSE: Microsoft NT4 DDK Sample Code License
4 * FILE: boot/drivers/video/miniport/vga/vga.h
5 * PURPOSE: Main Header File
6 * PROGRAMMERS: Copyright (c) 1992 Microsoft Corporation
7 * ReactOS Portable Systems Group
8 */
9
10 #include <ntdef.h>
11 #include <dderror.h>
12 #include <miniport.h>
13 #include <video.h>
14
15 #include "cmdcnst.h"
16
17 //
18 // Base address of VGA memory range. Also used as base address of VGA
19 // memory when loading a font, which is done with the VGA mapped at A0000.
20 //
21
22 #define MEM_VGA 0xA0000
23 #define MEM_VGA_SIZE 0x20000
24
25 //
26 // For memory mapped IO
27 //
28
29 #define MEMORY_MAPPED_IO_OFFSET (0xB8000 - 0xA0000)
30
31 //
32 // Port definitions for filling the ACCESS_RANGES structure in the miniport
33 // information, defines the range of I/O ports the VGA spans.
34 // There is a break in the IO ports - a few ports are used for the parallel
35 // port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
36 // so all VGA ports are in one address range.
37 //
38
39 #define VGA_BASE_IO_PORT 0x000003B0
40 #define VGA_START_BREAK_PORT 0x000003BB
41 #define VGA_END_BREAK_PORT 0x000003C0
42 #define VGA_MAX_IO_PORT 0x000003DF
43
44 //
45 // VGA register definitions
46 //
47 // eVb: 3.1 [VGA] - Use offsets from the VGA Port Address instead of absolute
48 #define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and
49 #define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode
50 #define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port
51 // in mono mode
52 #define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read
53 // port in mono mode
54 #define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
55 // Register to read to reset
56 // Attribute Controller index/data
57
58 #define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and
59 #define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port
60 // for writes, but only Address is
61 // readable at 0x3C0
62 #define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is
63 // readable here
64 #define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write
65 // port
66 #define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read
67 // port
68 #define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the
69 // entire VGA subsystem
70 #define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and
71 #define SEQ_DATA_PORT 0x0015 // Data registers
72 #define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg
73 #define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg,
74 // write-only
75 #define DAC_STATE_PORT 0x0017 // DAC state (read/write),
76 // read-only
77 #define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg
78 #define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg
79 #define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port
80 #define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read
81 // port
82 #define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address
83 #define GRAPH_DATA_PORT 0x001F // and Data registers
84
85 #define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and
86 #define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode
87 #define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port
88 #define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read
89 // port in color mode
90 // eVb: 3.2 [END]
91 #define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
92 // Register to read to reset
93 // Attribute Controller index/data
94 // toggle in color mode
95
96 //
97 // Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
98 // VGA registers.
99 //
100
101 #define CRTC_ADDRESS_MONO_OFFSET 0x04
102 #define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
103 #define ATT_ADDRESS_OFFSET 0x10
104 #define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
105 #define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
106 #define SEQ_ADDRESS_OFFSET 0x14
107 #define DAC_PIXEL_MASK_OFFSET 0x16
108 #define DAC_STATE_OFFSET 0x17
109 #define DAC_ADDRESS_WRITE_OFFSET 0x18
110 #define GRAPH_ADDRESS_OFFSET 0x1E
111 #define CRTC_ADDRESS_COLOR_OFFSET 0x24
112 #define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
113
114 // toggle in color mode
115 //
116 // VGA indexed register indexes.
117 //
118
119 // CL-GD542x specific registers:
120 //
121 #define IND_CL_EXTS_ENB 0x06 // index in Sequencer to enable exts
122 #define IND_NORD_SCRATCH_PAD 0x09 // index in Seq of Nordic scratch pad
123 #define IND_CL_SCRATCH_PAD 0x0A // index in Seq of 542x scratch pad
124 #define IND_ALP_SCRATCH_PAD 0x15 // index in Seq of Alpine scratch pad
125 #define IND_CL_REV_REG 0x25 // index in CRTC of ID Register
126 #define IND_CL_ID_REG 0x27 // index in CRTC of ID Register
127 //
128 #define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
129 #define IND_CURSOR_END 0x0B // and End registers
130 #define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
131 #define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
132 #define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
133 // End register, which has the bit
134 // that protects/unprotects CRTC
135 // index registers 0-7
136 #define IND_CR2C 0x2C // Nordic LCD Interface Register
137 #define IND_CR2D 0x2D // Nordic LCD Display Control
138 #define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
139 #define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
140 #define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
141 #define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
142 #define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
143 #define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
144 #define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
145 #define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
146 #define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
147 #define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
148 // CRTC
149 #define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg
150 // in CRTC
151 #define IND_PERF_TUNING 0x16 // index of performance tuning in Seq
152 #define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
153 // synchronous reset
154 #define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
155 // synchronous reset
156
157 //
158 // Value to write to Extensions Control register values extensions.
159 //
160
161 #define CL64xx_EXTENSION_ENABLE_INDEX 0x0A // GR0A to be exact!
162 #define CL64xx_EXTENSION_ENABLE_VALUE 0xEC
163 #define CL64xx_EXTENSION_DISABLE_VALUE 0xCE
164 #define CL64xx_TRISTATE_CONTROL_REG 0xA1
165
166 #define CL6340_ENABLE_READBACK_REGISTER 0xE0
167 #define CL6340_ENABLE_READBACK_ALLSEL_VALUE 0xF0
168 #define CL6340_ENABLE_READBACK_OFF_VALUE 0x00
169 #define CL6340_IDENTIFICATION_REGISTER 0xE9
170 //
171 // Values for Attribute Controller Index register to turn video off
172 // and on, by setting bit 5 to 0 (off) or 1 (on).
173 //
174
175 #define VIDEO_DISABLE 0
176 #define VIDEO_ENABLE 0x20
177
178 #define INDEX_ENABLE_AUTO_START 0x31
179
180 // Masks to keep only the significant bits of the Graphics Controller and
181 // Sequencer Address registers. Masking is necessary because some VGAs, such
182 // as S3-based ones, don't return unused bits set to 0, and some SVGAs use
183 // these bits if extensions are enabled.
184 //
185
186 #define GRAPH_ADDR_MASK 0x0F
187 #define SEQ_ADDR_MASK 0x07
188
189 //
190 // Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
191 //
192
193 #define CHAIN4_MASK 0x08
194
195 //
196 // Value written to the Read Map register when identifying the existence of
197 // a VGA in VgaInitialize. This value must be different from the final test
198 // value written to the Bit Mask in that routine.
199 //
200
201 #define READ_MAP_TEST_SETTING 0x03
202
203 //
204 // Default text mode setting for various registers, used to restore their
205 // states if VGA detection fails after they've been modified.
206 //
207
208 #define MEMORY_MODE_TEXT_DEFAULT 0x02
209 #define BIT_MASK_DEFAULT 0xFF
210 #define READ_MAP_DEFAULT 0x00
211
212 \f
213 //
214 // Palette-related info.
215 //
216
217 //
218 // Highest valid DAC color register index.
219 //
220
221 #define VIDEO_MAX_COLOR_REGISTER 0xFF
222
223 //
224 // Highest valid palette register index
225 //
226
227 #define VIDEO_MAX_PALETTE_REGISTER 0x0F
228
229 //
230 // Driver Specific Attribute Flags
231 //
232
233 #define CAPS_NO_HOST_XFER 0x00000002 // Do not use host xfers to
234 // the blt engine.
235 #define CAPS_SW_POINTER 0x00000004 // Use software pointer.
236 #define CAPS_TRUE_COLOR 0x00000008 // Set upper color registers.
237 #define CAPS_MM_IO 0x00000010 // Use memory mapped IO.
238 #define CAPS_BLT_SUPPORT 0x00000020 // BLTs are supported
239 #define CAPS_IS_542x 0x00000040 // This is a 542x
240 #define CAPS_IS_5436 0x00000080 // This is a 5436
241 #define CAPS_CURSOR_VERT_EXP 0x00000100 // Flag set if 8x6 panel,
242 // but 6x4 resolution
243
244 //
245 // Structure used to describe each video mode in ModesVGA[].
246 //
247
248 typedef struct {
249 USHORT fbType; // color or monochrome, text or graphics, via
250 // VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
251 USHORT numPlanes; // # of video memory planes
252 USHORT bitsPerPlane; // # of bits of color in each plane
253 SHORT col; // # of text columns across screen with default font
254 SHORT row; // # of text rows down screen with default font
255 USHORT hres; // # of pixels across screen
256 USHORT vres; // # of scan lines down screen
257 // eVb: 3.2 [VGA] - Store frequency next to resolution data
258 ULONG Frequency; // Vertical Frequency
259 // eVb: 3.2 [END]
260 USHORT wbytes; // # of bytes from start of one scan line to start of next
261 ULONG sbytes; // total size of addressable display memory in bytes
262 // eVb: 3.3 [VBE] - Add VBE mode and bank flag
263 ULONG NoBankSwitch;
264 ULONG Mode;
265 // eVb: 3.3 [VBE]
266 PUSHORT CmdStream; // pointer to array of register-setting commands to
267 // set up mode
268 // eVb: 3.4 [VBE] - Add fields to track linear addresses/sizes and flags
269 ULONG PhysBase;
270 ULONG FrameBufferBase;
271 ULONG FrameBufferSize;
272 ULONG PhysSize;
273 ULONG LogicalWidth;
274 ULONG NonVgaMode;
275 ULONG Granularity;
276 // eVb: 3.4 [END]
277 } VIDEOMODE, *PVIDEOMODE;
278
279 //
280 // Mode into which to put the VGA before starting a VDM, so it's a plain
281 // vanilla VGA. (This is the mode's index in ModesVGA[], currently standard
282 // 80x25 text mode.)
283 //
284
285 #define DEFAULT_MODE 0
286
287 \f
288 //
289 // Info used by the Validator functions and save/restore code.
290 // Structure used to trap register accesses that must be done atomically.
291 //
292
293 #define VGA_MAX_VALIDATOR_DATA 100
294
295 #define VGA_VALIDATOR_UCHAR_ACCESS 1
296 #define VGA_VALIDATOR_USHORT_ACCESS 2
297 #define VGA_VALIDATOR_ULONG_ACCESS 3
298
299 typedef struct _VGA_VALIDATOR_DATA {
300 ULONG Port;
301 UCHAR AccessType;
302 ULONG Data;
303 } VGA_VALIDATOR_DATA, *PVGA_VALIDATOR_DATA;
304
305 //
306 // Number of bytes to save in each plane.
307 //
308
309 #define VGA_PLANE_SIZE 0x10000
310
311 //
312 // Number of each type of indexed register in a standard VGA, used by
313 // validator and state save/restore functions.
314 //
315 // Note: VDMs currently only support basic VGAs only.
316 //
317
318 #define VGA_NUM_SEQUENCER_PORTS 5
319 #define VGA_NUM_CRTC_PORTS 25
320 #define VGA_NUM_GRAPH_CONT_PORTS 9
321 #define VGA_NUM_ATTRIB_CONT_PORTS 21
322 #define VGA_NUM_DAC_ENTRIES 256
323
324 #define EXT_NUM_GRAPH_CONT_PORTS 0
325 #define EXT_NUM_SEQUENCER_PORTS 0
326 #define EXT_NUM_CRTC_PORTS 0
327 #define EXT_NUM_ATTRIB_CONT_PORTS 0
328 #define EXT_NUM_DAC_ENTRIES 0
329
330 //
331 // These constants determine the offsets within the
332 // VIDEO_HARDWARE_STATE_HEADER structure that are used to save and
333 // restore the VGA's state.
334 //
335
336 #define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER)
337
338 #define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0)
339 #define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \
340 VGA_NUM_SEQUENCER_PORTS)
341 #define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \
342 VGA_NUM_CRTC_PORTS)
343 #define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \
344 VGA_NUM_GRAPH_CONT_PORTS)
345 #define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \
346 VGA_NUM_ATTRIB_CONT_PORTS)
347 #define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \
348 (3 * VGA_NUM_DAC_ENTRIES))
349
350 #define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4)
351 #define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \
352 EXT_NUM_SEQUENCER_PORTS)
353 #define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \
354 EXT_NUM_CRTC_PORTS)
355 #define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET +\
356 EXT_NUM_GRAPH_CONT_PORTS)
357 #define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \
358 EXT_NUM_ATTRIB_CONT_PORTS)
359
360 #define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES)
361
362 #define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \
363 sizeof (VGA_VALIDATOR_DATA)) + \
364 sizeof (ULONG) + \
365 sizeof (ULONG) + \
366 sizeof (PVIDEO_ACCESS_RANGE)
367
368 #define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE
369
370 #define VGA_MISC_DATA_AREA_SIZE 0
371
372 #define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE
373
374 #define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE
375 #define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE
376 #define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE
377
378 //
379 // Space needed to store all state data.
380 //
381
382 #define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE
383
384 \f
385 //
386 // Device extension for the driver object. This data is only used
387 // locally, so this structure can be added to as needed.
388 //
389
390 typedef struct _HW_DEVICE_EXTENSION {
391
392 PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and
393 PHYSICAL_ADDRESS PhysicalFrameOffset; // physical memory address and
394 ULONG PhysicalVideoMemoryLength; // length of display memory
395 ULONG PhysicalFrameLength; // length of display memory for
396 // the current mode.
397
398 PUCHAR IOAddress; // base I/O address of VGA ports
399 PUCHAR VideoMemoryAddress; // base virtual memory address of VGA memory
400 ULONG ModeIndex; // index of current mode in ModesVGA[]
401 PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for
402 // current mode
403
404 VIDEO_CURSOR_POSITION CursorPosition; // current cursor position
405
406 UCHAR CursorEnable; // whether cursor is enabled or not
407 UCHAR CursorTopScanLine; // Cursor Start register setting (top scan)
408 UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan)
409 // eVb: 3.5 [VBE] - Add fields for VBE support and XP+ INT10 interface
410 VIDEO_PORT_INT10_INTERFACE Int10Interface;
411 BOOLEAN VesaBiosOk;
412 // eVb: 3.5 [END]
413 } HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
414
415 \f
416 //
417 // Function prototypes.
418 //
419
420 //
421 // Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[].
422 //
423
424
425 //
426 // Vga init scripts for font loading
427 //
428
429 extern USHORT EnableA000Data[];
430 extern USHORT DisableA000Color[];
431
432 //
433 // Mode Information
434 //
435
436 extern ULONG NumVideoModes;
437 extern VIDEOMODE ModesVGA[];
438 extern PVIDEOMODE VgaModeList;
439
440 // eVb: 3.5 [VGA] - Add ATI/Mach64 Access Range
441 #define NUM_VGA_ACCESS_RANGES 5
442 // eVb: 3.5 [END]
443 extern VIDEO_ACCESS_RANGE VgaAccessRange[];
444
445 /* VESA Bios Magic number */
446 #define VESA_MAGIC ('V' + ('E' << 8) + ('S' << 16) + ('A' << 24))
447
448 #include "vbe.h"