6 * This file is part of the w32api package.
9 * Created by Hervé Poussineau <hpoussin@reactos.org>
11 * THIS SOFTWARE IS NOT COPYRIGHTED
13 * This source code is offered for use in the public domain. You may
14 * use, modify or distribute it freely.
16 * This code is distributed in the hope that it will be useful but
17 * WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY
18 * DISCLAIMED. This includes but is not limited to warranties of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
30 #define MAX_IDE_CHANNEL 2
31 #define MAX_IDE_LINE 2
32 #define MAX_IDE_DEVICE 2
35 typedef struct _IDENTIFY_DATA
{
36 USHORT GeneralConfiguration
; /* 00 */
37 USHORT NumCylinders
; /* 02 */
38 USHORT Reserved1
; /* 04 */
39 USHORT NumHeads
; /* 06 */
40 USHORT UnformattedBytesPerTrack
; /* 08 */
41 USHORT UnformattedBytesPerSector
; /* 10 */
42 USHORT NumSectorsPerTrack
; /* 12 */
43 USHORT VendorUnique1
[3]; /* 14 */
44 UCHAR SerialNumber
[20]; /* 20 */
45 USHORT BufferType
; /* 40 */
46 USHORT BufferSectorSize
; /* 42 */
47 USHORT NumberOfEccBytes
; /* 44 */
48 UCHAR FirmwareRevision
[8]; /* 46 */
49 UCHAR ModelNumber
[40]; /* 54 */
50 UCHAR MaximumBlockTransfer
; /* 94 */
51 UCHAR VendorUnique2
; /* 95 */
52 USHORT DoubleWordIo
; /* 96 */
53 USHORT Capabilities
; /* 98 */
54 USHORT Reserved2
; /* 100 */
55 UCHAR VendorUnique3
; /* 102 */
56 UCHAR PioCycleTimingMode
; /* 103 */
57 UCHAR VendorUnique4
; /* 104 */
58 UCHAR DmaCycleTimingMode
; /* 105 */
59 USHORT TranslationFieldsValid
:3; /* 106 */
60 USHORT Reserved3
:13; /* - */
61 USHORT NumberOfCurrentCylinders
; /* 108 */
62 USHORT NumberOfCurrentHeads
; /* 110 */
63 USHORT CurrentSectorsPerTrack
; /* 112 */
64 ULONG CurrentSectorCapacity
; /* 114 */
65 USHORT CurrentMultiSectorSetting
; /* 118 */
66 ULONG UserAddressableSectors
; /* 120 */
67 USHORT SingleWordDMASupport
:8; /* 124 */
68 USHORT SingleWordDMAActive
:8; /* - */
69 USHORT MultiWordDMASupport
:8; /* 126 */
70 USHORT MultiWordDMAActive
:8; /* - */
71 USHORT AdvancedPIOModes
:8; /* 128 */
72 USHORT Reserved4
:8; /* - */
73 USHORT MinimumMWXferCycleTime
; /* 130 */
74 USHORT RecommendedMWXferCycleTime
; /* 132 */
75 USHORT MinimumPIOCycleTime
; /* 134 */
76 USHORT MinimumPIOCycleTimeIORDY
; /* 136 */
77 USHORT Reserved5
[11]; /* 138 */
78 USHORT MajorRevision
; /* 160 */
79 USHORT MinorRevision
; /* 162 */
80 USHORT Reserved6
; /* 164 */
81 USHORT CommandSetSupport
; /* 166 */
82 USHORT Reserved6a
[2]; /* 168 */
83 USHORT CommandSetActive
; /* 172 */
84 USHORT Reserved6b
; /* 174 */
85 USHORT UltraDMASupport
:8; /* 176 */
86 USHORT UltraDMAActive
:8; /* - */
87 USHORT Reserved7
[11]; /* 178 */
88 ULONG Max48BitLBA
[2]; /* 200 */
89 USHORT Reserved7a
[22]; /* 208 */
90 USHORT LastLun
:3; /* 252 */
91 USHORT Reserved8
:13; /* - */
92 USHORT MediaStatusNotification
:2; /* 254 */
93 USHORT Reserved9
:6; /* - */
94 USHORT DeviceWriteProtect
:1; /* - */
95 USHORT Reserved10
:7; /* - */
96 USHORT Reserved11
[128]; /* 256 */
97 } IDENTIFY_DATA
, *PIDENTIFY_DATA
;
99 typedef struct _EXTENDED_IDENTIFY_DATA
{
100 USHORT GeneralConfiguration
; /* 00 */
101 USHORT NumCylinders
; /* 02 */
102 USHORT Reserved1
; /* 04 */
103 USHORT NumHeads
; /* 06 */
104 USHORT UnformattedBytesPerTrack
; /* 08 */
105 USHORT UnformattedBytesPerSector
; /* 10 */
106 USHORT NumSectorsPerTrack
; /* 12 */
107 __GNU_EXTENSION
union
109 USHORT VendorUnique1
[3]; /* 14 */
112 UCHAR InterSectorGap
; /* 14 */
113 UCHAR InterSectorGapSize
; /* - */
114 UCHAR Reserved16
; /* 16 */
115 UCHAR BytesInPLO
; /* - */
116 USHORT VendorUniqueCnt
; /* 18 */
119 UCHAR SerialNumber
[20]; /* 20 */
120 USHORT BufferType
; /* 40 */
121 USHORT BufferSectorSize
; /* 42 */
122 USHORT NumberOfEccBytes
; /* 44 */
123 UCHAR FirmwareRevision
[8]; /* 46 */
124 UCHAR ModelNumber
[40]; /* 54 */
125 UCHAR MaximumBlockTransfer
; /* 94 */
126 UCHAR VendorUnique2
; /* 95 */
127 USHORT DoubleWordIo
; /* 96 */
128 USHORT Capabilities
; /* 98 */
129 USHORT Reserved2
; /* 100 */
130 UCHAR VendorUnique3
; /* 102 */
131 UCHAR PioCycleTimingMode
; /* 103 */
132 UCHAR VendorUnique4
; /* 104 */
133 UCHAR DmaCycleTimingMode
; /* 105 */
134 USHORT TranslationFieldsValid
:3; /* 106 */
135 USHORT Reserved3
:13; /* - */
136 USHORT NumberOfCurrentCylinders
; /* 108 */
137 USHORT NumberOfCurrentHeads
; /* 110 */
138 USHORT CurrentSectorsPerTrack
; /* 112 */
139 ULONG CurrentSectorCapacity
; /* 114 */
140 USHORT CurrentMultiSectorSetting
; /* 118 */
141 ULONG UserAddressableSectors
; /* 120 */
142 USHORT SingleWordDMASupport
:8; /* 124 */
143 USHORT SingleWordDMAActive
:8; /* - */
144 USHORT MultiWordDMASupport
:8; /* 126 */
145 USHORT MultiWordDMAActive
:8; /* - */
146 USHORT AdvancedPIOModes
:8; /* 128 */
147 USHORT Reserved4
:8; /* - */
148 USHORT MinimumMWXferCycleTime
; /* 130 */
149 USHORT RecommendedMWXferCycleTime
; /* 132 */
150 USHORT MinimumPIOCycleTime
; /* 134 */
151 USHORT MinimumPIOCycleTimeIORDY
; /* 136 */
152 USHORT Reserved5
[11]; /* 138 */
153 USHORT MajorRevision
; /* 160 */
154 USHORT MinorRevision
; /* 162 */
155 USHORT Reserved6
; /* 164 */
156 USHORT CommandSetSupport
; /* 166 */
157 USHORT Reserved6a
[2]; /* 168 */
158 USHORT CommandSetActive
; /* 172 */
159 USHORT Reserved6b
; /* 174 */
160 USHORT UltraDMASupport
:8; /* 176 */
161 USHORT UltraDMAActive
:8; /* - */
162 USHORT Reserved7
[11]; /* 178 */
163 ULONG Max48BitLBA
[2]; /* 200 */
164 USHORT Reserved7a
[22]; /* 208 */
165 USHORT LastLun
:3; /* 252 */
166 USHORT Reserved8
:13; /* - */
167 USHORT MediaStatusNotification
:2; /* 254 */
168 USHORT Reserved9
:6; /* - */
169 USHORT DeviceWriteProtect
:1; /* - */
170 USHORT Reserved10
:7; /* - */
171 USHORT Reserved11
[128]; /* 256 */
172 } EXTENDED_IDENTIFY_DATA
, *PEXTENDED_IDENTIFY_DATA
;
175 typedef struct _PCIIDE_TRANSFER_MODE_SELECT
178 BOOLEAN DevicePresent
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
179 BOOLEAN FixedDisk
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
180 BOOLEAN IoReadySupported
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
181 ULONG DeviceTransferModeSupported
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
182 ULONG BestPioCycleTime
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
183 ULONG BestSwDmaCycleTime
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
184 ULONG BestMwDmaCycleTime
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
185 ULONG BestUDmaCycleTime
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
186 ULONG DeviceTransferModeCurrent
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
187 ULONG UserChoiceTransferMode
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
189 IDENTIFY_DATA IdentifyData
[MAX_IDE_DEVICE
];
190 ULONG DeviceTransferModeSelected
[MAX_IDE_DEVICE
* MAX_IDE_LINE
];
191 PULONG TransferModeTimingTable
;
192 ULONG TransferModeTableLength
;
193 } PCIIDE_TRANSFER_MODE_SELECT
, *PPCIIDE_TRANSFER_MODE_SELECT
;
202 typedef IDE_CHANNEL_STATE
203 (NTAPI
*PCIIDE_CHANNEL_ENABLED
)(
204 IN PVOID DeviceExtension
,
208 (NTAPI
*PCIIDE_SYNC_ACCESS_REQUIRED
)(
209 IN PVOID DeviceExtension
);
212 (NTAPI
*PCIIDE_TRANSFER_MODE_SELECT_FUNC
)(
213 IN PVOID DeviceExtension
,
214 IN OUT PPCIIDE_TRANSFER_MODE_SELECT XferMode
);
217 (NTAPI
*PCIIDE_USEDMA_FUNC
)(
218 IN PVOID DeviceExtension
,
219 IN PUCHAR CdbCommand
,
223 (NTAPI
*PCIIDE_UDMA_MODES_SUPPORTED
)(
224 IN IDENTIFY_DATA IdentifyData
,
225 OUT PULONG BestXferMode
,
226 OUT PULONG CurrentXferMode
);
228 typedef struct _IDE_CONTROLLER_PROPERTIES
232 ULONG SupportedTransferMode
[MAX_IDE_CHANNEL
][MAX_IDE_DEVICE
];
233 PCIIDE_CHANNEL_ENABLED PciIdeChannelEnabled
;
234 PCIIDE_SYNC_ACCESS_REQUIRED PciIdeSyncAccessRequired
;
235 PCIIDE_TRANSFER_MODE_SELECT_FUNC PciIdeTransferModeSelect
;
236 BOOLEAN IgnoreActiveBitForAtaDevice
;
237 BOOLEAN AlwaysClearBusMasterInterrupt
;
238 PCIIDE_USEDMA_FUNC PciIdeUseDma
;
239 ULONG AlignmentRequirement
;
241 PCIIDE_UDMA_MODES_SUPPORTED PciIdeUdmaModesSupported
;
242 } IDE_CONTROLLER_PROPERTIES
, *PIDE_CONTROLLER_PROPERTIES
;
245 (NTAPI
*PCONTROLLER_PROPERTIES
)(
246 IN PVOID DeviceExtension
,
247 IN PIDE_CONTROLLER_PROPERTIES ControllerProperties
);
251 IN PDRIVER_OBJECT DriverObject
,
252 IN PUNICODE_STRING RegistryPath
,
253 IN PCONTROLLER_PROPERTIES HwGetControllerProperties
,
254 IN ULONG ExtensionSize
);
258 IN PVOID DeviceExtension
,
260 IN ULONG ConfigDataOffset
,
261 IN ULONG BufferLength
);
265 IN PVOID DeviceExtension
,
268 IN ULONG ConfigDataOffset
,
269 IN ULONG BufferLength
);
271 /* Bit field values for
272 * PCIIDE_TRANSFER_MODE_SELECT.DeviceTransferModeSupported and
273 * IDE_CONTROLLER_PROPERTIES.SupportedTransferMode
276 #define PIO_MODE0 (1 << 0)
277 #define PIO_MODE1 (1 << 1)
278 #define PIO_MODE2 (1 << 2)
279 #define PIO_MODE3 (1 << 3)
280 #define PIO_MODE4 (1 << 4)
281 // Single-word DMA Modes
282 #define SWDMA_MODE0 (1 << 5)
283 #define SWDMA_MODE1 (1 << 6)
284 #define SWDMA_MODE2 (1 << 7)
285 // Multi-word DMA Modes
286 #define MWDMA_MODE0 (1 << 8)
287 #define MWDMA_MODE1 (1 << 9)
288 #define MWDMA_MODE2 (1 << 10)
290 #define UDMA_MODE0 (1 << 11)
291 #define UDMA_MODE1 (1 << 12)
292 #define UDMA_MODE2 (1 << 13)
293 #define UDMA_MODE3 (1 << 14)
294 #define UDMA_MODE4 (1 << 15)
295 #define UDMA_MODE5 (1 << 16)