#include <ntddk.h>
+
+//
+// Host Controller Capability Registers
+//
+#define EHCI_CAPLENGTH 0x00
+#define EHCI_HCIVERSION 0x02
+#define EHCI_HCSPARAMS 0x04
+#define EHCI_HCCPARAMS 0x08
+#define EHCI_HCSP_PORTROUTE 0x0c
+
+
+//
+// Extended Capabilities
+//
+#define EHCI_ECP_SHIFT 8
+#define EHCI_ECP_MASK 0xff
+#define EHCI_LEGSUP_CAPID_MASK 0xff
+#define EHCI_LEGSUP_CAPID 0x01
+#define EHCI_LEGSUP_OSOWNED (1 << 24)
+#define EHCI_LEGSUP_BIOSOWNED (1 << 16)
+
+
//
// EHCI Operational Registers
//
#define EHCI_PRT_POWER 0x1000
#define EHCI_PRT_RELEASEOWNERSHIP 0x2000
+#define EHCI_PORTSC_DATAMASK 0xffffffd1
//
// Terminate Pointer used for QueueHeads and Element Transfer Descriptors to mark Pointers as the end
//
//Software
ULONG PhysicalAddr;
LIST_ENTRY LinkedDescriptors;
+ ULONG TotalBytesToTransfer;
} QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
//
//Software
ULONG PhysicalAddr;
LIST_ENTRY LinkedQueueHeads;
- PQUEUE_TRANSFER_DESCRIPTOR TransferDescriptor;
- PIRP IrpToComplete;
- PMDL Mdl;
- PKEVENT Event;
PVOID Request;
} QUEUE_HEAD, *PQUEUE_HEAD;
EHCI_HCC_CONTENT HCCParams;
ULONG HCCParamsLong;
};
- UCHAR PortRoute [8];
+ UCHAR PortRoute [15];
} EHCI_CAPS, *PEHCI_CAPS;
KSPIN_LOCK Lock;
LPDMA_MEMORY_ALLOCATOR DmaMemAllocator;
} EHCI_HOST_CONTROLLER, *PEHCI_HOST_CONTROLLER;
+
+typedef struct
+{
+ ULONG PortStatus;
+ ULONG PortChange;
+}EHCI_PORT_STATUS;
+