{
ULONG Control, NumberOfPorts, Index, Descriptor, FrameInterval, Periodic;
- //
- // first write address of HCCA
- //
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET), m_HCCAPhysicalAddress.LowPart);
-
//
// lets write physical address of dummy control endpoint descriptor
//
WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_BULK_HEAD_ED_OFFSET), m_BulkEndpointDescriptor->PhysicalAddress.LowPart);
//
- // read control register
+ // get frame interval
//
- Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET));
+ FrameInterval = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_FRAME_INTERVAL_OFFSET));
+ FrameInterval = ((FrameInterval & OHCI_FRAME_INTERVAL_TOGGLE) ^ OHCI_FRAME_INTERVAL_TOGGLE);
+ DPRINT1("FrameInterval %x IntervalValue %x\n", FrameInterval, m_IntervalValue);
+ FrameInterval |= OHCI_FSMPS(m_IntervalValue) | m_IntervalValue;
+ DPRINT1("FrameInterval %x\n", FrameInterval);
//
- // remove flags
- //
- Control &= ~(OHCI_CONTROL_BULK_SERVICE_RATIO_MASK | OHCI_ENABLE_LIST | OHCI_HC_FUNCTIONAL_STATE_MASK | OHCI_INTERRUPT_ROUTING);
+ // write frame interval
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_FRAME_INTERVAL_OFFSET), FrameInterval);
//
- // set command status flags
+ // write address of HCCA
//
- Control |= OHCI_ENABLE_LIST | OHCI_CONTROL_BULK_RATIO_1_4 | OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL;
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET), m_HCCAPhysicalAddress.LowPart);
//
- // now start the controller
+ // now enable the interrupts
//
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET), Control);
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_INTERRUPT_ENABLE_OFFSET), OHCI_NORMAL_INTERRUPTS | OHCI_MASTER_INTERRUPT_ENABLE);
//
- // wait a bit
+ // enable all queues
//
- KeStallExecutionProcessor(100);
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET), OHCI_ENABLE_LIST);
//
- // is the controller started
+ // 90 % periodic
//
- Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET));
+ Periodic = OHCI_PERIODIC(m_IntervalValue);
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_PERIODIC_START_OFFSET), Periodic);
+ DPRINT1("Periodic Start %x\n", Periodic);
//
- // assert that the controller has been started
+ // start the controller
//
- ASSERT((Control & OHCI_HC_FUNCTIONAL_STATE_MASK) == OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL);
- ASSERT((Control & OHCI_ENABLE_LIST) == OHCI_ENABLE_LIST);
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET), OHCI_ENABLE_LIST | OHCI_CONTROL_BULK_RATIO_1_4 | OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL);
//
- // get frame interval
+ // wait a bit
//
- FrameInterval = (READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_FRAME_INTERVAL_OFFSET)) & OHCI_FRAME_INTERVAL_TOGGLE) ^ OHCI_FRAME_INTERVAL_TOGGLE;
- FrameInterval |= OHCI_FSMPS(m_IntervalValue) | m_IntervalValue;
+ KeStallExecutionProcessor(100);
//
- // write frame interval
+ // is the controller started
//
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_FRAME_INTERVAL_OFFSET), FrameInterval);
+ Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET));
//
- // 90 % periodic
+ // assert that the controller has been started
//
- Periodic = OHCI_PERIODIC(m_IntervalValue);
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_PERIODIC_START_OFFSET), Periodic);
-
+ ASSERT((Control & OHCI_HC_FUNCTIONAL_STATE_MASK) == OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL);
+ ASSERT((Control & OHCI_ENABLE_LIST) == OHCI_ENABLE_LIST);
+ DPRINT1("Control %x\n", Control);
//
// read descriptor
//
WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_DESCRIPTOR_A_OFFSET), Descriptor);
-
-
//
// retrieve number of ports
//
DPRINT1("NumberOfPorts %lu\n", m_NumberOfPorts);
- //
- // now enable the interrupts
- //
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_INTERRUPT_ENABLE_OFFSET), OHCI_NORMAL_INTERRUPTS | OHCI_MASTER_INTERRUPT_ENABLE);
-
//
// done
//
NTSTATUS
CUSBHardwareDevice::StopController(void)
{
- ULONG Control, Reset;
+ ULONG Control, Reset, Status;
ULONG Index, FrameInterval;
//
- // first turn off all interrupts
+ // alignment check
//
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_INTERRUPT_DISABLE_OFFSET), OHCI_ALL_INTERRUPTS);
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET, 0xFFFFFFFF);
+ Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET));
+ DPRINT1("HcHCCA Alignment %x\n", Control);
+ ASSERT((Control & 0xFFFFFFF0) == 0xFFFFFFF0);
//
// check context
//
Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET));
- //
- // FIXME: support routing
- //
- ASSERT((Control & OHCI_INTERRUPT_ROUTING) == 0);
+ if ((Control & OHCI_INTERRUPT_ROUTING))
+ {
+ //
+ // read command status
+ //
+ Status = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_COMMAND_STATUS_OFFSET));
- //
- // have a break
- //
- KeStallExecutionProcessor(100);
+ //
+ // change ownership
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_COMMAND_STATUS_OFFSET), Status | OHCI_OWNERSHIP_CHANGE_REQUEST);
+ for(Index = 0; Index < 100; Index++)
+ {
+ //
+ // wait a bit
+ //
+ KeStallExecutionProcessor(100);
- //
- // some controllers also depend on this
- //
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET), OHCI_HC_FUNCTIONAL_STATE_RESET);
+ //
+ // check control
+ //
+ Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET));
+ if (!(Control & OHCI_INTERRUPT_ROUTING))
+ {
+ //
+ // acquired ownership
+ //
+ break;
+ }
+ }
- //
- // wait a bit
- //
- KeStallExecutionProcessor(100);
+ //
+ // if the ownership is still not changed, perform reset
+ //
+ if (Control & OHCI_INTERRUPT_ROUTING)
+ {
+ DPRINT1("SMM not responding\n");
+ }
+ else
+ {
+ DPRINT1("SMM has given up ownership\n");
+ }
+ }
+ else
+ {
+ //
+ // read contents of control register
+ //
+ Control = (READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET)) & OHCI_HC_FUNCTIONAL_STATE_MASK);
+ DPRINT1("Controller State %x\n", Control);
+
+ if (Control != OHCI_HC_FUNCTIONAL_STATE_RESET)
+ {
+ //
+ // OHCI 5.1.1.3.4, no SMM, BIOS active
+ //
+ if (Control != OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL)
+ {
+ //
+ // lets resume
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET), OHCI_HC_FUNCTIONAL_STATE_RESUME);
+ Index = 0;
+ do
+ {
+ //
+ // wait untill its resumed
+ //
+ KeStallExecutionProcessor(10);
+
+ //
+ // check control register
+ //
+ Control = (READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET)) & OHCI_HC_FUNCTIONAL_STATE_MASK);
+ if (Control & OHCI_HC_FUNCTIONAL_STATE_RESUME)
+ {
+ //
+ // it has resumed
+ //
+ break;
+ }
+
+ //
+ // check for time outs
+ //
+ Index++;
+ if(Index > 100)
+ {
+ DPRINT1("Failed to resume controller\n");
+ break;
+ }
+ }while(TRUE);
+ }
+ }
+ else
+ {
+ //
+ // 5.1.1.3.5 OHCI, no SMM, no BIOS
+ //
+ Index = 0;
+
+ //
+ // some controllers also depend on this
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET), OHCI_HC_FUNCTIONAL_STATE_RESET);
+ do
+ {
+ //
+ // wait untill its reset
+ //
+ KeStallExecutionProcessor(10);
+
+ //
+ // check control register
+ //
+ Control = (READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET)) & OHCI_HC_FUNCTIONAL_STATE_MASK);
+ if (Control == OHCI_HC_FUNCTIONAL_STATE_RESET)
+ {
+ //
+ // it has reset
+ //
+ break;
+ }
+
+ //
+ // check for time outs
+ //
+ Index++;
+ if(Index > 100)
+ {
+ DPRINT1("Failed to reset controller\n");
+ break;
+ }
+
+ }while(TRUE);
+ }
+ }
//
// read from interval
//
m_IntervalValue = OHCI_GET_INTERVAL_VALUE(FrameInterval);
+ DPRINT1("FrameInterval %x Interval %x\n", FrameInterval, m_IntervalValue);
+
//
// now reset controller
//
//
if ((Reset & OHCI_HOST_CONTROLLER_RESET) == 0)
{
+ //
+ // restore the frame interval register
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_FRAME_INTERVAL_OFFSET), FrameInterval);
+
//
// controller completed reset
//
OUT USHORT *PortStatus,
OUT USHORT *PortChange)
{
+ ULONG Value;
+
+ if (PortId > m_NumberOfPorts)
+ return STATUS_UNSUCCESSFUL;
+
+ // init result variables
+ *PortStatus = 0;
+ *PortChange = 0;
+
//
- // FIXME: should read status from hardware
+ // read port status
//
- *PortStatus = m_PortStatus[PortId].PortStatus;
- *PortChange = m_PortStatus[PortId].PortChange;
+ Value = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)));
+ DPRINT("GetPortStatus PortId %x Value %x\n", PortId, Value);
+
+
+ // connected
+ if (Value & OHCI_RH_PORTSTATUS_CCS)
+ *PortStatus |= USB_PORT_STATUS_CONNECT;
+
+ // did a device connect?
+ if (Value & OHCI_RH_PORTSTATUS_CSC)
+ *PortChange |= USB_PORT_STATUS_CONNECT;
+
+ // port enabled
+ if (Value & OHCI_RH_PORTSTATUS_PES)
+ *PortStatus |= USB_PORT_STATUS_ENABLE;
+
+ // port enabled
+ if (Value & OHCI_RH_PORTSTATUS_PESC)
+ *PortChange |= USB_PORT_STATUS_ENABLE;
+
+ // port suspend
+ if (Value & OHCI_RH_PORTSTATUS_PSS)
+ *PortStatus |= USB_PORT_STATUS_SUSPEND;
+
+ // port suspend
+ if (Value & OHCI_RH_PORTSTATUS_PSSC)
+ *PortChange |= USB_PORT_STATUS_ENABLE;
+
+ // port reset
+ if (Value & OHCI_RH_PORTSTATUS_PSS)
+ *PortStatus |= USB_PORT_STATUS_RESET;
+
+ // port reset
+ if (Value & OHCI_RH_PORTSTATUS_PRSC)
+ *PortChange |= USB_PORT_STATUS_RESET;
+
return STATUS_SUCCESS;
}
ULONG PortId,
ULONG Status)
{
- ULONG Value, Index = 0;
+ ULONG Value;
DPRINT("CUSBHardwareDevice::ClearPortStatus PortId %x Feature %x\n", PortId, Status);
CUSBHardwareDevice::GetCurrentFrameNumber(
PULONG FrameNumber)
{
+ ULONG Control;
+ ULONG Number;
+
+
+ Number = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_FRAME_INTERVAL_NUMBER_OFFSET));
+ DPRINT1("FrameNumberInterval %x Frame %x\n", Number, m_HCCA->CurrentFrameNumber);
+
+ //
+ // remove reserved bits
+ //
+ Number &= 0xFFFF;
+
//
// store frame number
//
- *FrameNumber = m_HCCA->CurrentFrameNumber;
+ *FrameNumber = Number;
+
+ //
+ // is the controller started
+ //
+ Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET));
+ ASSERT((Control & OHCI_ENABLE_LIST) == OHCI_ENABLE_LIST);
+
+
}
VOID
//
// defer processing
//
- DPRINT("Status %x Acknowledge %x\n", Status, Acknowledge);
+ DPRINT("Status %x Acknowledge %x FrameNumber %x\n", Status, Acknowledge, This->m_HCCA->CurrentFrameNumber);
KeInsertQueueDpc(&This->m_IntDpcObject, (PVOID)Status, (PVOID)(DoneHead & ~1));
//
{
CUSBHardwareDevice *This;
ULONG CStatus, Index, PortStatus;
- POHCI_ENDPOINT_DESCRIPTOR EndpointDescriptor;
ULONG DoneHead;
//
//
This->m_PortStatus[Index].PortStatus |= USB_PORT_STATUS_LOW_SPEED;
}
-
- //
- // is there a status change callback
- //
- if (This->m_SCECallBack != NULL)
- {
- //
- // queue work item for processing
- //
- ExQueueWorkItem(&This->m_StatusChangeWorkItem, DelayedWorkQueue);
- }
}
else
{
// device disconnected
//
DPRINT1("Device disconnected at Port %x\n", Index);
+
+ //
+ // update port status flags
+ //
+ This->m_PortStatus[Index].PortStatus &= ~USB_PORT_STATUS_LOW_SPEED;
+ This->m_PortStatus[Index].PortStatus &= ~USB_PORT_STATUS_CONNECT;
+ This->m_PortStatus[Index].PortChange |= USB_PORT_STATUS_CONNECT;
+ }
+
+ //
+ // is there a status change callback
+ //
+ if (This->m_SCECallBack != NULL)
+ {
+ //
+ // queue work item for processing
+ //
+ ExQueueWorkItem(&This->m_StatusChangeWorkItem, DelayedWorkQueue);
}
}
}
projects / reactos.git / blobdiff