#include <fast486.h>
#include "opcodes.h"
#include "common.h"
+#include "opgroups.h"
#include "extraops.h"
/* PUBLIC VARIABLES ***********************************************************/
NULL, // TODO: OPCODE 0x03 NOT IMPLEMENTED
NULL, // TODO: OPCODE 0x04 NOT IMPLEMENTED
NULL, // TODO: OPCODE 0x05 NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0x06 NOT IMPLEMENTED
+ Fast486ExtOpcodeClts,
NULL, // TODO: OPCODE 0x07 NOT IMPLEMENTED
NULL, // TODO: OPCODE 0x08 NOT IMPLEMENTED
NULL, // TODO: OPCODE 0x09 NOT IMPLEMENTED
NULL, // Invalid
NULL, // Invalid
NULL, // Invalid
- NULL, // TODO: OPCODE 0x20 NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0x21 NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0x22 NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0x23 NOT IMPLEMENTED
+ Fast486ExtOpcodeStoreControlReg,
+ Fast486ExtOpcodeStoreDebugReg,
+ Fast486ExtOpcodeLoadControlReg,
+ Fast486ExtOpcodeLoadDebugReg,
NULL, // TODO: OPCODE 0x24 NOT IMPLEMENTED
NULL, // Invalid
NULL, // TODO: OPCODE 0x26 NOT IMPLEMENTED
Fast486ExtOpcodePushFs,
Fast486ExtOpcodePopFs,
NULL, // Invalid
- NULL, // TODO: OPCODE 0xA3 NOT IMPLEMENTED
+ Fast486ExtOpcodeBitTest,
NULL, // TODO: OPCODE 0xA4 NOT IMPLEMENTED
NULL, // TODO: OPCODE 0xA5 NOT IMPLEMENTED
NULL, // Invalid
NULL, // Invalid
Fast486ExtOpcodePushGs,
Fast486ExtOpcodePopGs,
- NULL, // TODO: OPCODE 0xAA NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xAB NOT IMPLEMENTED
+ NULL, // Invalid
+ Fast486ExtOpcodeBts,
NULL, // TODO: OPCODE 0xAC NOT IMPLEMENTED
NULL, // TODO: OPCODE 0xAD NOT IMPLEMENTED
NULL, // TODO: OPCODE 0xAE NOT IMPLEMENTED
Fast486ExtOpcodeCmpXchgByte,
Fast486ExtOpcodeCmpXchg,
NULL, // TODO: OPCODE 0xB2 NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xB3 NOT IMPLEMENTED
+ Fast486ExtOpcodeBtr,
NULL, // TODO: OPCODE 0xB4 NOT IMPLEMENTED
NULL, // TODO: OPCODE 0xB5 NOT IMPLEMENTED
NULL, // TODO: OPCODE 0xB6 NOT IMPLEMENTED
NULL, // TODO: OPCODE 0xB7 NOT IMPLEMENTED
NULL, // TODO: OPCODE 0xB8 NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xB9 NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xBA NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xBB NOT IMPLEMENTED
+ Fast486OpcodeGroup0FB9,
+ Fast486OpcodeGroup0FBA,
+ Fast486ExtOpcodeBtc,
NULL, // TODO: OPCODE 0xBC NOT IMPLEMENTED
NULL, // TODO: OPCODE 0xBD NOT IMPLEMENTED
NULL, // TODO: OPCODE 0xBE NOT IMPLEMENTED
NULL, // Invalid
NULL, // Invalid
NULL, // Invalid
- NULL, // TODO: OPCODE 0xC8 NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xC9 NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xCA NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xCB NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xCC NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xCD NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xCE NOT IMPLEMENTED
- NULL, // TODO: OPCODE 0xCF NOT IMPLEMENTED
+ Fast486ExtOpcodeBswap,
+ Fast486ExtOpcodeBswap,
+ Fast486ExtOpcodeBswap,
+ Fast486ExtOpcodeBswap,
+ Fast486ExtOpcodeBswap,
+ Fast486ExtOpcodeBswap,
+ Fast486ExtOpcodeBswap,
+ Fast486ExtOpcodeBswap,
NULL, // Invalid
NULL, // Invalid
NULL, // Invalid
/* PUBLIC FUNCTIONS ***********************************************************/
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeClts)
+{
+ NO_LOCK_PREFIX();
+
+ /* The current privilege level must be zero */
+ if (Fast486GetCurrentPrivLevel(State) != 0)
+ {
+ Fast486Exception(State, FAST486_EXCEPTION_GP);
+ return FALSE;
+ }
+
+ /* Clear the task switch bit */
+ State->ControlRegisters[FAST486_REG_CR0] &= ~FAST486_CR0_TS;
+
+ return TRUE;
+}
+
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeStoreControlReg)
+{
+ BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
+ FAST486_MOD_REG_RM ModRegRm;
+
+ NO_LOCK_PREFIX();
+ TOGGLE_ADSIZE(AddressSize);
+
+ /* Get the operands */
+ if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* The current privilege level must be zero */
+ if (Fast486GetCurrentPrivLevel(State) != 0)
+ {
+ Fast486Exception(State, FAST486_EXCEPTION_GP);
+ return FALSE;
+ }
+
+ if ((ModRegRm.Register == 1) || (ModRegRm.Register > 3))
+ {
+ /* CR1, CR4, CR5, CR6 and CR7 don't exist */
+ Fast486Exception(State, FAST486_EXCEPTION_UD);
+ return FALSE;
+ }
+
+ if (ModRegRm.Register != 0)
+ {
+ /* CR2 and CR3 and are stored in array indexes 1 and 2 */
+ ModRegRm.Register--;
+ }
+
+ /* Store the value of the control register */
+ State->GeneralRegs[ModRegRm.SecondRegister].Long = State->ControlRegisters[ModRegRm.Register];
+
+ /* Return success */
+ return TRUE;
+}
+
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeStoreDebugReg)
+{
+ BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
+ FAST486_MOD_REG_RM ModRegRm;
+
+ NO_LOCK_PREFIX();
+ TOGGLE_ADSIZE(AddressSize);
+
+ /* Get the operands */
+ if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* The current privilege level must be zero */
+ if (Fast486GetCurrentPrivLevel(State) != 0)
+ {
+ Fast486Exception(State, FAST486_EXCEPTION_GP);
+ return FALSE;
+ }
+
+ if ((ModRegRm.Register == 6) || (ModRegRm.Register == 7))
+ {
+ /* DR6 and DR7 are aliases to DR4 and DR5 */
+ ModRegRm.Register -= 2;
+ }
+
+ if (State->DebugRegisters[FAST486_REG_DR5] & FAST486_DR5_GD)
+ {
+ /* Disallow access to debug registers */
+ Fast486Exception(State, FAST486_EXCEPTION_GP);
+ return FALSE;
+ }
+
+ /* Store the value of the debug register */
+ State->GeneralRegs[ModRegRm.SecondRegister].Long = State->DebugRegisters[ModRegRm.Register];
+
+ /* Return success */
+ return TRUE;
+}
+
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeLoadControlReg)
+{
+ ULONG Value;
+ BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
+ FAST486_MOD_REG_RM ModRegRm;
+
+ NO_LOCK_PREFIX();
+ TOGGLE_ADSIZE(AddressSize);
+
+ /* Get the operands */
+ if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* The current privilege level must be zero */
+ if (Fast486GetCurrentPrivLevel(State) != 0)
+ {
+ Fast486Exception(State, FAST486_EXCEPTION_GP);
+ return FALSE;
+ }
+
+ if ((ModRegRm.Register == 1) || (ModRegRm.Register > 3))
+ {
+ /* CR1, CR4, CR5, CR6 and CR7 don't exist */
+ Fast486Exception(State, FAST486_EXCEPTION_UD);
+ return FALSE;
+ }
+
+ if (ModRegRm.Register != 0)
+ {
+ /* CR2 and CR3 and are stored in array indexes 1 and 2 */
+ ModRegRm.Register--;
+ }
+
+ /* Get the value */
+ Value = State->GeneralRegs[ModRegRm.SecondRegister].Long;
+
+ if (ModRegRm.Register == (INT)FAST486_REG_CR0)
+ {
+ /* CR0 checks */
+
+ if (((Value & (FAST486_CR0_PG | FAST486_CR0_PE)) == FAST486_CR0_PG)
+ || ((Value & (FAST486_CR0_CD | FAST486_CR0_NW)) == FAST486_CR0_NW))
+ {
+ /* Invalid value */
+ Fast486Exception(State, FAST486_EXCEPTION_GP);
+ return FALSE;
+ }
+ }
+
+ /* Load a value to the control register */
+ State->ControlRegisters[ModRegRm.Register] = Value;
+
+ /* Return success */
+ return TRUE;
+}
+
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeLoadDebugReg)
+{
+ BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
+ FAST486_MOD_REG_RM ModRegRm;
+
+ NO_LOCK_PREFIX();
+ TOGGLE_ADSIZE(AddressSize);
+
+ /* Get the operands */
+ if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* The current privilege level must be zero */
+ if (Fast486GetCurrentPrivLevel(State) != 0)
+ {
+ Fast486Exception(State, FAST486_EXCEPTION_GP);
+ return FALSE;
+ }
+
+ if ((ModRegRm.Register == 6) || (ModRegRm.Register == 7))
+ {
+ /* DR6 and DR7 are aliases to DR4 and DR5 */
+ ModRegRm.Register -= 2;
+ }
+
+ if (State->DebugRegisters[FAST486_REG_DR5] & FAST486_DR5_GD)
+ {
+ /* Disallow access to debug registers */
+ Fast486Exception(State, FAST486_EXCEPTION_GP);
+ return FALSE;
+ }
+
+ /* Load a value to the debug register */
+ State->DebugRegisters[ModRegRm.Register] = State->GeneralRegs[ModRegRm.SecondRegister].Long;
+
+ if (ModRegRm.Register == (INT)FAST486_REG_DR4)
+ {
+ /* The reserved bits are 1 */
+ State->DebugRegisters[ModRegRm.Register] |= FAST486_DR4_RESERVED;
+ }
+ else if (ModRegRm.Register == (INT)FAST486_REG_DR5)
+ {
+ /* The reserved bits are 0 */
+ State->DebugRegisters[ModRegRm.Register] &= ~FAST486_DR5_RESERVED;
+ }
+
+ /* Return success */
+ return TRUE;
+}
+
FAST486_OPCODE_HANDLER(Fast486ExtOpcodePushFs)
{
/* Call the internal API */
return Fast486LoadSegment(State, FAST486_REG_FS, LOWORD(NewSelector));
}
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeBitTest)
+{
+ BOOLEAN OperandSize, AddressSize;
+ FAST486_MOD_REG_RM ModRegRm;
+ UINT DataSize;
+ ULONG BitNumber;
+
+ OperandSize = AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
+ TOGGLE_OPSIZE(OperandSize);
+ TOGGLE_ADSIZE(AddressSize);
+
+ /* Get the number of bits */
+ if (OperandSize) DataSize = 32;
+ else DataSize = 16;
+
+ /* Get the operands */
+ if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* Get the bit number */
+ BitNumber = OperandSize ? State->GeneralRegs[ModRegRm.Register].Long
+ : (ULONG)State->GeneralRegs[ModRegRm.Register].LowWord;
+
+ if (ModRegRm.Memory)
+ {
+ /*
+ * For memory operands, add the bit offset divided by
+ * the data size to the address
+ */
+ ModRegRm.MemoryAddress += BitNumber / DataSize;
+ }
+
+ /* Normalize the bit number */
+ BitNumber &= (1 << DataSize) - 1;
+
+ if (OperandSize)
+ {
+ ULONG Dummy, Value;
+
+ /* Read the value */
+ if (!Fast486ReadModrmDwordOperands(State, &ModRegRm, &Dummy, &Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* Set CF to the bit value */
+ State->Flags.Cf = (Value >> BitNumber) & 1;
+ }
+ else
+ {
+ USHORT Dummy, Value;
+
+ /* Read the value */
+ if (!Fast486ReadModrmWordOperands(State, &ModRegRm, &Dummy, &Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* Set CF to the bit value */
+ State->Flags.Cf = (Value >> BitNumber) & 1;
+ }
+
+ /* Return success */
+ return TRUE;
+}
+
FAST486_OPCODE_HANDLER(Fast486ExtOpcodePushGs)
{
/* Call the internal API */
return Fast486LoadSegment(State, FAST486_REG_GS, LOWORD(NewSelector));
}
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeBts)
+{
+ BOOLEAN OperandSize, AddressSize;
+ FAST486_MOD_REG_RM ModRegRm;
+ UINT DataSize;
+ ULONG BitNumber;
+
+ OperandSize = AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
+ TOGGLE_OPSIZE(OperandSize);
+ TOGGLE_ADSIZE(AddressSize);
+
+ /* Get the number of bits */
+ if (OperandSize) DataSize = 32;
+ else DataSize = 16;
+
+ /* Get the operands */
+ if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* Get the bit number */
+ BitNumber = OperandSize ? State->GeneralRegs[ModRegRm.Register].Long
+ : (ULONG)State->GeneralRegs[ModRegRm.Register].LowWord;
+
+ if (ModRegRm.Memory)
+ {
+ /*
+ * For memory operands, add the bit offset divided by
+ * the data size to the address
+ */
+ ModRegRm.MemoryAddress += BitNumber / DataSize;
+ }
+
+ /* Normalize the bit number */
+ BitNumber &= (1 << DataSize) - 1;
+
+ if (OperandSize)
+ {
+ ULONG Dummy, Value;
+
+ /* Read the value */
+ if (!Fast486ReadModrmDwordOperands(State, &ModRegRm, &Dummy, &Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* Set CF to the bit value */
+ State->Flags.Cf = (Value >> BitNumber) & 1;
+
+ /* Set the bit */
+ Value |= 1 << BitNumber;
+
+ /* Write back the result */
+ if (!Fast486WriteModrmDwordOperands(State, &ModRegRm, FALSE, Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+ }
+ else
+ {
+ USHORT Dummy, Value;
+
+ /* Read the value */
+ if (!Fast486ReadModrmWordOperands(State, &ModRegRm, &Dummy, &Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* Set CF to the bit value */
+ State->Flags.Cf = (Value >> BitNumber) & 1;
+
+ /* Set the bit */
+ Value |= 1 << BitNumber;
+
+ /* Write back the result */
+ if (!Fast486WriteModrmWordOperands(State, &ModRegRm, FALSE, Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+ }
+
+ /* Return success */
+ return TRUE;
+}
+
FAST486_OPCODE_HANDLER(Fast486ExtOpcodeCmpXchgByte)
{
FAST486_MOD_REG_RM ModRegRm;
UCHAR Accumulator = State->GeneralRegs[FAST486_REG_EAX].LowByte;
UCHAR Source, Destination, Result;
- BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;;
+ BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
- if (State->PrefixFlags & FAST486_PREFIX_ADSIZE)
- {
- /* The ADSIZE prefix toggles the size */
- AddressSize = !AddressSize;
- }
+ TOGGLE_ADSIZE(AddressSize);
/* Get the operands */
if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
OperandSize = AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
- if (State->PrefixFlags & FAST486_PREFIX_OPSIZE)
- {
- /* The OPSIZE prefix toggles the size */
- OperandSize = !OperandSize;
- }
-
- if (State->PrefixFlags & FAST486_PREFIX_ADSIZE)
- {
- /* The ADSIZE prefix toggles the size */
- AddressSize = !AddressSize;
- }
+ TOGGLE_OPSIZE(OperandSize);
+ TOGGLE_ADSIZE(AddressSize);
/* Get the operands */
if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
/* Return success */
return TRUE;
-
}
-FAST486_OPCODE_HANDLER(Fast486ExtOpcodeConditionalJmp)
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeBtr)
{
- BOOLEAN Jump = FALSE;
- LONG Offset = 0;
- BOOLEAN Size = State->SegmentRegs[FAST486_REG_CS].Size;
+ BOOLEAN OperandSize, AddressSize;
+ FAST486_MOD_REG_RM ModRegRm;
+ UINT DataSize;
+ ULONG BitNumber;
+
+ OperandSize = AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
+ TOGGLE_OPSIZE(OperandSize);
+ TOGGLE_ADSIZE(AddressSize);
- if (State->PrefixFlags & FAST486_PREFIX_OPSIZE)
+ /* Get the number of bits */
+ if (OperandSize) DataSize = 32;
+ else DataSize = 16;
+
+ /* Get the operands */
+ if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
{
- /* The OPSIZE prefix toggles the size */
- Size = !Size;
+ /* Exception occurred */
+ return FALSE;
}
- if (State->PrefixFlags & FAST486_PREFIX_LOCK)
+ /* Get the bit number */
+ BitNumber = OperandSize ? State->GeneralRegs[ModRegRm.Register].Long
+ : (ULONG)State->GeneralRegs[ModRegRm.Register].LowWord;
+
+ if (ModRegRm.Memory)
{
- /* Invalid prefix */
- Fast486Exception(State, FAST486_EXCEPTION_UD);
+ /*
+ * For memory operands, add the bit offset divided by
+ * the data size to the address
+ */
+ ModRegRm.MemoryAddress += BitNumber / DataSize;
+ }
+
+ /* Normalize the bit number */
+ BitNumber &= (1 << DataSize) - 1;
+
+ if (OperandSize)
+ {
+ ULONG Dummy, Value;
+
+ /* Read the value */
+ if (!Fast486ReadModrmDwordOperands(State, &ModRegRm, &Dummy, &Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* Set CF to the bit value */
+ State->Flags.Cf = (Value >> BitNumber) & 1;
+
+ /* Clear the bit */
+ Value &= ~(1 << BitNumber);
+
+ /* Write back the result */
+ if (!Fast486WriteModrmDwordOperands(State, &ModRegRm, FALSE, Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+ }
+ else
+ {
+ USHORT Dummy, Value;
+
+ /* Read the value */
+ if (!Fast486ReadModrmWordOperands(State, &ModRegRm, &Dummy, &Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* Set CF to the bit value */
+ State->Flags.Cf = (Value >> BitNumber) & 1;
+
+ /* Clear the bit */
+ Value &= ~(1 << BitNumber);
+
+ /* Write back the result */
+ if (!Fast486WriteModrmWordOperands(State, &ModRegRm, FALSE, Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+ }
+
+ /* Return success */
+ return TRUE;
+}
+
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeBtc)
+{
+ BOOLEAN OperandSize, AddressSize;
+ FAST486_MOD_REG_RM ModRegRm;
+ UINT DataSize;
+ ULONG BitNumber;
+
+ OperandSize = AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
+ TOGGLE_OPSIZE(OperandSize);
+ TOGGLE_ADSIZE(AddressSize);
+
+ /* Get the number of bits */
+ if (OperandSize) DataSize = 32;
+ else DataSize = 16;
+
+ /* Get the operands */
+ if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
+ {
+ /* Exception occurred */
return FALSE;
}
+ /* Get the bit number */
+ BitNumber = OperandSize ? State->GeneralRegs[ModRegRm.Register].Long
+ : (ULONG)State->GeneralRegs[ModRegRm.Register].LowWord;
+
+ if (ModRegRm.Memory)
+ {
+ /*
+ * For memory operands, add the bit offset divided by
+ * the data size to the address
+ */
+ ModRegRm.MemoryAddress += BitNumber / DataSize;
+ }
+
+ /* Normalize the bit number */
+ BitNumber &= (1 << DataSize) - 1;
+
+ if (OperandSize)
+ {
+ ULONG Dummy, Value;
+
+ /* Read the value */
+ if (!Fast486ReadModrmDwordOperands(State, &ModRegRm, &Dummy, &Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* Set CF to the bit value */
+ State->Flags.Cf = (Value >> BitNumber) & 1;
+
+ /* Toggle the bit */
+ Value ^= 1 << BitNumber;
+
+ /* Write back the result */
+ if (!Fast486WriteModrmDwordOperands(State, &ModRegRm, FALSE, Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+ }
+ else
+ {
+ USHORT Dummy, Value;
+
+ /* Read the value */
+ if (!Fast486ReadModrmWordOperands(State, &ModRegRm, &Dummy, &Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+
+ /* Set CF to the bit value */
+ State->Flags.Cf = (Value >> BitNumber) & 1;
+
+ /* Toggle the bit */
+ Value ^= 1 << BitNumber;
+
+ /* Write back the result */
+ if (!Fast486WriteModrmWordOperands(State, &ModRegRm, FALSE, Value))
+ {
+ /* Exception occurred */
+ return FALSE;
+ }
+ }
+
+ /* Return success */
+ return TRUE;
+}
+
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeConditionalJmp)
+{
+ BOOLEAN Jump = FALSE;
+ LONG Offset = 0;
+ BOOLEAN Size = State->SegmentRegs[FAST486_REG_CS].Size;
+
+ TOGGLE_OPSIZE(Size);
+ NO_LOCK_PREFIX();
+
/* Make sure this is the right instruction */
ASSERT((Opcode & 0xF0) == 0x80);
BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
FAST486_MOD_REG_RM ModRegRm;
- if (State->PrefixFlags & FAST486_PREFIX_ADSIZE)
- {
- /* The OPSIZE prefix toggles the size */
- AddressSize = !AddressSize;
- }
+ TOGGLE_ADSIZE(AddressSize);
/* Get the operands */
if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
return Fast486WriteModrmByteOperands(State, &ModRegRm, FALSE, Value);
}
+FAST486_OPCODE_HANDLER(Fast486ExtOpcodeBswap)
+{
+ PUCHAR Pointer;
+
+ NO_LOCK_PREFIX();
+
+ /* Get a pointer to the value */
+ Pointer = (PUCHAR)&State->GeneralRegs[Opcode & 0x07].Long;
+
+ /* Swap the byte order */
+ SWAP(Pointer[0], Pointer[3]);
+ SWAP(Pointer[1], Pointer[2]);
+
+ /* Return success */
+ return TRUE;
+}
+
FAST486_OPCODE_HANDLER(Fast486OpcodeExtended)
{
UCHAR SecondOpcode;
return FALSE;
}
}
+
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