/* SUPPORT ROUTINES FOR MSVC COMPATIBILITY ***********************************/
-VOID
-NTAPI
-CPUID(IN ULONG InfoType,
- OUT PULONG CpuInfoEax,
- OUT PULONG CpuInfoEbx,
- OUT PULONG CpuInfoEcx,
- OUT PULONG CpuInfoEdx)
-{
- ULONG CpuInfo[4];
-
- /* Perform the CPUID Operation */
- __cpuid((int*)CpuInfo, InfoType);
-
- /* Return the results */
- *CpuInfoEax = CpuInfo[0];
- *CpuInfoEbx = CpuInfo[1];
- *CpuInfoEcx = CpuInfo[2];
- *CpuInfoEdx = CpuInfo[3];
-}
-
-VOID
-NTAPI
-WRMSR(IN ULONG Register,
- IN LONGLONG Value)
-{
- /* Write to the MSR */
- __writemsr(Register, Value);
-}
-
-LONGLONG
-FASTCALL
-RDMSR(IN ULONG Register)
-{
- /* Read from the MSR */
- return __readmsr(Register);
-}
-
/* NSC/Cyrix CPU configuration register index */
#define CX86_CCR1 0xc1
/* FUNCTIONS *****************************************************************/
+INIT_FUNCTION
VOID
NTAPI
-INIT_FUNCTION
KiSetProcessorType(VOID)
{
ULONG EFlags, NewEFlags;
- ULONG Reg, Dummy;
+ CPU_INFO CpuInfo;
ULONG Stepping, Type;
/* Start by assuming no CPUID data */
__writeeflags(EFlags);
/* Peform CPUID 0 to see if CPUID 1 is supported */
- CPUID(0, &Reg, &Dummy, &Dummy, &Dummy);
- if (Reg > 0)
+ KiCpuId(&CpuInfo, 0);
+ if (CpuInfo.Eax > 0)
{
/* Do CPUID 1 now */
- CPUID(1, &Reg, &Dummy, &Dummy, &Dummy);
+ KiCpuId(&CpuInfo, 1);
/*
* Get the Stepping and Type. The stepping contains both the
*
* For the stepping, we convert this: zzzzzzxy into this: x0y
*/
- Stepping = Reg & 0xF0;
+ Stepping = CpuInfo.Eax & 0xF0;
Stepping <<= 4;
- Stepping += (Reg & 0xFF);
+ Stepping += (CpuInfo.Eax & 0xFF);
Stepping &= 0xF0F;
- Type = Reg & 0xF00;
+ Type = CpuInfo.Eax & 0xF00;
Type >>= 8;
/* Save them in the PRCB */
__writeeflags(EFlags);
}
+INIT_FUNCTION
ULONG
NTAPI
-INIT_FUNCTION
KiGetCpuVendor(VOID)
{
PKPRCB Prcb = KeGetCurrentPrcb();
- ULONG Vendor[5];
- ULONG Temp;
+ CPU_INFO CpuInfo;
/* Assume no Vendor ID and fail if no CPUID Support. */
Prcb->VendorString[0] = 0;
if (!Prcb->CpuID) return 0;
- /* Get the Vendor ID and null-terminate it */
- CPUID(0, &Vendor[0], &Vendor[1], &Vendor[2], &Vendor[3]);
- Vendor[4] = 0;
-
- /* Re-arrange vendor string */
- Temp = Vendor[2];
- Vendor[2] = Vendor[3];
- Vendor[3] = Temp;
+ /* Get the Vendor ID */
+ KiCpuId(&CpuInfo, 0);
- /* Copy it to the PRCB and null-terminate it again */
- RtlCopyMemory(Prcb->VendorString,
- &Vendor[1],
- sizeof(Prcb->VendorString) - sizeof(CHAR));
- Prcb->VendorString[sizeof(Prcb->VendorString) - sizeof(CHAR)] = ANSI_NULL;
+ /* Copy it to the PRCB and null-terminate it */
+ *(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
+ *(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
+ *(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
+ Prcb->VendorString[12] = 0;
/* Now check the CPU Type */
if (!strcmp(Prcb->VendorString, CmpIntelID))
return CPU_UNKNOWN;
}
+INIT_FUNCTION
ULONG
NTAPI
-INIT_FUNCTION
KiGetFeatureBits(VOID)
{
PKPRCB Prcb = KeGetCurrentPrcb();
ULONG Vendor;
ULONG FeatureBits = KF_WORKING_PTE;
- ULONG Reg[4], Dummy;
+ CPU_INFO CpuInfo, DummyCpuInfo;
UCHAR Ccr1;
BOOLEAN ExtendedCPUID = TRUE;
ULONG CpuFeatures = 0;
if (!Vendor) return FeatureBits;
/* Get the CPUID Info. Features are in Reg[3]. */
- CPUID(1, &Reg[0], &Reg[1], &Dummy, &Reg[3]);
+ KiCpuId(&CpuInfo, 1);
/* Set the initial APIC ID */
- Prcb->InitialApicId = (UCHAR)(Reg[1] >> 24);
+ Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24);
switch (Vendor)
{
if (Prcb->CpuType == 6)
{
/* Perform the special sequence to get the MicroCode Signature */
- WRMSR(0x8B, 0);
- CPUID(1, &Dummy, &Dummy, &Dummy, &Dummy);
- Prcb->UpdateSignature.QuadPart = RDMSR(0x8B);
+ __writemsr(0x8B, 0);
+ KiCpuId(&DummyCpuInfo, 1);
+ Prcb->UpdateSignature.QuadPart = __readmsr(0x8B);
}
else if (Prcb->CpuType == 5)
{
}
/* Check for broken P6 with bad SMP PTE implementation */
- if (((Reg[0] & 0x0FF0) == 0x0610 && (Reg[0] & 0x000F) <= 0x9) ||
- ((Reg[0] & 0x0FF0) == 0x0630 && (Reg[0] & 0x000F) <= 0x4))
+ if (((CpuInfo.Eax & 0x0FF0) == 0x0610 && (CpuInfo.Eax & 0x000F) <= 0x9) ||
+ ((CpuInfo.Eax & 0x0FF0) == 0x0630 && (CpuInfo.Eax & 0x000F) <= 0x4))
{
/* Remove support for correct PTE support. */
FeatureBits &= ~KF_WORKING_PTE;
((Prcb->CpuType == 6) && (Prcb->CpuStep < 0x0303)))
{
/* Disable it */
- Reg[3] &= ~0x800;
+ CpuInfo.Edx &= ~0x800;
}
break;
case CPU_AMD:
/* Check if this is a K5 or K6. (family 5) */
- if ((Reg[0] & 0x0F00) == 0x0500)
+ if ((CpuInfo.Eax & 0x0F00) == 0x0500)
{
/* Get the Model Number */
- switch (Reg[0] & 0x00F0)
+ switch (CpuInfo.Eax & 0x00F0)
{
/* Model 1: K5 - 5k86 (initial models) */
case 0x0010:
/* Check if this is Step 0 or 1. They don't support PGE */
- if ((Reg[0] & 0x000F) > 0x03) break;
+ if ((CpuInfo.Eax & 0x000F) > 0x03) break;
/* Model 0: K5 - SSA5 */
case 0x0000:
/* Model 0 doesn't support PGE at all. */
- Reg[3] &= ~0x2000;
+ CpuInfo.Edx &= ~0x2000;
break;
/* Model 8: K6-2 */
case 0x0080:
/* K6-2, Step 8 and over have support for MTRR. */
- if ((Reg[0] & 0x000F) >= 0x8) FeatureBits |= KF_AMDK6MTRR;
+ if ((CpuInfo.Eax & 0x000F) >= 0x8) FeatureBits |= KF_AMDK6MTRR;
break;
/* Model 9: K6-III
break;
}
}
- else if((Reg[0] & 0x0F00) < 0x0500)
+ else if((CpuInfo.Eax & 0x0F00) < 0x0500)
{
/* Families below 5 don't support PGE, PSE or CMOV at all */
- Reg[3] &= ~(0x08 | 0x2000 | 0x8000);
+ CpuInfo.Edx &= ~(0x08 | 0x2000 | 0x8000);
/* They also don't support advanced CPUID functions. */
ExtendedCPUID = FALSE;
case CPU_TRANSMETA:
/* Enable CMPXCHG8B if the family (>= 5), model and stepping (>= 4.2) support it */
- if ((Reg[0] & 0x0FFF) >= 0x0542)
+ if ((CpuInfo.Eax & 0x0FFF) >= 0x0542)
{
- WRMSR(0x80860004, RDMSR(0x80860004) | 0x0100);
+ __writemsr(0x80860004, __readmsr(0x80860004) | 0x0100);
FeatureBits |= KF_CMPXCHG8B;
}
}
/* Set the current features */
- CpuFeatures = Reg[3];
+ CpuFeatures = CpuInfo.Edx;
/* Convert all CPUID Feature bits into our format */
if (CpuFeatures & 0x00000002) FeatureBits |= KF_V86_VIS | KF_CR4;
if (CpuFeatures & 0x10000000)
{
/* Set the number of logical CPUs */
- Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(Reg[1] >> 16);
+ Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(CpuInfo.Ebx >> 16);
if (Prcb->LogicalProcessorsPerPhysicalProcessor > 1)
{
/* We're on dual-core */
if (ExtendedCPUID)
{
/* Do the call */
- CPUID(0x80000000, &Reg[0], &Dummy, &Dummy, &Dummy);
- if ((Reg[0] & 0xffffff00) == 0x80000000)
+ KiCpuId(&CpuInfo, 0x80000000);
+ if ((CpuInfo.Eax & 0xffffff00) == 0x80000000)
{
/* Check if CPUID 0x80000001 is supported */
- if (Reg[0] >= 0x80000001)
+ if (CpuInfo.Eax >= 0x80000001)
{
/* Check which extended features are available. */
- CPUID(0x80000001, &Dummy, &Dummy, &Dummy, &Reg[3]);
+ KiCpuId(&CpuInfo, 0x80000001);
/* Check if NX-bit is supported */
- if (Reg[3] & 0x00100000) FeatureBits |= KF_NX_BIT;
+ if (CpuInfo.Edx & 0x00100000) FeatureBits |= KF_NX_BIT;
/* Now handle each features for each CPU Vendor */
switch (Vendor)
{
case CPU_AMD:
case CPU_CENTAUR:
- if (Reg[3] & 0x80000000) FeatureBits |= KF_3DNOW;
+ if (CpuInfo.Edx & 0x80000000) FeatureBits |= KF_3DNOW;
break;
}
}
return FeatureBits;
}
+INIT_FUNCTION
VOID
NTAPI
-INIT_FUNCTION
KiGetCacheInformation(VOID)
{
PKIPCR Pcr = (PKIPCR)KeGetPcr();
ULONG Vendor;
- ULONG Data[4], Dummy;
+ CPU_INFO CpuInfo;
ULONG CacheRequests = 0, i;
ULONG CurrentRegister;
UCHAR RegisterByte, Associativity = 0;
case CPU_INTEL:
/*Check if we support CPUID 2 */
- CPUID(0, &Data[0], &Dummy, &Dummy, &Dummy);
- if (Data[0] >= 2)
+ KiCpuId(&CpuInfo, 0);
+ if (CpuInfo.Eax >= 2)
{
/* We need to loop for the number of times CPUID will tell us to */
do
{
/* Do the CPUID call */
- CPUID(2, &Data[0], &Data[1], &Data[2], &Data[3]);
+ KiCpuId(&CpuInfo, 2);
/* Check if it was the first call */
if (FirstPass)
* The number of times to loop is the first byte. Read
* it and then destroy it so we don't get confused.
*/
- CacheRequests = Data[0] & 0xFF;
- Data[0] &= 0xFFFFFF00;
+ CacheRequests = CpuInfo.Eax & 0xFF;
+ CpuInfo.Eax &= 0xFFFFFF00;
/* Don't go over this again */
FirstPass = FALSE;
for (i = 0; i < 4; i++)
{
/* Get the current register */
- CurrentRegister = Data[i];
+ CurrentRegister = CpuInfo.AsUINT32[i];
/*
* If the upper bit is set, then this register should
CurrentRegister >>= 8;
if (!RegisterByte) continue;
- /*
- * Valid values are from 0x40 (0 bytes) to 0x49
- * (32MB), or from 0x80 to 0x89 (same size but
- * 8-way associative.
- */
- if (((RegisterByte > 0x40) && (RegisterByte <= 0x47)) ||
- ((RegisterByte > 0x78) && (RegisterByte <= 0x7C)) ||
- ((RegisterByte > 0x80) && (RegisterByte <= 0x85)))
- {
- /* Compute associativity */
- Associativity = 4;
- if (RegisterByte >= 0x79) Associativity = 8;
-
- /* Mask out only the first nibble */
- RegisterByte &= 0x07;
-
- /* Check if this cache is bigger than the last */
- Size = 0x10000 << RegisterByte;
- if ((Size / Associativity) > CurrentSize)
- {
- /* Set the L2 Cache Size and Associativity */
- CurrentSize = Size / Associativity;
- Pcr->SecondLevelCacheSize = Size;
- Pcr->SecondLevelCacheAssociativity = Associativity;
- }
- }
- else if ((RegisterByte > 0x21) && (RegisterByte <= 0x29))
- {
- /* Set minimum cache line size */
- if (CacheLine < 128) CacheLine = 128;
-
- /* Hard-code size/associativity */
- Associativity = 8;
- switch (RegisterByte)
- {
- case 0x22:
- Size = 512 * 1024;
- Associativity = 4;
- break;
-
- case 0x23:
- Size = 1024 * 1024;
- break;
-
- case 0x25:
- Size = 2048 * 1024;
- break;
-
- case 0x29:
- Size = 4096 * 1024;
- break;
-
- default:
- Size = 0;
- break;
- }
-
- /* Check if this cache is bigger than the last */
- if ((Size / Associativity) > CurrentSize)
- {
- /* Set the L2 Cache Size and Associativity */
- CurrentSize = Size / Associativity;
- Pcr->SecondLevelCacheSize = Size;
- Pcr->SecondLevelCacheAssociativity = Associativity;
- }
- }
- else if (((RegisterByte > 0x65) && (RegisterByte < 0x69)) ||
- (RegisterByte == 0x2C) || (RegisterByte == 0xF0))
- {
- /* Indicates L1 cache line of 64 bytes */
- KePrefetchNTAGranularity = 64;
- }
- else if (RegisterByte == 0xF1)
+ Size = 0;
+ switch (RegisterByte)
{
- /* Indicates L1 cache line of 128 bytes */
- KePrefetchNTAGranularity = 128;
+ case 0x06:
+ case 0x08:
+ KePrefetchNTAGranularity = 32;
+ break;
+ case 0x09:
+ KePrefetchNTAGranularity = 64;
+ break;
+ case 0x0a:
+ case 0x0c:
+ KePrefetchNTAGranularity = 32;
+ break;
+ case 0x0d:
+ case 0x0e:
+ KePrefetchNTAGranularity = 64;
+ break;
+ case 0x1d:
+ Size = 128 * 1024;
+ Associativity = 2;
+ break;
+ case 0x21:
+ Size = 256 * 1024;
+ Associativity = 8;
+ break;
+ case 0x24:
+ Size = 1024 * 1024;
+ Associativity = 16;
+ break;
+ case 0x2c:
+ case 0x30:
+ KePrefetchNTAGranularity = 64;
+ break;
+ case 0x41:
+ case 0x42:
+ case 0x43:
+ case 0x44:
+ case 0x45:
+ Size = (1 << (RegisterByte - 0x41)) * 128 * 1024;
+ Associativity = 4;
+ break;
+ case 0x48:
+ Size = 3 * 1024 * 1024;
+ Associativity = 12;
+ break;
+ case 0x49:
+ Size = 4 * 1024 * 1024;
+ Associativity = 16;
+ break;
+ case 0x4e:
+ Size = 6 * 1024 * 1024;
+ Associativity = 24;
+ break;
+ case 0x60:
+ case 0x66:
+ case 0x67:
+ case 0x68:
+ KePrefetchNTAGranularity = 64;
+ break;
+ case 0x78:
+ Size = 1024 * 1024;
+ Associativity = 4;
+ break;
+ case 0x79:
+ case 0x7a:
+ case 0x7b:
+ case 0x7c:
+ case 0x7d:
+ Size = (1 << (RegisterByte - 0x79)) * 128 * 1024;
+ Associativity = 8;
+ break;
+ case 0x7f:
+ Size = 512 * 1024;
+ Associativity = 2;
+ break;
+ case 0x80:
+ Size = 512 * 1024;
+ Associativity = 8;
+ break;
+ case 0x82:
+ case 0x83:
+ case 0x84:
+ case 0x85:
+ Size = (1 << (RegisterByte - 0x82)) * 256 * 1024;
+ Associativity = 8;
+ break;
+ case 0x86:
+ Size = 512 * 1024;
+ Associativity = 4;
+ break;
+ case 0x87:
+ Size = 1024 * 1024;
+ Associativity = 8;
+ break;
+ case 0xf0:
+ KePrefetchNTAGranularity = 64;
+ break;
+ case 0xf1:
+ KePrefetchNTAGranularity = 128;
+ break;
}
- else if (((RegisterByte >= 0x4A) && (RegisterByte <= 0x4C)) ||
- (RegisterByte == 0x78) ||
- (RegisterByte == 0x7D) ||
- (RegisterByte == 0x7F) ||
- (RegisterByte == 0x86) ||
- (RegisterByte == 0x87))
+ if (Size && (Size / Associativity) > CurrentSize)
{
- /* Set minimum cache line size */
- if (CacheLine < 64) CacheLine = 64;
-
- /* Hard-code size/associativity */
- switch (RegisterByte)
- {
- case 0x4A:
- Size = 4 * 1024 * 1024;
- Associativity = 8;
- break;
-
- case 0x4B:
- Size = 6 * 1024 * 1024;
- Associativity = 12;
- break;
-
- case 0x4C:
- Size = 8 * 1024 * 1024;
- Associativity = 16;
- break;
-
- case 0x78:
- Size = 1 * 1024 * 1024;
- Associativity = 4;
- break;
-
- case 0x7D:
- Size = 2 * 1024 * 1024;
- Associativity = 8;
- break;
-
- case 0x7F:
- Size = 512 * 1024;
- Associativity = 2;
- break;
-
- case 0x86:
- Size = 512 * 1024;
- Associativity = 4;
- break;
-
- case 0x87:
- Size = 1 * 1024 * 1024;
- Associativity = 8;
- break;
-
- default:
- Size = 0;
- break;
- }
-
- /* Check if this cache is bigger than the last */
- if ((Size / Associativity) > CurrentSize)
- {
- /* Set the L2 Cache Size and Associativity */
- CurrentSize = Size / Associativity;
- Pcr->SecondLevelCacheSize = Size;
- Pcr->SecondLevelCacheAssociativity = Associativity;
- }
+ /* Set the L2 Cache Size and Associativity */
+ CurrentSize = Size / Associativity;
+ Pcr->SecondLevelCacheSize = Size;
+ Pcr->SecondLevelCacheAssociativity = Associativity;
}
}
}
case CPU_AMD:
/* Check if we support CPUID 0x80000005 */
- CPUID(0x80000000, &Data[0], &Data[1], &Data[2], &Data[3]);
- if (Data[0] >= 0x80000006)
+ KiCpuId(&CpuInfo, 0x80000000);
+ if (CpuInfo.Eax >= 0x80000005)
{
/* Get L1 size first */
- CPUID(0x80000005, &Data[0], &Data[1], &Data[2], &Data[3]);
- KePrefetchNTAGranularity = Data[2] & 0xFF;
+ KiCpuId(&CpuInfo, 0x80000005);
+ KePrefetchNTAGranularity = CpuInfo.Ecx & 0xFF;
/* Check if we support CPUID 0x80000006 */
- CPUID(0x80000000, &Data[0], &Data[1], &Data[2], &Data[3]);
- if (Data[0] >= 0x80000006)
+ KiCpuId(&CpuInfo, 0x80000000);
+ if (CpuInfo.Eax >= 0x80000006)
{
/* Get 2nd level cache and tlb size */
- CPUID(0x80000006, &Data[0], &Data[1], &Data[2], &Data[3]);
+ KiCpuId(&CpuInfo, 0x80000006);
/* Cache line size */
- CacheLine = Data[2] & 0xFF;
+ CacheLine = CpuInfo.Ecx & 0xFF;
/* Hardcode associativity */
- RegisterByte = (Data[2] >> 12) & 0xFF;
+ RegisterByte = (CpuInfo.Ecx >> 12) & 0xFF;
switch (RegisterByte)
{
case 2:
}
/* Compute size */
- Size = (Data[2] >> 16) << 10;
+ Size = (CpuInfo.Ecx >> 16) << 10;
/* Hack for Model 6, Steping 300 */
if ((KeGetCurrentPrcb()->CpuType == 6) &&
/* Set the cache line */
if (CacheLine > KeLargestCacheLine) KeLargestCacheLine = CacheLine;
- DPRINT1("Prefetch Cache: %d bytes\tL2 Cache: %d bytes\tL2 Cache Line: %d bytes\tL2 Cache Associativity: %d\n",
+ DPRINT1("Prefetch Cache: %lu bytes\tL2 Cache: %lu bytes\tL2 Cache Line: %lu bytes\tL2 Cache Associativity: %lu\n",
KePrefetchNTAGranularity,
Pcr->SecondLevelCacheSize,
KeLargestCacheLine,
Pcr->SecondLevelCacheAssociativity);
}
+INIT_FUNCTION
VOID
NTAPI
-INIT_FUNCTION
KiSetCR0Bits(VOID)
{
ULONG Cr0;
__writecr0(Cr0);
}
+INIT_FUNCTION
VOID
NTAPI
-INIT_FUNCTION
KiInitializeTSS2(IN PKTSS Tss,
IN PKGDTENTRY TssEntry OPTIONAL)
{
Tss->Ss0 = KGDT_R0_DATA;
}
+INIT_FUNCTION
VOID
FASTCALL
-INIT_FUNCTION
Ki386InitializeTss(IN PKTSS Tss,
IN PKIDTENTRY Idt,
IN PKGDTENTRY Gdt)
NTAPI
KeFlushCurrentTb(VOID)
{
+
+#if !defined(_GLOBAL_PAGES_ARE_AWESOME_)
+
/* Flush the TLB by resetting CR3 */
__writecr3(__readcr3());
+
+#else
+
+ /* Check if global pages are enabled */
+ if (KeFeatureBits & KF_GLOBAL_PAGE)
+ {
+ ULONG Cr4;
+
+ /* Disable PGE (Note: may not have been enabled yet) */
+ Cr4 = __readcr4();
+ __writecr4(Cr4 & ~CR4_PGE);
+
+ /* Flush everything */
+ __writecr3(__readcr3());
+
+ /* Re-enable PGE */
+ __writecr4(Cr4);
+ }
+ else
+ {
+ /* No global pages, resetting CR3 is enough */
+ __writecr3(__readcr3());
+ }
+
+#endif
+
}
VOID
ProcessorState->SpecialRegisters.Ldtr = Ke386GetLocalDescriptorTable();
}
+INIT_FUNCTION
VOID
NTAPI
-INIT_FUNCTION
KiInitializeMachineType(VOID)
{
/* Set the Machine Type we got from NTLDR */
KeI386MachineType = KeLoaderBlock->u.I386.MachineType & 0x000FF;
}
+INIT_FUNCTION
ULONG_PTR
NTAPI
-INIT_FUNCTION
KiLoadFastSyscallMachineSpecificRegisters(IN ULONG_PTR Context)
{
/* Set CS and ESP */
- WRMSR(0x174, KGDT_R0_CODE);
- WRMSR(0x175, (ULONG_PTR)KeGetCurrentPrcb()->DpcStack);
+ __writemsr(0x174, KGDT_R0_CODE);
+ __writemsr(0x175, (ULONG_PTR)KeGetCurrentPrcb()->DpcStack);
/* Set LSTAR */
- WRMSR(0x176, (ULONG_PTR)KiFastCallEntry);
+ __writemsr(0x176, (ULONG_PTR)KiFastCallEntry);
return 0;
}
+INIT_FUNCTION
VOID
NTAPI
-INIT_FUNCTION
KiRestoreFastSyscallReturnState(VOID)
{
/* Check if the CPU Supports fast system call */
}
}
+INIT_FUNCTION
ULONG_PTR
NTAPI
-INIT_FUNCTION
Ki386EnableDE(IN ULONG_PTR Context)
{
/* Enable DE */
return 0;
}
+INIT_FUNCTION
ULONG_PTR
NTAPI
-INIT_FUNCTION
Ki386EnableFxsr(IN ULONG_PTR Context)
{
/* Enable FXSR */
return 0;
}
+INIT_FUNCTION
ULONG_PTR
NTAPI
-INIT_FUNCTION
Ki386EnableXMMIExceptions(IN ULONG_PTR Context)
{
PKIDTENTRY IdtEntry;
return 0;
}
+INIT_FUNCTION
VOID
NTAPI
-INIT_FUNCTION
KiI386PentiumLockErrataFixup(VOID)
{
KDESCRIPTOR IdtDescriptor = {0, 0, 0};
KiSaveProcessorControlState(&Prcb->ProcessorState);
}
+INIT_FUNCTION
BOOLEAN
NTAPI
-INIT_FUNCTION
KiIsNpxPresent(VOID)
{
ULONG Cr0;
return TRUE;
}
+INIT_FUNCTION
BOOLEAN
NTAPI
-INIT_FUNCTION
KiIsNpxErrataPresent(VOID)
{
static double Value1 = 4195835.0, Value2 = 3145727.0;
{
PFNSAVE_FORMAT FpState;
ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);
- DPRINT1("%s is not really implemented\n", __FUNCTION__);
+ UNIMPLEMENTED_ONCE;
/* check if we are doing software emulation */
if (!KeI386NpxPresent) return STATUS_ILLEGAL_FLOAT_CONTEXT;
#else
__asm
{
- fnsave [FpState]
+ mov eax, [FpState]
+ fnsave [eax]
};
#endif
{
PFNSAVE_FORMAT FpState = *((PVOID *) Save);
ASSERT(KeGetCurrentThread()->Header.NpxIrql == KeGetCurrentIrql());
- DPRINT1("%s is not really implemented\n", __FUNCTION__);
+ UNIMPLEMENTED_ONCE;
#ifdef __GNUC__
asm volatile("fnclex\n\t");
__asm
{
fnclex
- frstor [FpState]
+ mov eax, [FpState]
+ frstor [eax]
};
#endif
if (TargetAffinity)
{
/* Sanity check */
- ASSERT(Prcb == (volatile PKPRCB)KeGetCurrentPrcb());
+ ASSERT(Prcb == KeGetCurrentPrcb());
/* FIXME: TODO */
ASSERTMSG("Not yet implemented\n", FALSE);
projects / reactos.git / blobdiff