return __readmsr(Register);
}
+/* NSC/Cyrix CPU configuration register index */
+#define CX86_CCR1 0xc1
+
+/* NSC/Cyrix CPU indexed register access macros */
+#define getCx86(reg) ({ WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x22,(reg)); READ_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x23); })
+
+#define setCx86(reg, data) do { \
+ WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x22,(reg)); \
+ WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x23,(data)); \
+} while (0)
+
/* FUNCTIONS *****************************************************************/
VOID
NTAPI
+INIT_FUNCTION
KiSetProcessorType(VOID)
{
ULONG EFlags, NewEFlags;
ULONG
NTAPI
+INIT_FUNCTION
KiGetCpuVendor(VOID)
{
PKPRCB Prcb = KeGetCurrentPrcb();
ULONG
NTAPI
+INIT_FUNCTION
KiGetFeatureBits(VOID)
{
PKPRCB Prcb = KeGetCurrentPrcb();
ULONG Vendor;
ULONG FeatureBits = KF_WORKING_PTE;
- ULONG Reg[4], Dummy;
+ ULONG Reg[4], Dummy, Ccr1;
BOOLEAN ExtendedCPUID = TRUE;
ULONG CpuFeatures = 0;
/* Cyrix CPUs */
case CPU_CYRIX:
- /* FIXME: CMPXCGH8B */
+ /* Workaround the "COMA" bug on 6x family of Cyrix CPUs */
+ if (Prcb->CpuType == 6 &&
+ Prcb->CpuStep <= 1)
+ {
+ /* Get CCR1 value */
+ Ccr1 = getCx86(CX86_CCR1);
+
+ /* Enable the NO_LOCK bit */
+ Ccr1 |= 0x10;
+
+ /* Set the new CCR1 value */
+ setCx86(CX86_CCR1, Ccr1);
+ }
+
+ /* Set the current features */
+ CpuFeatures = Reg[3];
break;
VOID
NTAPI
+INIT_FUNCTION
KiGetCacheInformation(VOID)
{
PKIPCR Pcr = (PKIPCR)KeGetPcr();
VOID
NTAPI
+INIT_FUNCTION
KiSetCR0Bits(VOID)
{
ULONG Cr0;
VOID
NTAPI
+INIT_FUNCTION
KiInitializeTSS2(IN PKTSS Tss,
IN PKGDTENTRY TssEntry OPTIONAL)
{
VOID
FASTCALL
+INIT_FUNCTION
Ki386InitializeTss(IN PKTSS Tss,
IN PKIDTENTRY Idt,
IN PKGDTENTRY Gdt)
VOID
NTAPI
+INIT_FUNCTION
KiInitializeMachineType(VOID)
{
/* Set the Machine Type we got from NTLDR */
ULONG_PTR
NTAPI
+INIT_FUNCTION
KiLoadFastSyscallMachineSpecificRegisters(IN ULONG_PTR Context)
{
/* Set CS and ESP */
VOID
NTAPI
+INIT_FUNCTION
KiRestoreFastSyscallReturnState(VOID)
{
/* Check if the CPU Supports fast system call */
ULONG_PTR
NTAPI
+INIT_FUNCTION
Ki386EnableDE(IN ULONG_PTR Context)
{
/* Enable DE */
ULONG_PTR
NTAPI
+INIT_FUNCTION
Ki386EnableFxsr(IN ULONG_PTR Context)
{
/* Enable FXSR */
ULONG_PTR
NTAPI
+INIT_FUNCTION
Ki386EnableXMMIExceptions(IN ULONG_PTR Context)
{
PKIDTENTRY IdtEntry;
VOID
NTAPI
+INIT_FUNCTION
KiI386PentiumLockErrataFixup(VOID)
{
KDESCRIPTOR IdtDescriptor;
BOOLEAN
NTAPI
+INIT_FUNCTION
KiIsNpxPresent(VOID)
{
ULONG Cr0;
BOOLEAN
NTAPI
+INIT_FUNCTION
KiIsNpxErrataPresent(VOID)
{
BOOLEAN ErrataPresent;