BOOLEAN
MempSetupPaging(IN PFN_NUMBER StartPage,
- IN PFN_COUNT NumberOfPages)
+ IN PFN_NUMBER NumberOfPages,
+ IN BOOLEAN KernelMapping)
{
return TRUE;
}
PHARDWARE_PDE_ARMV6 PointerPde;
PHARDWARE_LARGE_PTE_ARMV6 LargePte;
PFN_NUMBER Pfn;
-
+
/* Setup the Startup PDE */
LargePte = &PdrPage->PageDir.Pte[StartupPdePageTableIndex];
TempLargePte.PageFrameNumber = PaToLargePfn((ULONG_PTR)&PdrPage->PageDir);
*LargePte = TempLargePte;
-
+
/* Map-in the PDR */
LargePte = &PdrPage->PageDir.Pte[PdrPageTableIndex];
*LargePte = TempLargePte;
*PointerPde++ = TempPde;
}
- /*
+ /*
* Now map these page tables in PTE space (MiAddressToPte(PTE_BASE)).
* Note that they all live on a single page, since each is 1KB.
*/
TempPte.PageFrameNumber = 0;
*PointerPte = TempPte;
- /* TODO: Map in the kernel CPTs */
+ /* TODO: Map in the kernel CPTs */
return TRUE;
}
LoaderBlock->u.Arm.SecondLevelDcacheFillSize = SecondLevelDcacheFillSize;
LoaderBlock->u.Arm.SecondLevelIcacheSize = SecondLevelIcacheSize;
LoaderBlock->u.Arm.SecondLevelIcacheFillSize = SecondLevelIcacheSize;
-
+
/* Write initial context information */
LoaderBlock->KernelStack = (ULONG_PTR)PdrPage->KernelStack;
LoaderBlock->KernelStack += KERNEL_STACK_SIZE;
}
VOID
-WinLdrSetProcessorContext(PVOID GdtIdt,
- IN ULONG Pcr,
- IN ULONG Tss)
-{
+WinLdrSetProcessorContext(VOID)
+{
ARM_CONTROL_REGISTER ControlRegister;
ARM_TTB_REGISTER TtbRegister;
ARM_DOMAIN_REGISTER DomainRegister;
-
+
/* Set the TTBR */
TtbRegister.AsUlong = (ULONG_PTR)&PdrPage->PageDir;
ASSERT(TtbRegister.Reserved == 0);
ControlRegister.DCacheEnabled = TRUE;
ControlRegister.ForceAp = TRUE;
ControlRegister.ExtendedPageTables = TRUE;
- KeArmControlRegisterSet(ControlRegister);
+ KeArmControlRegisterSet(ControlRegister);
+}
+
+VOID
+WinLdrSetupMachineDependent(
+ PLOADER_PARAMETER_BLOCK LoaderBlock)
+{
+}
+
+VOID DiskStopFloppyMotor(VOID)
+{
+}
+
+VOID
+RealEntryPoint(VOID)
+{
+ BootMain("");
+}
+
+VOID
+NTAPI
+FrLdrBugCheckWithMessage(
+ ULONG BugCode,
+ PCHAR File,
+ ULONG Line,
+ PSTR Format,
+ ...)
+{
+
}