Can't sleep so write more source codes! add scan bus functions to get power caps...

[reactos.git] / reactos / drivers / bus / pcix / pci.h

diff --git a/reactos/drivers/bus/pcix/pci.h b/reactos/drivers/bus/pcix/pci.h
index becc9d5..327cce1 100644 (file)
--- a/reactos/drivers/bus/pcix/pci.h
+++ b/reactos/drivers/bus/pcix/pci.h
@@ -57,11 +57,21 @@
 #define PCI_INTERFACE_ROOT                  0x04
 
 //
-// PCI Skip Function FLags
+// PCI Skip Function Flags
 //
 #define PCI_SKIP_DEVICE_ENUMERATION         0x01
 #define PCI_SKIP_RESOURCE_ENUMERATION       0x02
 
+//
+// PCI Debugging Device Support
+//
+#define MAX_DEBUGGING_DEVICES_SUPPORTED     0x04
+
+//
+// PCI Driver Verifier Failures
+//
+#define PCI_VERIFIER_CODES                  0x04
+ 
 //
 // Device Extension, Interface, Translator and Arbiter Signatures
 //
@@ -197,8 +207,8 @@ typedef struct _PCI_FDO_EXTENSION
 
 typedef struct _PCI_FUNCTION_RESOURCES
 {
-    IO_RESOURCE_DESCRIPTOR Limit[7];                                               
-    CM_PARTIAL_RESOURCE_DESCRIPTOR Current[7];                                     
+    IO_RESOURCE_DESCRIPTOR Limit[7];
+    CM_PARTIAL_RESOURCE_DESCRIPTOR Current[7];
 } PCI_FUNCTION_RESOURCES, *PPCI_FUNCTION_RESOURCES;
 
 typedef union _PCI_HEADER_TYPE_DEPENDENT
@@ -231,7 +241,7 @@ typedef struct _PCI_PDO_EXTENSION
     struct _PCI_MJ_DISPATCH_TABLE *IrpDispatchTable;
     BOOLEAN DeviceState;
     BOOLEAN TentativeNextState;
-   
+
     KEVENT SecondaryExtLock;
     PCI_SLOT_NUMBER Slot;
     PDEVICE_OBJECT PhysicalDeviceObject;
@@ -288,7 +298,7 @@ typedef struct _PCI_PDO_EXTENSION
 typedef NTSTATUS (NTAPI *PCI_DISPATCH_FUNCTION)(
     IN PIRP Irp,
     IN PIO_STACK_LOCATION IoStackLocation,
-    IN PPCI_FDO_EXTENSION DeviceExtension
+    IN PVOID DeviceExtension
 );
 
 //
@@ -370,6 +380,17 @@ typedef struct PCI_ARBITER_INSTANCE
     //ARBITER_INSTANCE CommonInstance; FIXME: Need Arbiter Headers
 } PCI_ARBITER_INSTANCE, *PPCI_ARBITER_INSTANCE;
 
+//
+// PCI Verifier Data
+//
+typedef struct _PCI_VERIFIER_DATA
+{
+    ULONG FailureCode;
+    VF_FAILURE_CLASS FailureClass;
+    ULONG AssertionControl;
+    PCHAR DebuggerMessageText;
+} PCI_VERIFIER_DATA, *PPCI_VERIFIER_DATA;
+
 //
 // IRP Dispatch Routines
 //
@@ -402,6 +423,14 @@ PciCallDownIrpStack(
     IN PIRP Irp
 );
 
+NTSTATUS
+NTAPI
+PciIrpInvalidDeviceRequest(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_FDO_EXTENSION DeviceExtension
+);
+
 //
 // Power Routines
 //
@@ -429,6 +458,14 @@ PciFdoIrpQueryPower(
     IN PPCI_FDO_EXTENSION DeviceExtension
 );
 
+NTSTATUS
+NTAPI
+PciSetPowerManagedDevicePowerState(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN DEVICE_POWER_STATE DeviceState,
+    IN BOOLEAN IrpSet
+);
+
 //
 // Bus FDO Routines
 //
@@ -543,6 +580,210 @@ PciFdoIrpQueryLegacyBusInformation(
     IN PPCI_FDO_EXTENSION DeviceExtension
 );
 
+//
+// Device PDO Routines
+//
+NTSTATUS
+NTAPI
+PciPdoCreate(
+    IN PPCI_FDO_EXTENSION DeviceExtension,
+    IN PCI_SLOT_NUMBER Slot,
+    OUT PDEVICE_OBJECT *PdoDeviceObject
+);
+
+NTSTATUS
+NTAPI
+PciPdoWaitWake(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoSetPowerState(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryPower(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpStartDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryRemoveDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpRemoveDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpCancelRemoveDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpStopDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryStopDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpCancelStopDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryDeviceRelations(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryInterface(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryCapabilities(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryResources(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryResourceRequirements(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryDeviceText(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpReadConfig(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpWriteConfig(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryId(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryDeviceState(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryBusInformation(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpDeviceUsageNotification(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpSurpriseRemoval(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryLegacyBusInformation(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+
 //
 // HAL Callback/Hook Routines
 //
@@ -561,6 +802,12 @@ PciVerifierInit(
     IN PDRIVER_OBJECT DriverObject
 );
 
+PPCI_VERIFIER_DATA
+NTAPI
+PciVerifierRetrieveFailureData(
+    IN ULONG FailureCode
+);
+
 //
 // Utility Routines
 //
@@ -688,6 +935,45 @@ PciIsCriticalDeviceClass(
     IN UCHAR SubClass
 );
 
+BOOLEAN
+NTAPI
+PciIsDeviceOnDebugPath(
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciGetBiosConfig(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    OUT PPCI_COMMON_HEADER PciData
+);
+
+NTSTATUS
+NTAPI
+PciSaveBiosConfig(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    OUT PPCI_COMMON_HEADER PciData
+);
+
+UCHAR
+NTAPI
+PciReadDeviceCapability(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN UCHAR Offset,
+    IN ULONG CapabilityId,
+    OUT PPCI_CAPABILITIES_HEADER Buffer,
+    IN ULONG Length
+);
+
+BOOLEAN
+NTAPI
+PciCanDisableDecodes(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN PPCI_COMMON_HEADER Config,
+    IN ULONGLONG HackFlags,
+    IN BOOLEAN ForPowerDown
+);
+
 //
 // Configuration Routines
 //
@@ -707,6 +993,30 @@ PciReadSlotConfig(
     IN ULONG Length
 );
 
+VOID
+NTAPI
+PciWriteDeviceConfig(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN PVOID Buffer,
+    IN ULONG Offset,
+    IN ULONG Length
+);
+
+VOID
+NTAPI
+PciReadDeviceConfig(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN PVOID Buffer,
+    IN ULONG Offset,
+    IN ULONG Length
+);
+
+UCHAR
+NTAPI
+PciGetAdjustedInterruptLine(
+    IN PPCI_PDO_EXTENSION PdoExtension
+);
+
 //
 // State Machine Logic Transition Routines
 //