- Add support for PnP IRP to PDO: IRP_MN_QUERY_BUS_INFORMATION (PciQueryBusInformatio...

[reactos.git] / reactos / drivers / bus / pcix / pci.h

diff --git a/reactos/drivers/bus/pcix/pci.h b/reactos/drivers/bus/pcix/pci.h
index 8c6797d..87b1c44 100644 (file)
--- a/reactos/drivers/bus/pcix/pci.h
+++ b/reactos/drivers/bus/pcix/pci.h
@@ -56,6 +56,34 @@
 #define PCI_INTERFACE_FDO                   0x02
 #define PCI_INTERFACE_ROOT                  0x04
 
+//
+// PCI Skip Function Flags
+//
+#define PCI_SKIP_DEVICE_ENUMERATION         0x01
+#define PCI_SKIP_RESOURCE_ENUMERATION       0x02
+
+//
+// PCI Apply Hack Flags
+//
+#define PCI_HACK_FIXUP_BEFORE_CONFIGURATION 0x00
+#define PCI_HACK_FIXUP_AFTER_CONFIGURATION  0x01
+#define PCI_HACK_FIXUP_BEFORE_UPDATE        0x03
+
+//
+// PCI Debugging Device Support
+//
+#define MAX_DEBUGGING_DEVICES_SUPPORTED     0x04
+
+//
+// PCI Driver Verifier Failures
+//
+#define PCI_VERIFIER_CODES                  0x04
+
+//
+// PCI ID Buffer ANSI Strings
+//
+#define MAX_ANSI_STRINGS                    0x08
+
 //
 // Device Extension, Interface, Translator and Arbiter Signatures
 //
@@ -79,6 +107,18 @@ typedef enum _PCI_SIGNATURE
     PciInterface_Location  = 'icP?'
 } PCI_SIGNATURE, *PPCI_SIGNATURE;
 
+//
+// Driver-handled PCI Device Types
+//
+typedef enum _PCI_DEVICE_TYPES
+{
+    PciTypeInvalid,
+    PciTypeHostBridge,
+    PciTypePciBridge,
+    PciTypeCardbusBridge,
+    PciTypeDevice
+} PCI_DEVICE_TYPES;
+
 //
 // Device Extension Logic States
 //
@@ -191,8 +231,8 @@ typedef struct _PCI_FDO_EXTENSION
 
 typedef struct _PCI_FUNCTION_RESOURCES
 {
-    IO_RESOURCE_DESCRIPTOR Limit[7];                                               
-    CM_PARTIAL_RESOURCE_DESCRIPTOR Current[7];                                     
+    IO_RESOURCE_DESCRIPTOR Limit[7];
+    CM_PARTIAL_RESOURCE_DESCRIPTOR Current[7];
 } PCI_FUNCTION_RESOURCES, *PPCI_FUNCTION_RESOURCES;
 
 typedef union _PCI_HEADER_TYPE_DEPENDENT
@@ -225,7 +265,7 @@ typedef struct _PCI_PDO_EXTENSION
     struct _PCI_MJ_DISPATCH_TABLE *IrpDispatchTable;
     BOOLEAN DeviceState;
     BOOLEAN TentativeNextState;
-   
+
     KEVENT SecondaryExtLock;
     PCI_SLOT_NUMBER Slot;
     PDEVICE_OBJECT PhysicalDeviceObject;
@@ -282,7 +322,7 @@ typedef struct _PCI_PDO_EXTENSION
 typedef NTSTATUS (NTAPI *PCI_DISPATCH_FUNCTION)(
     IN PIRP Irp,
     IN PIO_STACK_LOCATION IoStackLocation,
-    IN PPCI_FDO_EXTENSION DeviceExtension
+    IN PVOID DeviceExtension
 );
 
 //
@@ -364,6 +404,113 @@ typedef struct PCI_ARBITER_INSTANCE
     //ARBITER_INSTANCE CommonInstance; FIXME: Need Arbiter Headers
 } PCI_ARBITER_INSTANCE, *PPCI_ARBITER_INSTANCE;
 
+//
+// PCI Verifier Data
+//
+typedef struct _PCI_VERIFIER_DATA
+{
+    ULONG FailureCode;
+    VF_FAILURE_CLASS FailureClass;
+    ULONG AssertionControl;
+    PCHAR DebuggerMessageText;
+} PCI_VERIFIER_DATA, *PPCI_VERIFIER_DATA;
+
+//
+// PCI ID Buffer Descriptor
+//
+typedef struct _PCI_ID_BUFFER
+{
+    ULONG Count;
+    ANSI_STRING Strings[MAX_ANSI_STRINGS];
+    ULONG StringSize[MAX_ANSI_STRINGS];
+    ULONG TotalLength;
+    PCHAR CharBuffer;
+    CHAR BufferData[256];
+} PCI_ID_BUFFER, *PPCI_ID_BUFFER;
+
+//
+// PCI Configuration Callbacks
+//
+struct _PCI_CONFIGURATOR_CONTEXT;
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_INITIALIZE)(
+    IN struct _PCI_CONFIGURATOR_CONTEXT* Context
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_RESTORE_CURRENT)(
+    IN struct _PCI_CONFIGURATOR_CONTEXT* Context
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_SAVE_LIMITS)(
+    IN struct _PCI_CONFIGURATOR_CONTEXT* Context
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_SAVE_CURRENT_SETTINGS)(
+    IN struct _PCI_CONFIGURATOR_CONTEXT* Context
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_CHANGE_RESOURCE_SETTINGS)(
+    IN struct _PCI_CONFIGURATOR_CONTEXT* Context
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_GET_ADDITIONAL_RESOURCE_DESCRIPTORS)(
+    IN struct _PCI_CONFIGURATOR_CONTEXT* Context,
+    IN PPCI_COMMON_HEADER PciData,
+    IN PIO_RESOURCE_DESCRIPTOR IoDescriptor
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_RESET_DEVICE)(
+    IN struct _PCI_CONFIGURATOR_CONTEXT* Context
+);
+
+//
+// PCI Configurator
+//
+typedef struct _PCI_CONFIGURATOR
+{
+    PCI_CONFIGURATOR_INITIALIZE Initialize;
+    PCI_CONFIGURATOR_RESTORE_CURRENT RestoreCurrent;
+    PCI_CONFIGURATOR_SAVE_LIMITS SaveLimits;
+    PCI_CONFIGURATOR_SAVE_CURRENT_SETTINGS SaveCurrentSettings;
+    PCI_CONFIGURATOR_CHANGE_RESOURCE_SETTINGS ChangeResourceSettings;
+    PCI_CONFIGURATOR_GET_ADDITIONAL_RESOURCE_DESCRIPTORS GetAdditionalResourceDescriptors;
+    PCI_CONFIGURATOR_RESET_DEVICE ResetDevice;
+} PCI_CONFIGURATOR, *PPCI_CONFIGURATOR;
+
+//
+// PCI Configurator Context
+//
+typedef struct _PCI_CONFIGURATOR_CONTEXT
+{
+    PPCI_PDO_EXTENSION PdoExtension;
+    PPCI_COMMON_HEADER Current;
+    PPCI_COMMON_HEADER PciData;
+    PPCI_CONFIGURATOR Configurator;
+    USHORT SecondaryStatus;
+    USHORT Status;
+    USHORT Command;
+} PCI_CONFIGURATOR_CONTEXT, *PPCI_CONFIGURATOR_CONTEXT;
+
+//
+// PCI IPI Function
+//
+typedef VOID (NTAPI *PCI_IPI_FUNCTION)(
+    IN PVOID Reserved,
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+//
+// PCI IPI Context
+//
+typedef struct _PCI_IPI_CONTEXT
+{
+    LONG RunCount;
+    ULONG Barrier;
+    PPCI_PDO_EXTENSION PdoExtension;
+    PCI_IPI_FUNCTION Function;
+    PVOID Context;
+} PCI_IPI_CONTEXT, *PPCI_IPI_CONTEXT;
+
 //
 // IRP Dispatch Routines
 //
@@ -396,6 +543,14 @@ PciCallDownIrpStack(
     IN PIRP Irp
 );
 
+NTSTATUS
+NTAPI
+PciIrpInvalidDeviceRequest(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_FDO_EXTENSION DeviceExtension
+);
+
 //
 // Power Routines
 //
@@ -423,6 +578,14 @@ PciFdoIrpQueryPower(
     IN PPCI_FDO_EXTENSION DeviceExtension
 );
 
+NTSTATUS
+NTAPI
+PciSetPowerManagedDevicePowerState(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN DEVICE_POWER_STATE DeviceState,
+    IN BOOLEAN IrpSet
+);
+
 //
 // Bus FDO Routines
 //
@@ -537,6 +700,210 @@ PciFdoIrpQueryLegacyBusInformation(
     IN PPCI_FDO_EXTENSION DeviceExtension
 );
 
+//
+// Device PDO Routines
+//
+NTSTATUS
+NTAPI
+PciPdoCreate(
+    IN PPCI_FDO_EXTENSION DeviceExtension,
+    IN PCI_SLOT_NUMBER Slot,
+    OUT PDEVICE_OBJECT *PdoDeviceObject
+);
+
+NTSTATUS
+NTAPI
+PciPdoWaitWake(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoSetPowerState(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryPower(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpStartDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryRemoveDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpRemoveDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpCancelRemoveDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpStopDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryStopDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpCancelStopDevice(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryDeviceRelations(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryInterface(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryCapabilities(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryResources(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryResourceRequirements(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryDeviceText(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpReadConfig(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpWriteConfig(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryId(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryDeviceState(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryBusInformation(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpDeviceUsageNotification(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpSurpriseRemoval(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciPdoIrpQueryLegacyBusInformation(
+    IN PIRP Irp,
+    IN PIO_STACK_LOCATION IoStackLocation,
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+
 //
 // HAL Callback/Hook Routines
 //
@@ -555,6 +922,12 @@ PciVerifierInit(
     IN PDRIVER_OBJECT DriverObject
 );
 
+PPCI_VERIFIER_DATA
+NTAPI
+PciVerifierRetrieveFailureData(
+    IN ULONG FailureCode
+);
+
 //
 // Utility Routines
 //
@@ -657,6 +1030,119 @@ PciFindNextSecondaryExtension(
     IN PCI_SIGNATURE ExtensionType
 );
 
+ULONGLONG
+NTAPI
+PciGetHackFlags(
+    IN USHORT VendorId,
+    IN USHORT DeviceId,
+    IN USHORT SubVendorId,
+    IN USHORT SubSystemId,
+    IN UCHAR RevisionId
+);
+
+PPCI_PDO_EXTENSION
+NTAPI
+PciFindPdoByFunction(
+    IN PPCI_FDO_EXTENSION DeviceExtension,
+    IN ULONG FunctionNumber,
+    IN PPCI_COMMON_HEADER PciData
+);
+
+BOOLEAN
+NTAPI
+PciIsCriticalDeviceClass(
+    IN UCHAR BaseClass,
+    IN UCHAR SubClass
+);
+
+BOOLEAN
+NTAPI
+PciIsDeviceOnDebugPath(
+    IN PPCI_PDO_EXTENSION DeviceExtension
+);
+
+NTSTATUS
+NTAPI
+PciGetBiosConfig(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    OUT PPCI_COMMON_HEADER PciData
+);
+
+NTSTATUS
+NTAPI
+PciSaveBiosConfig(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    OUT PPCI_COMMON_HEADER PciData
+);
+
+UCHAR
+NTAPI
+PciReadDeviceCapability(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN UCHAR Offset,
+    IN ULONG CapabilityId,
+    OUT PPCI_CAPABILITIES_HEADER Buffer,
+    IN ULONG Length
+);
+
+BOOLEAN
+NTAPI
+PciCanDisableDecodes(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN PPCI_COMMON_HEADER Config,
+    IN ULONGLONG HackFlags,
+    IN BOOLEAN ForPowerDown
+);
+
+PCI_DEVICE_TYPES
+NTAPI
+PciClassifyDeviceType(
+    IN PPCI_PDO_EXTENSION PdoExtension
+);
+
+ULONG_PTR
+NTAPI
+PciExecuteCriticalSystemRoutine(
+    IN ULONG_PTR IpiContext
+);
+
+BOOLEAN
+NTAPI
+PciCreateIoDescriptorFromBarLimit(
+    PIO_RESOURCE_DESCRIPTOR ResourceDescriptor,
+    IN PULONG BarArray,
+    IN BOOLEAN Rom
+);
+
+BOOLEAN
+NTAPI
+PciIsSlotPresentInParentMethod(
+    IN PPCI_PDO_EXTENSION PdoExtension,
+    IN ULONG Method
+);
+
+VOID
+NTAPI
+PciDecodeEnable(
+    IN PPCI_PDO_EXTENSION PdoExtension,
+    IN BOOLEAN Enable,
+    OUT PUSHORT Command
+);
+
+NTSTATUS
+NTAPI
+PciQueryBusInformation(
+    IN PPCI_PDO_EXTENSION PdoExtension,
+    IN PPNP_BUS_INFORMATION* Buffer
+);
+
+NTSTATUS
+NTAPI
+PciQueryCapabilities(
+    IN PPCI_PDO_EXTENSION PdoExtension,
+    IN OUT PDEVICE_CAPABILITIES DeviceCapability
+);
+
 //
 // Configuration Routines
 //
@@ -676,6 +1162,30 @@ PciReadSlotConfig(
     IN ULONG Length
 );
 
+VOID
+NTAPI
+PciWriteDeviceConfig(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN PVOID Buffer,
+    IN ULONG Offset,
+    IN ULONG Length
+);
+
+VOID
+NTAPI
+PciReadDeviceConfig(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN PVOID Buffer,
+    IN ULONG Offset,
+    IN ULONG Length
+);
+
+UCHAR
+NTAPI
+PciGetAdjustedInterruptLine(
+    IN PPCI_PDO_EXTENSION PdoExtension
+);
+
 //
 // State Machine Logic Transition Routines
 //
@@ -706,7 +1216,6 @@ PciCommitStateTransition(
     IN PCI_STATE NewState
 );
 
-
 //
 // Arbiter Support
 //
@@ -740,6 +1249,12 @@ PciDebugDumpCommonConfig(
     IN PPCI_COMMON_HEADER PciData
 );
 
+VOID
+NTAPI
+PciDebugDumpQueryCapabilities(
+    IN PDEVICE_CAPABILITIES DeviceCaps
+);
+
 //
 // Interface Support
 //
@@ -893,6 +1408,12 @@ ario_Constructor(
     IN PINTERFACE Interface
 );
 
+VOID
+NTAPI
+ario_ApplyBrokenVideoHack(
+    IN PPCI_FDO_EXTENSION FdoExtension
+);
+
 NTSTATUS
 NTAPI
 pcicbintrf_Constructor(
@@ -969,6 +1490,34 @@ PciQueryDeviceRelations(
     IN OUT PDEVICE_RELATIONS *pDeviceRelations
 );
 
+NTSTATUS
+NTAPI
+PciQueryResources(
+    IN PPCI_PDO_EXTENSION PdoExtension,
+    OUT PCM_RESOURCE_LIST *Buffer
+);
+
+NTSTATUS
+NTAPI
+PciQueryTargetDeviceRelations(
+    IN PPCI_PDO_EXTENSION PdoExtension,
+    IN OUT PDEVICE_RELATIONS *pDeviceRelations
+);
+
+NTSTATUS
+NTAPI
+PciQueryEjectionRelations(
+    IN PPCI_PDO_EXTENSION PdoExtension,
+    IN OUT PDEVICE_RELATIONS *pDeviceRelations
+);
+
+NTSTATUS
+NTAPI
+PciQueryRequirements(
+    IN PPCI_PDO_EXTENSION PdoExtension,
+    IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *RequirementsList
+);
+
 //
 // Identification Functions
 //
@@ -979,6 +1528,164 @@ PciGetDeviceDescriptionMessage(
     IN UCHAR SubClass
 );
 
+NTSTATUS
+NTAPI
+PciQueryDeviceText(
+    IN PPCI_PDO_EXTENSION PdoExtension,
+    IN DEVICE_TEXT_TYPE QueryType,
+    IN ULONG Locale,
+    OUT PWCHAR *Buffer
+);
+
+NTSTATUS
+NTAPI
+PciQueryId(
+    IN PPCI_PDO_EXTENSION DeviceExtension,
+    IN BUS_QUERY_ID_TYPE QueryType,
+    OUT PWCHAR *Buffer
+);
+
+//
+// CardBUS Support
+//
+VOID
+NTAPI
+Cardbus_MassageHeaderForLimitsDetermination(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Cardbus_SaveCurrentSettings(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Cardbus_SaveLimits(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Cardbus_RestoreCurrent(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Cardbus_GetAdditionalResourceDescriptors(
+    IN PPCI_CONFIGURATOR_CONTEXT Context,
+    IN PPCI_COMMON_HEADER PciData,
+    IN PIO_RESOURCE_DESCRIPTOR IoDescriptor
+);
+
+VOID
+NTAPI
+Cardbus_ResetDevice(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Cardbus_ChangeResourceSettings(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+//
+// PCI Device Support
+//
+VOID
+NTAPI
+Device_MassageHeaderForLimitsDetermination(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Device_SaveCurrentSettings(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Device_SaveLimits(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Device_RestoreCurrent(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Device_GetAdditionalResourceDescriptors(
+    IN PPCI_CONFIGURATOR_CONTEXT Context,
+    IN PPCI_COMMON_HEADER PciData,
+    IN PIO_RESOURCE_DESCRIPTOR IoDescriptor
+);
+
+VOID
+NTAPI
+Device_ResetDevice(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Device_ChangeResourceSettings(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+//
+// PCI-to-PCI Bridge Device Support
+//
+VOID
+NTAPI
+PPBridge_MassageHeaderForLimitsDetermination(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+PPBridge_SaveCurrentSettings(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+PPBridge_SaveLimits(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+PPBridge_RestoreCurrent(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+PPBridge_GetAdditionalResourceDescriptors(
+    IN PPCI_CONFIGURATOR_CONTEXT Context,
+    IN PPCI_COMMON_HEADER PciData,
+    IN PIO_RESOURCE_DESCRIPTOR IoDescriptor
+);
+
+VOID
+NTAPI
+PPBridge_ResetDevice(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+PPBridge_ChangeResourceSettings(
+    IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
 //
 // External Resources
 //
@@ -1000,5 +1707,13 @@ extern PCI_INTERFACE AgpTargetInterface;
 extern PCI_INTERFACE TranslatorInterfaceInterrupt;
 extern PDRIVER_OBJECT PciDriverObject;
 extern PWATCHDOG_TABLE WdTable;
+extern PPCI_HACK_ENTRY PciHackTable;
+extern BOOLEAN PciAssignBusNumbers;
+extern BOOLEAN PciEnableNativeModeATA;
+extern PPCI_IRQ_ROUTING_TABLE PciIrqRoutingTable;
+extern BOOLEAN PciRunningDatacenter;
+
+/* Exported by NTOS, should this go in the NDK? */
+extern NTSYSAPI BOOLEAN InitSafeBootMode;
 
 /* EOF */