//
#define PCI_VERIFIER_CODES 0x04
+//
+// PCI ID Buffer ANSI Strings
+//
+#define MAX_ANSI_STRINGS 0x08
+
//
// Device Extension, Interface, Translator and Arbiter Signatures
//
PciInterface_Location = 'icP?'
} PCI_SIGNATURE, *PPCI_SIGNATURE;
+//
+// Driver-handled PCI Device Types
+//
+typedef enum _PCI_DEVICE_TYPES
+{
+ PciTypeInvalid,
+ PciTypeHostBridge,
+ PciTypePciBridge,
+ PciTypeCardbusBridge,
+ PciTypeDevice
+} PCI_DEVICE_TYPES;
+
//
// Device Extension Logic States
//
BOOLEAN MovedDevice;
BOOLEAN DisablePowerDown;
BOOLEAN NeedsHotPlugConfiguration;
- BOOLEAN SwitchedIDEToNativeMode;
+ BOOLEAN IDEInNativeMode;
BOOLEAN BIOSAllowsIDESwitchToNativeMode;
BOOLEAN IoSpaceUnderNativeIdeControl;
BOOLEAN OnDebugPath;
+ BOOLEAN IoSpaceNotRequired;
PCI_POWER_STATE PowerState;
PCI_HEADER_TYPE_DEPENDENT Dependent;
ULONGLONG HackFlags;
PCHAR DebuggerMessageText;
} PCI_VERIFIER_DATA, *PPCI_VERIFIER_DATA;
+//
+// PCI ID Buffer Descriptor
+//
+typedef struct _PCI_ID_BUFFER
+{
+ ULONG Count;
+ ANSI_STRING Strings[MAX_ANSI_STRINGS];
+ ULONG StringSize[MAX_ANSI_STRINGS];
+ ULONG TotalLength;
+ PCHAR CharBuffer;
+ CHAR BufferData[256];
+} PCI_ID_BUFFER, *PPCI_ID_BUFFER;
+
+//
+// PCI Configuration Callbacks
+//
+struct _PCI_CONFIGURATOR_CONTEXT;
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_INITIALIZE)(
+ IN struct _PCI_CONFIGURATOR_CONTEXT* Context
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_RESTORE_CURRENT)(
+ IN struct _PCI_CONFIGURATOR_CONTEXT* Context
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_SAVE_LIMITS)(
+ IN struct _PCI_CONFIGURATOR_CONTEXT* Context
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_SAVE_CURRENT_SETTINGS)(
+ IN struct _PCI_CONFIGURATOR_CONTEXT* Context
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_CHANGE_RESOURCE_SETTINGS)(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PPCI_COMMON_HEADER PciData
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_GET_ADDITIONAL_RESOURCE_DESCRIPTORS)(
+ IN struct _PCI_CONFIGURATOR_CONTEXT* Context,
+ IN PPCI_COMMON_HEADER PciData,
+ IN PIO_RESOURCE_DESCRIPTOR IoDescriptor
+);
+
+typedef VOID (NTAPI *PCI_CONFIGURATOR_RESET_DEVICE)(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PPCI_COMMON_HEADER PciData
+);
+
+//
+// PCI Configurator
+//
+typedef struct _PCI_CONFIGURATOR
+{
+ PCI_CONFIGURATOR_INITIALIZE Initialize;
+ PCI_CONFIGURATOR_RESTORE_CURRENT RestoreCurrent;
+ PCI_CONFIGURATOR_SAVE_LIMITS SaveLimits;
+ PCI_CONFIGURATOR_SAVE_CURRENT_SETTINGS SaveCurrentSettings;
+ PCI_CONFIGURATOR_CHANGE_RESOURCE_SETTINGS ChangeResourceSettings;
+ PCI_CONFIGURATOR_GET_ADDITIONAL_RESOURCE_DESCRIPTORS GetAdditionalResourceDescriptors;
+ PCI_CONFIGURATOR_RESET_DEVICE ResetDevice;
+} PCI_CONFIGURATOR, *PPCI_CONFIGURATOR;
+
+//
+// PCI Configurator Context
+//
+typedef struct _PCI_CONFIGURATOR_CONTEXT
+{
+ PPCI_PDO_EXTENSION PdoExtension;
+ PPCI_COMMON_HEADER Current;
+ PPCI_COMMON_HEADER PciData;
+ PPCI_CONFIGURATOR Configurator;
+ USHORT SecondaryStatus;
+ USHORT Status;
+ USHORT Command;
+} PCI_CONFIGURATOR_CONTEXT, *PPCI_CONFIGURATOR_CONTEXT;
+
+//
+// PCI IPI Function
+//
+typedef VOID (NTAPI *PCI_IPI_FUNCTION)(
+ IN PVOID Reserved,
+ IN PVOID Context
+);
+
+//
+// PCI IPI Context
+//
+typedef struct _PCI_IPI_CONTEXT
+{
+ LONG RunCount;
+ ULONG Barrier;
+ PVOID DeviceExtension;
+ PCI_IPI_FUNCTION Function;
+ PVOID Context;
+} PCI_IPI_CONTEXT, *PPCI_IPI_CONTEXT;
+
+//
+// PCI Legacy Device Location Cache
+//
+typedef struct _PCI_LEGACY_DEVICE
+{
+ struct _PCI_LEGACY_DEVICE *Next;
+ PDEVICE_OBJECT DeviceObject;
+ ULONG BusNumber;
+ ULONG SlotNumber;
+ UCHAR InterruptLine;
+ UCHAR InterruptPin;
+ UCHAR BaseClass;
+ UCHAR SubClass;
+ PDEVICE_OBJECT PhysicalDeviceObject;
+ ROUTING_TOKEN RoutingToken;
+ PPCI_PDO_EXTENSION PdoExtension;
+} PCI_LEGACY_DEVICE, *PPCI_LEGACY_DEVICE;
+
//
// IRP Dispatch Routines
//
IN BOOLEAN ForPowerDown
);
+PCI_DEVICE_TYPES
+NTAPI
+PciClassifyDeviceType(
+ IN PPCI_PDO_EXTENSION PdoExtension
+);
+
+ULONG_PTR
+NTAPI
+PciExecuteCriticalSystemRoutine(
+ IN ULONG_PTR IpiContext
+);
+
+BOOLEAN
+NTAPI
+PciCreateIoDescriptorFromBarLimit(
+ PIO_RESOURCE_DESCRIPTOR ResourceDescriptor,
+ IN PULONG BarArray,
+ IN BOOLEAN Rom
+);
+
BOOLEAN
NTAPI
PciIsSlotPresentInParentMethod(
OUT PUSHORT Command
);
+NTSTATUS
+NTAPI
+PciQueryBusInformation(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PPNP_BUS_INFORMATION* Buffer
+);
+
+NTSTATUS
+NTAPI
+PciQueryCapabilities(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN OUT PDEVICE_CAPABILITIES DeviceCapability
+);
+
+PCM_PARTIAL_RESOURCE_DESCRIPTOR
+NTAPI
+PciNextPartialDescriptor(
+ PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor
+);
+
//
// Configuration Routines
//
IN PCI_STATE NewState
);
-
//
// Arbiter Support
//
IN PPCI_COMMON_HEADER PciData
);
+VOID
+NTAPI
+PciDebugDumpQueryCapabilities(
+ IN PDEVICE_CAPABILITIES DeviceCaps
+);
+
+VOID
+NTAPI
+PciDebugPrintIoResReqList(
+ IN PIO_RESOURCE_REQUIREMENTS_LIST Requirements
+);
+
+VOID
+NTAPI
+PciDebugPrintCmResList(
+ IN PCM_RESOURCE_LIST ResourceList
+);
+
+VOID
+NTAPI
+PciDebugPrintPartialResource(
+ IN PCM_PARTIAL_RESOURCE_DESCRIPTOR PartialResource
+);
+
//
// Interface Support
//
IN OUT PDEVICE_RELATIONS *pDeviceRelations
);
+NTSTATUS
+NTAPI
+PciQueryResources(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ OUT PCM_RESOURCE_LIST *Buffer
+);
+
+NTSTATUS
+NTAPI
+PciQueryTargetDeviceRelations(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN OUT PDEVICE_RELATIONS *pDeviceRelations
+);
+
+NTSTATUS
+NTAPI
+PciQueryEjectionRelations(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN OUT PDEVICE_RELATIONS *pDeviceRelations
+);
+
+NTSTATUS
+NTAPI
+PciQueryRequirements(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *RequirementsList
+);
+
+BOOLEAN
+NTAPI
+PciComputeNewCurrentSettings(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PCM_RESOURCE_LIST ResourceList
+);
+
+NTSTATUS
+NTAPI
+PciSetResources(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN BOOLEAN DoReset,
+ IN BOOLEAN SomethingSomethingDarkSide
+);
+
+NTSTATUS
+NTAPI
+PciBuildRequirementsList(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PPCI_COMMON_HEADER PciData,
+ OUT PIO_RESOURCE_REQUIREMENTS_LIST* Buffer
+);
+
//
// Identification Functions
//
IN UCHAR SubClass
);
+NTSTATUS
+NTAPI
+PciQueryDeviceText(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN DEVICE_TEXT_TYPE QueryType,
+ IN ULONG Locale,
+ OUT PWCHAR *Buffer
+);
+
+NTSTATUS
+NTAPI
+PciQueryId(
+ IN PPCI_PDO_EXTENSION DeviceExtension,
+ IN BUS_QUERY_ID_TYPE QueryType,
+ OUT PWCHAR *Buffer
+);
+
+//
+// CardBUS Support
+//
+VOID
+NTAPI
+Cardbus_MassageHeaderForLimitsDetermination(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Cardbus_SaveCurrentSettings(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Cardbus_SaveLimits(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Cardbus_RestoreCurrent(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Cardbus_GetAdditionalResourceDescriptors(
+ IN PPCI_CONFIGURATOR_CONTEXT Context,
+ IN PPCI_COMMON_HEADER PciData,
+ IN PIO_RESOURCE_DESCRIPTOR IoDescriptor
+);
+
+VOID
+NTAPI
+Cardbus_ResetDevice(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PPCI_COMMON_HEADER PciData
+);
+
+VOID
+NTAPI
+Cardbus_ChangeResourceSettings(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PPCI_COMMON_HEADER PciData
+);
+
+//
+// PCI Device Support
+//
+VOID
+NTAPI
+Device_MassageHeaderForLimitsDetermination(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Device_SaveCurrentSettings(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Device_SaveLimits(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Device_RestoreCurrent(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+Device_GetAdditionalResourceDescriptors(
+ IN PPCI_CONFIGURATOR_CONTEXT Context,
+ IN PPCI_COMMON_HEADER PciData,
+ IN PIO_RESOURCE_DESCRIPTOR IoDescriptor
+);
+
+VOID
+NTAPI
+Device_ResetDevice(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PPCI_COMMON_HEADER PciData
+);
+
+VOID
+NTAPI
+Device_ChangeResourceSettings(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PPCI_COMMON_HEADER PciData
+);
+
+//
+// PCI-to-PCI Bridge Device Support
+//
+VOID
+NTAPI
+PPBridge_MassageHeaderForLimitsDetermination(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+PPBridge_SaveCurrentSettings(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+PPBridge_SaveLimits(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+PPBridge_RestoreCurrent(
+ IN PPCI_CONFIGURATOR_CONTEXT Context
+);
+
+VOID
+NTAPI
+PPBridge_GetAdditionalResourceDescriptors(
+ IN PPCI_CONFIGURATOR_CONTEXT Context,
+ IN PPCI_COMMON_HEADER PciData,
+ IN PIO_RESOURCE_DESCRIPTOR IoDescriptor
+);
+
+VOID
+NTAPI
+PPBridge_ResetDevice(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PPCI_COMMON_HEADER PciData
+);
+
+VOID
+NTAPI
+PPBridge_ChangeResourceSettings(
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ IN PPCI_COMMON_HEADER PciData
+);
+
+//
+// Bus Number Routines
+//
+BOOLEAN
+NTAPI
+PciAreBusNumbersConfigured(
+ IN PPCI_PDO_EXTENSION PdoExtension
+);
+
+//
+// Routine Interface
+//
+NTSTATUS
+NTAPI
+PciCacheLegacyDeviceRouting(
+ IN PDEVICE_OBJECT DeviceObject,
+ IN ULONG BusNumber,
+ IN ULONG SlotNumber,
+ IN UCHAR InterruptLine,
+ IN UCHAR InterruptPin,
+ IN UCHAR BaseClass,
+ IN UCHAR SubClass,
+ IN PDEVICE_OBJECT PhysicalDeviceObject,
+ IN PPCI_PDO_EXTENSION PdoExtension,
+ OUT PDEVICE_OBJECT *pFoundDeviceObject
+);
+
//
// External Resources
//
extern PDRIVER_OBJECT PciDriverObject;
extern PWATCHDOG_TABLE WdTable;
extern PPCI_HACK_ENTRY PciHackTable;
+extern BOOLEAN PciAssignBusNumbers;
extern BOOLEAN PciEnableNativeModeATA;
+extern PPCI_IRQ_ROUTING_TABLE PciIrqRoutingTable;
+extern BOOLEAN PciRunningDatacenter;
/* Exported by NTOS, should this go in the NDK? */
extern NTSYSAPI BOOLEAN InitSafeBootMode;