HalpSwitchToRealModeTrapHandlers(VOID)
{
ULONG Handler;
+ PHARDWARE_PTE IdtPte;
+
+ /*
+ * On P5, the first 7 entries of the IDT are write protected to work around
+ * the cmpxchg8b lock errata. Unprotect them here so we can set our custom
+ * invalid op-code handler.
+ */
+ if (KeGetCurrentPrcb()->CpuType == 5)
+ {
+ IdtPte = GetPteAddress(((PKIPCR)KeGetPcr())->IDT);
+ IdtPte->Write = 1;
+
+ /* Flush the TLB by resetting CR3 */
+ __writecr3(__readcr3());
+ }
/* Save the current Invalid Opcode and General Protection Fault Handlers */
HalpGpfHandler = ((((PKIPCR)KeGetPcr())->IDT[13].ExtendedOffset << 16) &
NTAPI
HalpRestoreTrapHandlers(VOID)
{
+ PHARDWARE_PTE IdtPte;
+
/* We're back, restore the handlers we over-wrote */
((PKIPCR)KeGetPcr())->IDT[13].ExtendedOffset =
(USHORT)((HalpGpfHandler >> 16) & 0xFFFF);
((PKIPCR)KeGetPcr())->IDT[6].ExtendedOffset =
(USHORT)((HalpBopHandler >> 16) & 0xFFFF);
((PKIPCR)KeGetPcr())->IDT[6].Offset = (USHORT)HalpBopHandler;
+
+ /* On P5, restore the write protection for the first 7 IDT entries */
+ if (KeGetCurrentPrcb()->CpuType == 5)
+ {
+ IdtPte = GetPteAddress(((PKIPCR)KeGetPcr())->IDT);
+ IdtPte->Write = 0;
+
+ /* Flush the TLB by resetting CR3 */
+ __writecr3(__readcr3());
+ }
}
VOID
Pte = GetPteAddress((PVOID)i);
Pte->Valid = 0;
Pte->Write = 0;
+ Pte->Owner = 0;
Pte->PageFrameNumber = 0;
}
NTAPI
HalpBiosDisplayReset(VOID)
{
- ULONG Flags = 0;
+ ULONG Flags;
/* Disable interrupts */
- Ke386SaveFlags(Flags);
+ Flags = __readeflags();
_disable();
/* Map memory available to the V8086 real-mode code */
HalpUnmapRealModeMemory();
/* Restore interrupts if they were previously enabled */
- Ke386RestoreFlags(Flags);
+ __writeeflags(Flags);
return TRUE;
}