/* INCLUDES *****************************************************************/
#include <hal.h>
+#include <suppress.h>
+
#define NDEBUG
#include <debug.h>
}
RtlClearBit(AdapterObject->MapRegisters,
- CurrentEntry - AdapterObject->MapRegisterBase);
+ (ULONG)(CurrentEntry - AdapterObject->MapRegisterBase));
CurrentEntry->VirtualAddress = VirtualAddress;
CurrentEntry->PhysicalAddress = PhysicalAddress;
if (Controller == 1)
{
/* Set the Request Data */
+ _PRAGMA_WARNING_SUPPRESS(__WARNING_DEREF_NULL_PTR)
WRITE_PORT_UCHAR(&((PDMA1_CONTROL)AdapterBaseVa)->Mode, DmaMode.Byte);
-
+
/* Unmask DMA Channel */
WRITE_PORT_UCHAR(&((PDMA1_CONTROL)AdapterBaseVa)->SingleMask,
AdapterObject->ChannelNumber | DMA_CLEARMASK);
{
/* Set the Request Data */
WRITE_PORT_UCHAR(&((PDMA2_CONTROL)AdapterBaseVa)->Mode, DmaMode.Byte);
-
+
/* Unmask DMA Channel */
WRITE_PORT_UCHAR(&((PDMA2_CONTROL)AdapterBaseVa)->SingleMask,
AdapterObject->ChannelNumber | DMA_CLEARMASK);
ULONG MapRegisterCount;
BOOLEAN WriteToDevice;
} SCATTER_GATHER_CONTEXT, *PSCATTER_GATHER_CONTEXT;
-
+
IO_ALLOCATION_ACTION
NTAPI
SCATTER_GATHER_ELEMENT TempElements[MAX_SG_ELEMENTS];
ULONG ElementCount = 0, RemainingLength = AdapterControlContext->Length;
PUCHAR CurrentVa = AdapterControlContext->CurrentVa;
-
+
/* Store the map register base for later in HalPutScatterGatherList */
AdapterControlContext->MapRegisterBase = MapRegisterBase;
-
+
while (RemainingLength > 0 && ElementCount < MAX_SG_ELEMENTS)
{
TempElements[ElementCount].Length = RemainingLength;
AdapterControlContext->WriteToDevice);
if (TempElements[ElementCount].Length == 0)
break;
-
+
DPRINT("Allocated one S/G element: 0x%I64u with length: 0x%x\n",
TempElements[ElementCount].Address.QuadPart,
TempElements[ElementCount].Length);
-
+
ASSERT(TempElements[ElementCount].Length <= RemainingLength);
RemainingLength -= TempElements[ElementCount].Length;
ElementCount++;
}
-
+
if (RemainingLength > 0)
{
DPRINT1("Scatter/gather list construction failed!\n");
RtlCopyMemory(ScatterGatherList->Elements,
TempElements,
sizeof(SCATTER_GATHER_ELEMENT) * ElementCount);
-
+
DPRINT("Initiating S/G DMA with %d element(s)\n", ElementCount);
-
+
AdapterControlContext->AdapterListControlRoutine(DeviceObject,
Irp,
ScatterGatherList,
AdapterControlContext->AdapterListControlContext);
-
+
return DeallocateObjectKeepRegisters;
}
IN BOOLEAN WriteToDevice)
{
PSCATTER_GATHER_CONTEXT AdapterControlContext;
-
+
AdapterControlContext = ExAllocatePoolWithTag(NonPagedPool, sizeof(SCATTER_GATHER_CONTEXT), TAG_DMA);
if (!AdapterControlContext) return STATUS_INSUFFICIENT_RESOURCES;
-
+
AdapterControlContext->AdapterObject = AdapterObject;
AdapterControlContext->Mdl = Mdl;
AdapterControlContext->CurrentVa = CurrentVa;
AdapterControlContext->AdapterListControlRoutine = ExecutionRoutine;
AdapterControlContext->AdapterListControlContext = Context;
AdapterControlContext->WriteToDevice = WriteToDevice;
-
+
return IoAllocateAdapterChannel(AdapterObject,
DeviceObject,
AdapterControlContext->MapRegisterCount,
{
PSCATTER_GATHER_CONTEXT AdapterControlContext = (PSCATTER_GATHER_CONTEXT)ScatterGather->Reserved;
ULONG i;
-
+
for (i = 0; i < ScatterGather->NumberOfElements; i++)
{
IoFlushAdapterBuffers(AdapterObject,
IoFreeMapRegisters(AdapterObject,
AdapterControlContext->MapRegisterBase,
AdapterControlContext->MapRegisterCount);
-
+
DPRINT("S/G DMA has finished!\n");
-
+
ExFreePoolWithTag(AdapterControlContext, TAG_DMA);
ExFreePoolWithTag(ScatterGather, TAG_DMA);
}
do
{
OldCount = Count;
-
+
/* Send Reset */
WRITE_PORT_UCHAR(&DmaControl1->ClearBytePointer, 0);
-
+
/* Read Count */
Count = READ_PORT_UCHAR(&DmaControl1->DmaAddressCount
[AdapterObject->ChannelNumber].DmaBaseCount);
do
{
OldCount = Count;
-
+
/* Send Reset */
WRITE_PORT_UCHAR(&DmaControl2->ClearBytePointer, 0);
-
+
/* Read Count */
Count = READ_PORT_UCHAR(&DmaControl2->DmaAddressCount
[AdapterObject->ChannelNumber].DmaBaseCount);
if (Index == MAXULONG)
{
InsertTailList(&MasterAdapter->AdapterQueue, &AdapterObject->AdapterQueue);
-
+
WorkItem = ExAllocatePoolWithTag(NonPagedPool,
sizeof(GROW_WORK_ITEM),
TAG_DMA);
DeviceQueueEntry = KeRemoveDeviceQueue(&AdapterObject->ChannelWaitQueue);
if (!DeviceQueueEntry) break;
-
+
WaitContextBlock = CONTAINING_RECORD(DeviceQueueEntry,
WAIT_CONTEXT_BLOCK,
WaitQueueEntry);
RealMapRegisterBase = (PROS_MAP_REGISTER_ENTRY)((ULONG_PTR)MapRegisterBase & ~MAP_BASE_SW_SG);
RtlClearBits(MasterAdapter->MapRegisters,
- RealMapRegisterBase - MasterAdapter->MapRegisterBase,
+ (ULONG)(RealMapRegisterBase - MasterAdapter->MapRegisterBase),
NumberOfMapRegisters);
}
{
KeAcquireSpinLock(&MasterAdapter->SpinLock, &OldIrql);
RtlClearBits(MasterAdapter->MapRegisters,
- AdapterObject->MapRegisterBase -
- MasterAdapter->MapRegisterBase,
+ (ULONG)(AdapterObject->MapRegisterBase -
+ MasterAdapter->MapRegisterBase),
AdapterObject->NumberOfMapRegisters);
KeReleaseSpinLock(&MasterAdapter->SpinLock, OldIrql);
}
-
+
IoFreeAdapterChannel(AdapterObject);
break;
/* Reset Register */
WRITE_PORT_UCHAR(&DmaControl1->ClearBytePointer, 0);
-
+
/* Set the Mode */
WRITE_PORT_UCHAR(&DmaControl1->Mode, AdapterMode.Byte);
-
+
/* Set the Offset Register */
WRITE_PORT_UCHAR(&DmaControl1->DmaAddressCount[AdapterObject->ChannelNumber].DmaBaseAddress,
(UCHAR)(TransferOffset));
WRITE_PORT_UCHAR(&DmaControl1->DmaAddressCount[AdapterObject->ChannelNumber].DmaBaseAddress,
(UCHAR)(TransferOffset >> 8));
-
+
/* Set the Page Register */
WRITE_PORT_UCHAR(AdapterObject->PagePort + FIELD_OFFSET(EISA_CONTROL, DmaController1Pages),
(UCHAR)(PhysicalAddress.LowPart >> 16));
WRITE_PORT_UCHAR(AdapterObject->PagePort + FIELD_OFFSET(EISA_CONTROL, DmaController2Pages),
0);
}
-
+
/* Set the Length */
WRITE_PORT_UCHAR(&DmaControl1->DmaAddressCount[AdapterObject->ChannelNumber].DmaBaseCount,
(UCHAR)(TransferLength - 1));
WRITE_PORT_UCHAR(&DmaControl1->DmaAddressCount[AdapterObject->ChannelNumber].DmaBaseCount,
(UCHAR)((TransferLength - 1) >> 8));
-
+
/* Unmask the Channel */
WRITE_PORT_UCHAR(&DmaControl1->SingleMask, AdapterObject->ChannelNumber | DMA_CLEARMASK);
}
/* Reset Register */
WRITE_PORT_UCHAR(&DmaControl2->ClearBytePointer, 0);
-
+
/* Set the Mode */
WRITE_PORT_UCHAR(&DmaControl2->Mode, AdapterMode.Byte);
-
+
/* Set the Offset Register */
WRITE_PORT_UCHAR(&DmaControl2->DmaAddressCount[AdapterObject->ChannelNumber].DmaBaseAddress,
(UCHAR)(TransferOffset));
WRITE_PORT_UCHAR(&DmaControl2->DmaAddressCount[AdapterObject->ChannelNumber].DmaBaseAddress,
(UCHAR)(TransferOffset >> 8));
-
+
/* Set the Page Register */
WRITE_PORT_UCHAR(AdapterObject->PagePort + FIELD_OFFSET(EISA_CONTROL, DmaController1Pages),
(UCHAR)(PhysicalAddress.u.LowPart >> 16));
WRITE_PORT_UCHAR(AdapterObject->PagePort + FIELD_OFFSET(EISA_CONTROL, DmaController2Pages),
0);
}
-
+
/* Set the Length */
WRITE_PORT_UCHAR(&DmaControl2->DmaAddressCount[AdapterObject->ChannelNumber].DmaBaseCount,
(UCHAR)(TransferLength - 1));
WRITE_PORT_UCHAR(&DmaControl2->DmaAddressCount[AdapterObject->ChannelNumber].DmaBaseCount,
(UCHAR)((TransferLength - 1) >> 8));
-
+
/* Unmask the Channel */
WRITE_PORT_UCHAR(&DmaControl2->SingleMask,
AdapterObject->ChannelNumber | DMA_CLEARMASK);