[PCI]: Add PCI IRQ Routing Table structure to Shared, Internal PCI Header (based...

[reactos.git] / reactos / hal / halx86 / include / bus.h

diff --git a/reactos/hal/halx86/include/bus.h b/reactos/hal/halx86/include/bus.h
index 3f6e1d6..67a57cf 100644 (file)
--- a/reactos/hal/halx86/include/bus.h
+++ b/reactos/hal/halx86/include/bus.h
@@ -158,6 +158,77 @@ typedef struct _PCI_REGISTRY_INFO_INTERNAL
     PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
 } PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
 
+//
+// PCI Type 1 Ports
+//
+#define PCI_TYPE1_ADDRESS_PORT      (PULONG)0xCF8
+#define PCI_TYPE1_DATA_PORT         0xCFC
+
+//
+// PCI Type 2 Ports
+//
+#define PCI_TYPE2_CSE_PORT          (PUCHAR)0xCF8
+#define PCI_TYPE2_FORWARD_PORT      (PUCHAR)0xCFA
+#define PCI_TYPE2_ADDRESS_BASE      0xC
+
+//
+// PCI Type 1 Configuration Register
+//
+typedef struct _PCI_TYPE1_CFG_BITS
+{
+    union
+    {
+        struct
+        {
+            ULONG Reserved1:2;
+            ULONG RegisterNumber:6;
+            ULONG FunctionNumber:3;
+            ULONG DeviceNumber:5;
+            ULONG BusNumber:8;
+            ULONG Reserved2:7;
+            ULONG Enable:1;
+        } bits;
+
+        ULONG AsULONG;
+    } u;
+} PCI_TYPE1_CFG_BITS, *PPCI_TYPE1_CFG_BITS;
+
+//
+// PCI Type 2 CSE Register
+//
+typedef struct _PCI_TYPE2_CSE_BITS
+{
+    union
+    {
+        struct
+        {
+            UCHAR Enable:1;
+            UCHAR FunctionNumber:3;
+            UCHAR Key:4;
+        } bits;
+
+        UCHAR AsUCHAR;
+    } u;
+} PCI_TYPE2_CSE_BITS, PPCI_TYPE2_CSE_BITS;
+
+//
+// PCI Type 2 Address Register
+//
+typedef struct _PCI_TYPE2_ADDRESS_BITS
+{
+    union
+    {
+        struct
+        {
+            USHORT RegisterNumber:8;
+            USHORT Agent:4;
+            USHORT AddressBase:4;
+        } bits;
+
+        USHORT AsUSHORT;
+    } u;
+} PCI_TYPE2_ADDRESS_BITS, *PPCI_TYPE2_ADDRESS_BITS;
+
 typedef struct _PCI_TYPE0_CFG_CYCLE_BITS
 {
     union