#include <poppack.h>
#endif
-CHAR *APstart, *APend;
+extern CHAR *APstart, *APend;
#define BIOS_AREA 0x0
#define COMMON_AREA 0x2000
BOOLEAN VerifyLocalAPIC(VOID)
{
SIZE_T reg0, reg1;
- ULONG l, h;
+ LARGE_INTEGER MsrValue;
+
/* The version register is read-only in a real APIC */
reg0 = APICRead(APIC_VER);
DPRINT1("Getting VERSION: %x\n", reg0);
return FALSE;
}
- Ke386Rdmsr(0x1b /*MSR_IA32_APICBASE*/, l, h);
+ MsrValue.QuadPart = __readmsr(0x1B /*MSR_IA32_APICBASE*/);
- if (!(l & /*MSR_IA32_APICBASE_ENABLE*/(1<<11)))
+ if (!(MsrValue.LowPart & /*MSR_IA32_APICBASE_ENABLE*/(1<<11)))
{
DPRINT1("Local APIC disabled by BIOS -- reenabling.\n");
- l &= ~/*MSR_IA32_APICBASE_BASE*/(1<<11);
- l |= /*MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE*/(1<<11)|0xfee00000;
- Ke386Wrmsr(0x1b/*MSR_IA32_APICBASE*/, l, h);
+ MsrValue.LowPart &= ~/*MSR_IA32_APICBASE_BASE*/(1<<11);
+ MsrValue.LowPart |= /*MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE*/(1<<11)|0xfee00000;
+ __writemsr(0x1B /*MSR_IA32_APICBASE*/, MsrValue.HighPart);
}
ULONG tmp, i, flags;
/* save flags and disable interrupts */
- Ke386SaveFlags(flags);
+ flags = __readeflags();
_disable();
/* Wait up to 100ms for the APIC to become ready */
{
DPRINT1("CPU(%d) Current IPI was not delivered after 100ms.\n", ThisCPU());
}
- Ke386RestoreFlags(flags);
+ __writeeflags(flags);
}
#endif
if (TSCPresent)
{
t2.QuadPart = (LONGLONG)__rdtsc();
- CPUMap[CPU].CoreSpeed = (HZ * (t2.QuadPart - t1.QuadPart));
+ CPUMap[CPU].CoreSpeed = (HZ * (ULONG)(t2.QuadPart - t1.QuadPart));
DPRINT("CPU clock speed is %ld.%04ld MHz.\n",
CPUMap[CPU].CoreSpeed/1000000,
CPUMap[CPU].CoreSpeed%1000000);
Access.SegmentType = I386_INTERRUPT_GATE;
idt = (KIDTENTRY*)((ULONG)KeGetPcr()->IDT + index * sizeof(KIDTENTRY));
- idt->Offset = address & 0xffff;
+ idt->Offset = (USHORT)(address & 0xffff);
idt->Selector = KGDT_R0_CODE;
idt->Access = Access.Value;
- idt->ExtendedOffset = address >> 16;
+ idt->ExtendedOffset = (USHORT)(address >> 16);
#endif
}