-/* $Id: pci.c,v 1.9 2003/04/26 07:06:54 hbirr Exp $
+/* $Id: pci.c,v 1.12 2004/10/22 20:08:22 ekohl Exp $
*
* COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel
case 2:
KeAcquireSpinLock(&PciLock, &oldIrql);
- WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
+ WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
*Value = READ_PORT_UCHAR((PUCHAR)(IOADDR(Slot, Offset)));
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
case 2:
KeAcquireSpinLock(&PciLock, &oldIrql);
- WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
+ WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
*Value = READ_PORT_USHORT((PUSHORT)(IOADDR(Slot, Offset)));
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
case 2:
KeAcquireSpinLock(&PciLock, &oldIrql);
- WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
+ WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
*Value = READ_PORT_ULONG((PULONG)(IOADDR(Slot, Offset)));
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
case 2:
KeAcquireSpinLock(&PciLock, &oldIrql);
- WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
+ WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
WRITE_PORT_UCHAR((PUCHAR)(IOADDR(Slot,Offset)), Value);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
case 2:
KeAcquireSpinLock(&PciLock, &oldIrql);
- WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
+ WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
WRITE_PORT_USHORT((PUSHORT)(IOADDR(Slot, Offset)), Value);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
case 2:
KeAcquireSpinLock(&PciLock, &oldIrql);
- WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
+ WRITE_PORT_UCHAR((PUCHAR)0xCF8, (UCHAR)FUNC(Slot));
WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
WRITE_PORT_ULONG((PULONG)(IOADDR(Slot, Offset)), Value);
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
if ((Length == 0) || (BusConfigType == 0))
return 0;
- ReadPciConfigUlong(BusNumber,
- SlotNumber & 0x1F,
+ ReadPciConfigUlong((UCHAR)BusNumber,
+ (UCHAR)(SlotNumber & 0x1F),
0x00,
&Vendor);
/* some broken boards return 0 if a slot is empty: */
}
/* 0E=PCI_HEADER_TYPE */
- ReadPciConfigUchar(BusNumber,
- SlotNumber & 0x1F,
+ ReadPciConfigUchar((UCHAR)BusNumber,
+ (UCHAR)(SlotNumber & 0x1F),
0x0E,
&HeaderType);
if (((HeaderType & PCI_MULTIFUNCTION) == 0) && ((SlotNumber & 0xE0) != 0))
}
return 0;
}
- ReadPciConfigUlong(BusNumber,
- SlotNumber,
+ ReadPciConfigUlong((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
0x00,
&Vendor);
/* some broken boards return 0 if a slot is empty: */
if ((Address & 1) && (Len >= 1))
{
- ReadPciConfigUchar(BusNumber,
- SlotNumber,
- Address,
+ ReadPciConfigUchar((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
+ (UCHAR)Address,
Ptr);
- Ptr = Ptr + 1;
+ Ptr = (char*)Ptr + 1;
Address++;
Len--;
}
if ((Address & 2) && (Len >= 2))
{
- ReadPciConfigUshort(BusNumber,
- SlotNumber,
- Address,
+ ReadPciConfigUshort((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
+ (UCHAR)Address,
Ptr);
- Ptr = Ptr + 2;
+ Ptr = (char*)Ptr + 2;
Address += 2;
Len -= 2;
}
while (Len >= 4)
{
- ReadPciConfigUlong(BusNumber,
- SlotNumber,
- Address,
+ ReadPciConfigUlong((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
+ (UCHAR)Address,
Ptr);
- Ptr = Ptr + 4;
+ Ptr = (char*)Ptr + 4;
Address += 4;
Len -= 4;
}
if (Len >= 2)
{
- ReadPciConfigUshort(BusNumber,
- SlotNumber,
- Address,
+ ReadPciConfigUshort((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
+ (UCHAR)Address,
Ptr);
- Ptr = Ptr + 2;
+ Ptr = (char*)Ptr + 2;
Address += 2;
Len -= 2;
}
if (Len >= 1)
{
- ReadPciConfigUchar(BusNumber,
- SlotNumber,
- Address,
+ ReadPciConfigUchar((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
+ (UCHAR)Address,
Ptr);
- Ptr = Ptr + 1;
+ Ptr = (char*)Ptr + 1;
Address++;
Len--;
}
if ((Length == 0) || (BusConfigType == 0))
return 0;
- ReadPciConfigUlong(BusNumber,
- SlotNumber & 0x1F,
+ ReadPciConfigUlong((UCHAR)BusNumber,
+ (UCHAR)(SlotNumber & 0x1F),
0x00,
&Vendor);
/* some broken boards return 0 if a slot is empty: */
/* 0E=PCI_HEADER_TYPE */
- ReadPciConfigUchar(BusNumber,
- SlotNumber & 0x1F,
+ ReadPciConfigUchar((UCHAR)BusNumber,
+ (UCHAR)(SlotNumber & 0x1F),
0x0E,
&HeaderType);
if (((HeaderType & PCI_MULTIFUNCTION) == 0) && ((SlotNumber & 0xE0) != 0))
return 0;
- ReadPciConfigUlong(BusNumber,
- SlotNumber,
+ ReadPciConfigUlong((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
0x00,
&Vendor);
/* some broken boards return 0 if a slot is empty: */
if ((Address & 1) && (Len >= 1))
{
- WritePciConfigUchar(BusNumber,
- SlotNumber,
- Address,
+ WritePciConfigUchar((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
+ (UCHAR)Address,
*(PUCHAR)Ptr);
- Ptr = Ptr + 1;
+ Ptr = (char*)Ptr + 1;
Address++;
Len--;
}
if ((Address & 2) && (Len >= 2))
{
- WritePciConfigUshort(BusNumber,
- SlotNumber,
- Address,
+ WritePciConfigUshort((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
+ (UCHAR)Address,
*(PUSHORT)Ptr);
- Ptr = Ptr + 2;
+ Ptr = (char*)Ptr + 2;
Address += 2;
Len -= 2;
}
while (Len >= 4)
{
- WritePciConfigUlong(BusNumber,
- SlotNumber,
- Address,
+ WritePciConfigUlong((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
+ (UCHAR)Address,
*(PULONG)Ptr);
- Ptr = Ptr + 4;
+ Ptr = (char*)Ptr + 4;
Address += 4;
Len -= 4;
}
if (Len >= 2)
{
- WritePciConfigUshort(BusNumber,
- SlotNumber,
- Address,
+ WritePciConfigUshort((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
+ (UCHAR)Address,
*(PUSHORT)Ptr);
- Ptr = Ptr + 2;
+ Ptr = (char*)Ptr + 2;
Address += 2;
Len -= 2;
}
if (Len >= 1)
{
- WritePciConfigUchar(BusNumber,
- SlotNumber,
- Address,
+ WritePciConfigUchar((UCHAR)BusNumber,
+ (UCHAR)SlotNumber,
+ (UCHAR)Address,
*(PUCHAR)Ptr);
- Ptr = Ptr + 1;
+ Ptr = (char*)Ptr + 1;
Address++;
Len--;
}
PKAFFINITY Affinity)
{
#ifdef MP
- *Irql = PROFILE_LEVEL - BusInterruptVector;
+ *Irql = (KIRQL)(PROFILE_LEVEL - BusInterruptVector);
*Affinity = 0xFFFFFFFF;
return IRQ2VECTOR(BusInterruptVector);
#else
- *Irql = PROFILE_LEVEL - BusInterruptVector;
+ *Irql = (KIRQL)(PROFILE_LEVEL - BusInterruptVector);
*Affinity = 0xFFFFFFFF;
return BusInterruptVector;
#endif
IN ULONG SlotNumber,
IN OUT PCM_RESOURCE_LIST *AllocatedResources)
{
+ ULONG DataSize;
+ PCI_COMMON_CONFIG PciConfig;
UINT Address;
- UINT NoAddresses;
- ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
+ UINT ResourceCount;
ULONG Size[PCI_TYPE0_ADDRESSES];
NTSTATUS Status = STATUS_SUCCESS;
UCHAR Offset;
/* FIXME: Should handle 64-bit addresses */
+ DataSize = HalpGetPciData(BusHandler,
+ BusNumber,
+ SlotNumber,
+ &PciConfig,
+ 0,
+ PCI_COMMON_HDR_LENGTH);
+ if (PCI_COMMON_HDR_LENGTH != DataSize)
+ {
+ return STATUS_UNSUCCESSFUL;
+ }
+
/* Read the PCI configuration space for the device and store base address and
size information in temporary storage. Count the number of valid base addresses */
- NoAddresses = 0;
+ ResourceCount = 0;
for (Address = 0; Address < PCI_TYPE0_ADDRESSES; Address++)
{
- Offset = offsetof(PCI_COMMON_CONFIG, u.type0.BaseAddresses[Address]);
- Status = ReadPciConfigUlong(BusNumber, SlotNumber,
- Offset, BaseAddresses + Address);
- if (! NT_SUCCESS(Status))
+ if (0xffffffff == PciConfig.u.type0.BaseAddresses[Address])
{
- return Status;
+ PciConfig.u.type0.BaseAddresses[Address] = 0;
}
- if (0xffffffff == BaseAddresses[Address])
+ if (0 != PciConfig.u.type0.BaseAddresses[Address])
{
- BaseAddresses[Address] = 0;
- }
- if (0 != BaseAddresses[Address])
- {
- NoAddresses++;
- Status = WritePciConfigUlong(BusNumber, SlotNumber, Offset, 0xffffffff);
+ ResourceCount++;
+ Offset = offsetof(PCI_COMMON_CONFIG, u.type0.BaseAddresses[Address]);
+ Status = WritePciConfigUlong((UCHAR)BusNumber, (UCHAR)SlotNumber, Offset, 0xffffffff);
if (! NT_SUCCESS(Status))
{
- WritePciConfigUlong(BusNumber, SlotNumber, Offset, BaseAddresses[Address]);
+ WritePciConfigUlong((UCHAR)BusNumber, (UCHAR)SlotNumber, Offset,
+ PciConfig.u.type0.BaseAddresses[Address]);
return Status;
}
- Status = ReadPciConfigUlong(BusNumber, SlotNumber,
+ Status = ReadPciConfigUlong((UCHAR)BusNumber, (UCHAR)SlotNumber,
Offset, Size + Address);
if (! NT_SUCCESS(Status))
{
- WritePciConfigUlong(BusNumber, SlotNumber, Offset, BaseAddresses[Address]);
+ WritePciConfigUlong((UCHAR)BusNumber, (UCHAR)SlotNumber, Offset,
+ PciConfig.u.type0.BaseAddresses[Address]);
return Status;
}
- Status = WritePciConfigUlong(BusNumber, SlotNumber, Offset, BaseAddresses[Address]);
+ Status = WritePciConfigUlong((UCHAR)BusNumber, (UCHAR)SlotNumber, Offset,
+ PciConfig.u.type0.BaseAddresses[Address]);
if (! NT_SUCCESS(Status))
{
return Status;
}
-
}
}
+ if (0 != PciConfig.u.type0.InterruptLine)
+ {
+ ResourceCount++;
+ }
+
/* Allocate output buffer and initialize */
*AllocatedResources = ExAllocatePoolWithTag(PagedPool,
sizeof(CM_RESOURCE_LIST) +
- (NoAddresses - 1) * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR),
+ (ResourceCount - 1) * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR),
TAG_PCI);
if (NULL == *AllocatedResources)
{
- return STATUS_NO_MEMORY;
+ return STATUS_NO_MEMORY;
}
(*AllocatedResources)->Count = 1;
(*AllocatedResources)->List[0].InterfaceType = PCIBus;
(*AllocatedResources)->List[0].BusNumber = BusNumber;
(*AllocatedResources)->List[0].PartialResourceList.Version = 1;
(*AllocatedResources)->List[0].PartialResourceList.Revision = 1;
- (*AllocatedResources)->List[0].PartialResourceList.Count = NoAddresses;
+ (*AllocatedResources)->List[0].PartialResourceList.Count = ResourceCount;
Descriptor = (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors;
/* Store configuration information */
for (Address = 0; Address < PCI_TYPE0_ADDRESSES; Address++)
{
- if (0 != BaseAddresses[Address])
+ if (0 != PciConfig.u.type0.BaseAddresses[Address])
{
if (PCI_BASE_ADDRESS_SPACE_MEMORY ==
- (BaseAddresses[Address] & PCI_BASE_ADDRESS_SPACE))
+ (PciConfig.u.type0.BaseAddresses[Address] & PCI_BASE_ADDRESS_SPACE))
{
Descriptor->Type = CmResourceTypeMemory;
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE; /* FIXME Just a guess */
- Descriptor->u.Memory.Start.QuadPart = (BaseAddresses[Address] & PCI_BASE_ADDRESS_MEM_MASK);
+ Descriptor->u.Memory.Start.QuadPart = (PciConfig.u.type0.BaseAddresses[Address] & PCI_BASE_ADDRESS_MEM_MASK);
Descriptor->u.Memory.Length = PciSize(Size[Address], PCI_BASE_ADDRESS_MEM_MASK);
}
else if (PCI_BASE_ADDRESS_SPACE_IO ==
- (BaseAddresses[Address] & PCI_BASE_ADDRESS_SPACE))
+ (PciConfig.u.type0.BaseAddresses[Address] & PCI_BASE_ADDRESS_SPACE))
{
Descriptor->Type = CmResourceTypePort;
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
Descriptor->Flags = CM_RESOURCE_PORT_IO; /* FIXME Just a guess */
- Descriptor->u.Port.Start.QuadPart = BaseAddresses[Address] &= PCI_BASE_ADDRESS_IO_MASK;
+ Descriptor->u.Port.Start.QuadPart = PciConfig.u.type0.BaseAddresses[Address] &= PCI_BASE_ADDRESS_IO_MASK;
Descriptor->u.Port.Length = PciSize(Size[Address], PCI_BASE_ADDRESS_IO_MASK & 0xffff);
}
else
{
- assert(FALSE);
+ ASSERT(FALSE);
return STATUS_UNSUCCESSFUL;
}
Descriptor++;
}
}
- assert(Descriptor == (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors + NoAddresses);
+ if (0 != PciConfig.u.type0.InterruptLine)
+ {
+ Descriptor->Type = CmResourceTypeInterrupt;
+ Descriptor->ShareDisposition = CmResourceShareShared; /* FIXME Just a guess */
+ Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE; /* FIXME Just a guess */
+ Descriptor->u.Interrupt.Level = PciConfig.u.type0.InterruptLine;
+ Descriptor->u.Interrupt.Vector = PciConfig.u.type0.InterruptLine;
+ Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
+
+ Descriptor++;
+ }
+
+ ASSERT(Descriptor == (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors + ResourceCount);
/* FIXME: Should store the resources in the registry resource map */
projects / reactos.git / blobdiff