X-Git-Url: https://git.reactos.org/?p=reactos.git;a=blobdiff_plain;f=hal%2Fhalx86%2Fup%2Fpic.c;h=f61bf738d0ac641f185c6d476b6e0d76adc5b066;hp=052dc1bb5f97e84e255a2f528e0374e1c9d74de8;hb=040d78354e7da85350629a8b28f303d959a81f9c;hpb=7a0c3bde06485b108dfcb053ba4ecaa4ac629b5c diff --git a/hal/halx86/up/pic.c b/hal/halx86/up/pic.c index 052dc1bb5f9..f61bf738d0a 100644 --- a/hal/halx86/up/pic.c +++ b/hal/halx86/up/pic.c @@ -1,7 +1,7 @@ /* * PROJECT: ReactOS HAL * LICENSE: BSD - See COPYING.ARM in the top level directory - * FILE: hal/halx86/generic/pic.c + * FILE: hal/halx86/up/pic.c * PURPOSE: HAL PIC Management and Control Code * PROGRAMMERS: ReactOS Portable Systems Group */ @@ -12,6 +12,11 @@ #define NDEBUG #include +VOID +NTAPI +HalpEndSoftwareInterrupt(IN KIRQL OldIrql, + IN PKTRAP_FRAME TrapFrame); + /* GLOBALS ********************************************************************/ #ifndef _MINIHAL_ @@ -94,8 +99,7 @@ PHAL_DISMISS_INTERRUPT HalpSpecialDismissLevelTable[16] = /* This table contains the static x86 PIC mapping between IRQLs and IRQs */ ULONG KiI8259MaskTable[32] = { -#if defined(__GNUC__) && \ - (__GNUC__ * 100 + __GNUC_MINOR__ >= 404) +#if defined(__GNUC__) || defined(__clang__) || (defined(_MSC_VER) && _MSC_VER >= 1900) /* * It Device IRQLs only start at 4 or higher, so these are just software * IRQLs that don't really change anything on the hardware @@ -211,8 +215,7 @@ ULONG KiI8259MaskTable[32] = /* This table indicates which IRQs, if pending, can preempt a given IRQL level */ ULONG FindHigherIrqlMask[32] = { -#if defined(__GNUC__) && \ - (__GNUC__ * 100 + __GNUC_MINOR__ >= 404) +#if defined(__GNUC__) || defined(__clang__) || (defined(_MSC_VER) && _MSC_VER >= 1900) /* * Software IRQLs, at these levels all hardware interrupts can preempt. * Each higher IRQL simply enables which software IRQL can preempt the @@ -263,7 +266,7 @@ ULONG FindHigherIrqlMask[32] = * so it will always preempt until we reach PROFILE_LEVEL. */ 0b00000000000000000001011111110000, /* IRQL 20 */ - 0b00000000000000000001001111110000, /* IRQL 20 */ + 0b00000000000000000001001111110000, /* IRQL 21 */ 0b00000000000000000001000111110000, /* IRQL 22 */ 0b00000000000000000001000011110000, /* IRQL 23 */ 0b00000000000000000001000001110000, /* IRQL 24 */ @@ -330,8 +333,9 @@ KIRQL SWInterruptLookUpTable[8] = #if defined(__GNUC__) #define HalpDelayedHardwareInterrupt(x) \ - VOID HalpHardwareInterrupt##x(VOID); \ + VOID __cdecl HalpHardwareInterrupt##x(VOID); \ VOID \ + __cdecl \ HalpHardwareInterrupt##x(VOID) \ { \ asm volatile ("int $%c0\n"::"i"(PRIMARY_VECTOR_BASE + x)); \ @@ -340,8 +344,9 @@ KIRQL SWInterruptLookUpTable[8] = #elif defined(_MSC_VER) #define HalpDelayedHardwareInterrupt(x) \ - VOID HalpHardwareInterrupt##x(VOID); \ + VOID __cdecl HalpHardwareInterrupt##x(VOID); \ VOID \ + __cdecl \ HalpHardwareInterrupt##x(VOID) \ { \ __asm \ @@ -375,10 +380,10 @@ HalpDelayedHardwareInterrupt(15); /* Handlers for pending interrupts */ PHAL_SW_INTERRUPT_HANDLER SWInterruptHandlerTable[20] = { - KiUnexpectedInterrupt, + (PHAL_SW_INTERRUPT_HANDLER)KiUnexpectedInterrupt, HalpApcInterrupt, HalpDispatchInterrupt2, - KiUnexpectedInterrupt, + (PHAL_SW_INTERRUPT_HANDLER)KiUnexpectedInterrupt, HalpHardwareInterrupt0, HalpHardwareInterrupt1, HalpHardwareInterrupt2, @@ -414,10 +419,6 @@ NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts) { ULONG EFlags; - I8259_ICW1 Icw1; - I8259_ICW2 Icw2; - I8259_ICW3 Icw3; - I8259_ICW4 Icw4; EISA_ELCR Elcr; ULONG i, j; @@ -425,63 +426,8 @@ HalpInitializePICs(IN BOOLEAN EnableInterrupts) EFlags = __readeflags(); _disable(); - /* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */ - Icw1.NeedIcw4 = TRUE; - Icw1.InterruptMode = EdgeTriggered; - Icw1.OperatingMode = Cascade; - Icw1.Interval = Interval8; - Icw1.Init = TRUE; - Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */ - __outbyte(PIC1_CONTROL_PORT, Icw1.Bits); - - /* Set interrupt vector base */ - Icw2.Bits = PRIMARY_VECTOR_BASE; - __outbyte(PIC1_DATA_PORT, Icw2.Bits); - - /* Connect slave to IRQ 2 */ - Icw3.Bits = 0; - Icw3.SlaveIrq2 = TRUE; - __outbyte(PIC1_DATA_PORT, Icw3.Bits); - - /* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */ - Icw4.Reserved = 0; - Icw4.SystemMode = New8086Mode; - Icw4.EoiMode = NormalEoi; - Icw4.BufferedMode = NonBuffered; - Icw4.SpecialFullyNestedMode = FALSE; - __outbyte(PIC1_DATA_PORT, Icw4.Bits); - - /* Mask all interrupts */ - __outbyte(PIC1_DATA_PORT, 0xFF); - - /* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */ - Icw1.NeedIcw4 = TRUE; - Icw1.InterruptMode = EdgeTriggered; - Icw1.OperatingMode = Cascade; - Icw1.Interval = Interval8; - Icw1.Init = TRUE; - Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */ - __outbyte(PIC2_CONTROL_PORT, Icw1.Bits); - - /* Set interrupt vector base */ - Icw2.Bits = PRIMARY_VECTOR_BASE + 8; - __outbyte(PIC2_DATA_PORT, Icw2.Bits); - - /* Slave ID */ - Icw3.Bits = 0; - Icw3.SlaveId = 2; - __outbyte(PIC2_DATA_PORT, Icw3.Bits); - - /* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */ - Icw4.Reserved = 0; - Icw4.SystemMode = New8086Mode; - Icw4.EoiMode = NormalEoi; - Icw4.BufferedMode = NonBuffered; - Icw4.SpecialFullyNestedMode = FALSE; - __outbyte(PIC2_DATA_PORT, Icw4.Bits); - - /* Mask all interrupts */ - __outbyte(PIC2_DATA_PORT, 0xFF); + /* Initialize and mask the PIC */ + HalpInitializeLegacyPICs(); /* Read EISA Edge/Level Register for master and slave */ Elcr.Bits = (__inbyte(EISA_ELCR_SLAVE) << 8) | __inbyte(EISA_ELCR_MASTER); @@ -730,15 +676,17 @@ HalClearSoftwareInterrupt(IN KIRQL Irql) KeGetPcr()->IRR &= ~(1 << Irql); } -VOID -NTAPI -HalpEndSoftwareInterrupt(IN KIRQL OldIrql, - IN PKTRAP_FRAME TrapFrame) +PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY +FASTCALL +HalpEndSoftwareInterrupt2(IN KIRQL OldIrql, + IN PKTRAP_FRAME TrapFrame) { ULONG PendingIrql, PendingIrqlMask, PendingIrqMask; PKPCR Pcr = KeGetPcr(); PIC_MASK Mask; + UNREFERENCED_PARAMETER(TrapFrame); + /* Set old IRQL */ Pcr->Irql = OldIrql; @@ -747,10 +695,10 @@ HalpEndSoftwareInterrupt(IN KIRQL OldIrql, { /* Check for pending software interrupts and compare with current IRQL */ PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql]; - if (!PendingIrqlMask) return; + if (!PendingIrqlMask) return NULL; /* Check for in-service delayed interrupt */ - if (Pcr->IrrActive & 0xFFFFFFF0) return; + if (Pcr->IrrActive & 0xFFFFFFF0) return NULL; /* Check if pending IRQL affects hardware state */ BitScanReverse(&PendingIrql, PendingIrqlMask); @@ -775,9 +723,11 @@ HalpEndSoftwareInterrupt(IN KIRQL OldIrql, else { /* No need to loop checking for hardware interrupts */ - SWInterruptHandlerTable2[PendingIrql](TrapFrame); + return SWInterruptHandlerTable2[PendingIrql]; } } + + return NULL; } /* EDGE INTERRUPT DISMISSAL FUNCTIONS *****************************************/ @@ -808,7 +758,7 @@ _HalpDismissIrqGeneric(IN KIRQL Irql, Ocw2.EoiMode = SpecificEoi; /* Check which PIC needs the EOI */ - if (Irq > 8) + if (Irq >= 8) { /* Send the EOI for the IRQ */ __outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF)); @@ -840,7 +790,7 @@ _HalpDismissIrqGeneric(IN KIRQL Irql, } BOOLEAN -REGISTERCALL +NTAPI HalpDismissIrqGeneric(IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql) @@ -850,7 +800,7 @@ HalpDismissIrqGeneric(IN KIRQL Irql, } BOOLEAN -REGISTERCALL +NTAPI HalpDismissIrq15(IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql) @@ -886,7 +836,7 @@ HalpDismissIrq15(IN KIRQL Irql, BOOLEAN -REGISTERCALL +NTAPI HalpDismissIrq13(IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql) @@ -899,7 +849,7 @@ HalpDismissIrq13(IN KIRQL Irql, } BOOLEAN -REGISTERCALL +NTAPI HalpDismissIrq07(IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql) @@ -952,7 +902,7 @@ _HalpDismissIrqLevel(IN KIRQL Irql, Ocw2.EoiMode = SpecificEoi; /* Check which PIC needs the EOI */ - if (Irq > 8) + if (Irq >= 8) { /* Send the EOI for the IRQ */ __outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF)); @@ -983,7 +933,7 @@ _HalpDismissIrqLevel(IN KIRQL Irql, } BOOLEAN -REGISTERCALL +NTAPI HalpDismissIrqLevel(IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql) @@ -993,7 +943,7 @@ HalpDismissIrqLevel(IN KIRQL Irql, } BOOLEAN -REGISTERCALL +NTAPI HalpDismissIrq15Level(IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql) @@ -1028,7 +978,7 @@ HalpDismissIrq15Level(IN KIRQL Irql, } BOOLEAN -REGISTERCALL +NTAPI HalpDismissIrq13Level(IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql) @@ -1041,7 +991,7 @@ HalpDismissIrq13Level(IN KIRQL Irql, } BOOLEAN -REGISTERCALL +NTAPI HalpDismissIrq07Level(IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql) @@ -1066,6 +1016,7 @@ HalpDismissIrq07Level(IN KIRQL Irql, } VOID +__cdecl HalpHardwareInterruptLevel(VOID) { PKPCR Pcr = KeGetPcr(); @@ -1241,6 +1192,7 @@ HalEndSystemInterrupt(IN KIRQL OldIrql, { /* Now handle pending software interrupt */ SWInterruptHandlerTable2[PendingIrql](TrapFrame); + UNREACHABLE; } } } @@ -1249,8 +1201,8 @@ HalEndSystemInterrupt(IN KIRQL OldIrql, /* SOFTWARE INTERRUPT TRAPS ***************************************************/ FORCEINLINE -VOID DECLSPEC_NORETURN +VOID _HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame) { KIRQL CurrentIrql; @@ -1278,8 +1230,8 @@ _HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame) KiEoiHelper(TrapFrame); } -VOID DECLSPEC_NORETURN +VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame) { @@ -1287,8 +1239,8 @@ HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame) _HalpApcInterruptHandler(TrapFrame); } -VOID DECLSPEC_NORETURN +VOID FASTCALL HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame) { @@ -1327,8 +1279,8 @@ _HalpDispatchInterruptHandler(VOID) return CurrentIrql; } -VOID DECLSPEC_NORETURN +VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame) { @@ -1345,6 +1297,7 @@ HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame) } VOID +__cdecl HalpDispatchInterrupt2(VOID) { ULONG PendingIrqlMask, PendingIrql;