[PCI]: Add PCI IRQ Routing Table structure to Shared, Internal PCI Header (based...
authorSir Richard <sir_richard@svn.reactos.org>
Sun, 27 Jun 2010 23:54:47 +0000 (23:54 +0000)
committerSir Richard <sir_richard@svn.reactos.org>
Sun, 27 Jun 2010 23:54:47 +0000 (23:54 +0000)
[PCI]: Remove HAL-internal PCI definitions from the existing "Shared/Internal" PCI Header which existed in NTOS's private include directory, and move them to HAL-internal headers.
[PCI]: Remove remaining shared PCI definitions from that same header, and put them in the new Shared/Internal PCI Header.
[PCI]: Remove duplicated PCI definitions from FreeLDR, and use thw new Shared/Internal PCI Header.

svn path=/trunk/; revision=47886

reactos/boot/freeldr/freeldr/arch/i386/hwpci.c
reactos/boot/freeldr/freeldr/include/freeldr.h
reactos/hal/halx86/include/bus.h
reactos/hal/halx86/include/hal.h
reactos/include/reactos/drivers/pci/pci.h
reactos/ntoskrnl/include/internal/pci.h [deleted file]

index 611bb10..20960cf 100644 (file)
 #define NDEBUG
 #include <debug.h>
 
-#include <pshpack1.h>
-
-typedef struct _ROUTING_SLOT
-{
-  UCHAR  BusNumber;
-  UCHAR  DeviceNumber;
-  UCHAR  LinkA;
-  USHORT BitmapA;
-  UCHAR  LinkB;
-  USHORT BitmapB;
-  UCHAR  LinkC;
-  USHORT BitmapC;
-  UCHAR  LinkD;
-  USHORT BitmapD;
-  UCHAR  SlotNumber;
-  UCHAR  Reserved;
-} ROUTING_SLOT, *PROUTING_SLOT;
-
-typedef struct _PCI_IRQ_ROUTING_TABLE
-{
-  ULONG Signature;
-  USHORT Version;
-  USHORT Size;
-  UCHAR  RouterBus;
-  UCHAR  RouterSlot;
-  USHORT ExclusiveIRQs;
-  ULONG CompatibleRouter;
-  ULONG MiniportData;
-  UCHAR  Reserved[11];
-  UCHAR  Checksum;
-  ROUTING_SLOT Slot[1];
-} PCI_IRQ_ROUTING_TABLE, *PPCI_IRQ_ROUTING_TABLE;
-
-#include <poppack.h>
-
-typedef struct _PCI_REGISTRY_INFO
-{
-    UCHAR MajorRevision;
-    UCHAR MinorRevision;
-    UCHAR NoBuses;
-    UCHAR HardwareMechanism;
-} PCI_REGISTRY_INFO, *PPCI_REGISTRY_INFO;
-
 static PPCI_IRQ_ROUTING_TABLE
 GetPciIrqRoutingTable(VOID)
 {
@@ -77,14 +34,14 @@ GetPciIrqRoutingTable(VOID)
   Table = (PPCI_IRQ_ROUTING_TABLE)0xF0000;
   while ((ULONG_PTR)Table < 0x100000)
     {
-      if (Table->Signature == 0x52495024)
+      if (Table->Signature == 'RIP$')
        {
          DPRINTM(DPRINT_HWDETECT,
                    "Found signature\n");
 
          Ptr = (PUCHAR)Table;
          Sum = 0;
-         for (i = 0; i < Table->Size; i++)
+         for (i = 0; i < Table->TableSize; i++)
            {
              Sum += Ptr[i];
            }
@@ -156,11 +113,11 @@ DetectPciIrqRoutingTable(PCONFIGURATION_COMPONENT_DATA BusKey)
   Table = GetPciIrqRoutingTable();
   if (Table != NULL)
     {
-      DPRINTM(DPRINT_HWDETECT, "Table size: %u\n", Table->Size);
+      DPRINTM(DPRINT_HWDETECT, "Table size: %u\n", Table->TableSize);
 
       /* Set 'Configuration Data' value */
       Size = FIELD_OFFSET(CM_PARTIAL_RESOURCE_LIST, PartialDescriptors) +
-         2 * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR) + Table->Size;
+         2 * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR) + Table->TableSize;
       PartialResourceList = MmHeapAlloc(Size);
       if (PartialResourceList == NULL)
       {
@@ -184,10 +141,10 @@ DetectPciIrqRoutingTable(PCONFIGURATION_COMPONENT_DATA BusKey)
       PartialDescriptor = &PartialResourceList->PartialDescriptors[1];
       PartialDescriptor->Type = CmResourceTypeDeviceSpecific;
       PartialDescriptor->ShareDisposition = CmResourceShareUndetermined;
-      PartialDescriptor->u.DeviceSpecificData.DataSize = Table->Size;
+      PartialDescriptor->u.DeviceSpecificData.DataSize = Table->TableSize;
 
       memcpy(&PartialResourceList->PartialDescriptors[2],
-          Table, Table->Size);
+          Table, Table->TableSize);
 
       FldrCreateComponentKey(BusKey,
                              PeripheralClass,
index c80fed6..eaea923 100644 (file)
 #include <comm.h>
 /* Swap */
 #include <bytesex.h>
+/* Internal shared PCI header */
+#include <drivers/pci/pci.h>
 
 VOID BootMain(LPSTR CmdLine);
 VOID RunLoader(VOID);
index 3f6e1d6..67a57cf 100644 (file)
@@ -158,6 +158,77 @@ typedef struct _PCI_REGISTRY_INFO_INTERNAL
     PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
 } PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
 
+//
+// PCI Type 1 Ports
+//
+#define PCI_TYPE1_ADDRESS_PORT      (PULONG)0xCF8
+#define PCI_TYPE1_DATA_PORT         0xCFC
+
+//
+// PCI Type 2 Ports
+//
+#define PCI_TYPE2_CSE_PORT          (PUCHAR)0xCF8
+#define PCI_TYPE2_FORWARD_PORT      (PUCHAR)0xCFA
+#define PCI_TYPE2_ADDRESS_BASE      0xC
+
+//
+// PCI Type 1 Configuration Register
+//
+typedef struct _PCI_TYPE1_CFG_BITS
+{
+    union
+    {
+        struct
+        {
+            ULONG Reserved1:2;
+            ULONG RegisterNumber:6;
+            ULONG FunctionNumber:3;
+            ULONG DeviceNumber:5;
+            ULONG BusNumber:8;
+            ULONG Reserved2:7;
+            ULONG Enable:1;
+        } bits;
+
+        ULONG AsULONG;
+    } u;
+} PCI_TYPE1_CFG_BITS, *PPCI_TYPE1_CFG_BITS;
+
+//
+// PCI Type 2 CSE Register
+//
+typedef struct _PCI_TYPE2_CSE_BITS
+{
+    union
+    {
+        struct
+        {
+            UCHAR Enable:1;
+            UCHAR FunctionNumber:3;
+            UCHAR Key:4;
+        } bits;
+
+        UCHAR AsUCHAR;
+    } u;
+} PCI_TYPE2_CSE_BITS, PPCI_TYPE2_CSE_BITS;
+
+//
+// PCI Type 2 Address Register
+//
+typedef struct _PCI_TYPE2_ADDRESS_BITS
+{
+    union
+    {
+        struct
+        {
+            USHORT RegisterNumber:8;
+            USHORT Agent:4;
+            USHORT AddressBase:4;
+        } bits;
+
+        USHORT AsUSHORT;
+    } u;
+} PCI_TYPE2_ADDRESS_BITS, *PPCI_TYPE2_ADDRESS_BITS;
+
 typedef struct _PCI_TYPE0_CFG_CYCLE_BITS
 {
     union
index 0c3654f..f18d872 100644 (file)
 #include <arc/arc.h>
 #include <ntndk.h>
 
+/* Internal shared PCI header */
+#include <drivers/pci/pci.h>
+
 /* Internal kernel headers */
-#include "internal/pci.h"
 #define KeGetCurrentThread _KeGetCurrentThread
 #ifdef _M_AMD64
 #include <internal/amd64/ke.h>
index ad812ff..5833675 100644 (file)
 #define PCI_ASSERT_BRIDGE_RESET                             0x0040
 #define PCI_ENABLE_BRIDGE_VGA_16BIT                         0x0010
 
+//
+// PCI IRQ Routing Table in BIOS/Registry (Signature: PIR$)
+//
+#include <pshpack1.h>
+typedef struct _PIN_INFO
+{
+    UCHAR Link;
+    USHORT InterruptMap;
+} PIN_INFO, *PPIN_INFO;
+    
+typedef struct _SLOT_INFO
+{
+    UCHAR BusNumber;
+    UCHAR DeviceNumber;
+    PIN_INFO PinInfo[4];
+    UCHAR SlotNumber;
+    UCHAR Reserved;
+} SLOT_INFO, *PSLOT_INFO;
+
+typedef struct _PCI_IRQ_ROUTING_TABLE
+{
+    ULONG Signature;
+    USHORT Version;
+    USHORT TableSize;
+    UCHAR RouterBus;
+    UCHAR RouterDevFunc;
+    USHORT ExclusiveIRQs;
+    ULONG CompatibleRouter;
+    ULONG MiniportData;
+    UCHAR Reserved[11];
+    UCHAR Checksum;
+    SLOT_INFO Slot[ANYSIZE_ARRAY];
+} PCI_IRQ_ROUTING_TABLE, *PPCI_IRQ_ROUTING_TABLE;
+#include <poppack.h>
+
+//
+// PCI Registry Information
+//
+typedef struct _PCI_REGISTRY_INFO
+{
+    UCHAR MajorRevision;
+    UCHAR MinorRevision;
+    UCHAR NoBuses; // Number Of Buses
+    UCHAR HardwareMechanism;
+} PCI_REGISTRY_INFO, *PPCI_REGISTRY_INFO;
+
+//
+// PCI Card Descriptor in Registry
+//
+typedef struct _PCI_CARD_DESCRIPTOR
+{
+    ULONG Flags;
+    USHORT VendorID;
+    USHORT DeviceID;
+    USHORT RevisionID;
+    USHORT SubsystemVendorID;
+    USHORT SubsystemID;
+    USHORT Reserved;
+} PCI_CARD_DESCRIPTOR, *PPCI_CARD_DESCRIPTOR;
 
 /* EOF */
diff --git a/reactos/ntoskrnl/include/internal/pci.h b/reactos/ntoskrnl/include/internal/pci.h
deleted file mode 100644 (file)
index cba5dc5..0000000
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * PROJECT:         ReactOS Kernel
- * LICENSE:         GPL - See COPYING in the top level directory
- * FILE:            ntoskrnl/include/hal.h
- * PURPOSE:         Internal header for PCI Support
- * PROGRAMMERS:     Alex Ionescu (alex.ionescu@reactos.org)
- */
-
-#pragma once
-
-//
-// PCI Type 1 Ports
-//
-#define PCI_TYPE1_ADDRESS_PORT      (PULONG)0xCF8
-#define PCI_TYPE1_DATA_PORT         0xCFC
-
-//
-// PCI Type 2 Ports
-//
-#define PCI_TYPE2_CSE_PORT          (PUCHAR)0xCF8
-#define PCI_TYPE2_FORWARD_PORT      (PUCHAR)0xCFA
-#define PCI_TYPE2_ADDRESS_BASE      0xC
-
-//
-// PCI Type 1 Configuration Register
-//
-typedef struct _PCI_TYPE1_CFG_BITS
-{
-    union
-    {
-        struct
-        {
-            ULONG Reserved1:2;
-            ULONG RegisterNumber:6;
-            ULONG FunctionNumber:3;
-            ULONG DeviceNumber:5;
-            ULONG BusNumber:8;
-            ULONG Reserved2:7;
-            ULONG Enable:1;
-        } bits;
-
-        ULONG AsULONG;
-    } u;
-} PCI_TYPE1_CFG_BITS, *PPCI_TYPE1_CFG_BITS;
-
-//
-// PCI Type 2 CSE Register
-//
-typedef struct _PCI_TYPE2_CSE_BITS
-{
-    union
-    {
-        struct
-        {
-            UCHAR Enable:1;
-            UCHAR FunctionNumber:3;
-            UCHAR Key:4;
-        } bits;
-
-        UCHAR AsUCHAR;
-    } u;
-} PCI_TYPE2_CSE_BITS, PPCI_TYPE2_CSE_BITS;
-
-//
-// PCI Type 2 Address Register
-//
-typedef struct _PCI_TYPE2_ADDRESS_BITS
-{
-    union
-    {
-        struct
-        {
-            USHORT RegisterNumber:8;
-            USHORT Agent:4;
-            USHORT AddressBase:4;
-        } bits;
-
-        USHORT AsUSHORT;
-    } u;
-} PCI_TYPE2_ADDRESS_BITS, *PPCI_TYPE2_ADDRESS_BITS;
-
-//
-// PCI Registry Information
-//
-typedef struct _PCI_REGISTRY_INFO
-{
-    UCHAR MajorRevision;
-    UCHAR MinorRevision;
-    UCHAR NoBuses; // Number Of Buses
-    UCHAR HardwareMechanism;
-} PCI_REGISTRY_INFO, *PPCI_REGISTRY_INFO;
-
-//
-// PCI Card Descriptor in Registry
-//
-typedef struct _PCI_CARD_DESCRIPTOR
-{
-    ULONG Flags;
-    USHORT VendorID;
-    USHORT DeviceID;
-    USHORT RevisionID;
-    USHORT SubsystemVendorID;
-    USHORT SubsystemID;
-    USHORT Reserved;
-} PCI_CARD_DESCRIPTOR, *PPCI_CARD_DESCRIPTOR;