[ROSAPPS][PICE] Fix a glitch at two places where code intends to replace invalid...
authorJoachim Henze <Joachim.Henze@reactos.org>
Thu, 30 May 2019 10:40:54 +0000 (12:40 +0200)
committerJoachim Henze <Joachim.Henze@reactos.org>
Thu, 30 May 2019 10:40:54 +0000 (12:40 +0200)
Found by some static code analysis tool reporting 'Condition always false'.
The fix is a selective back-port from the more recent version of pICE hardware.c
Revision: 1.6, Date: 2004/02/17 23:07:36

The most recent source of pICE atm can be found at
https://sourceforge.net/projects/pice/files/pICE%20source/build_20/

Thanks to DougLyons and JIRA user 'maddin200'.

modules/rosapps/applications/sysutils/utils/pice/module/hardware.c

index 0a067fd..65864a0 100644 (file)
@@ -283,7 +283,7 @@ BOOLEAN AddToRingBuffer(LPSTR p)
                }
                else
                {
-                       if((UCHAR)p[i]<0x20 && (UCHAR)p[i]>0x7f)
+                       if((UCHAR)p[i]<0x20 || (UCHAR)p[i]>0x7f)
                                p[i]=0x20;
 
                        aBuffers[ulInPos][j++] = p[i];
@@ -873,7 +873,7 @@ void Print(USHORT Window,LPSTR p)
                        }
                        else
                        {
-                               if((UCHAR)p[i]<0x20 && (UCHAR)p[i]>0x7f)
+                               if((UCHAR)p[i]<0x20 || (UCHAR)p[i]>0x7f)
                                        p[i]=0x20;
 
                 if(bOutput)