/* INCLUDES *******************************************************************/
#include <freeldr.h>
+#include <internal/arm/ke.h>
+#include <internal/arm/mm.h>
+#include <internal/arm/intrin_i.h>
/* GLOBALS ********************************************************************/
-typedef union _ARM_PTE
-{
- union
- {
- struct
- {
- ULONG Type:2;
- ULONG Unused:30;
- } Fault;
- struct
- {
- ULONG Type:2;
- ULONG Reserved:3;
- ULONG Domain:4;
- ULONG Ignored:1;
- ULONG BaseAddress:22;
- } Coarse;
- struct
- {
- ULONG Type:2;
- ULONG Buffered:1;
- ULONG Cached:1;
- ULONG Reserved:1;
- ULONG Domain:4;
- ULONG Ignored:1;
- ULONG Access:2;
- ULONG Ignored1:8;
- ULONG BaseAddress:12;
- } Section;
- struct
- {
- ULONG Type:2;
- ULONG Reserved:3;
- ULONG Domain:4;
- ULONG Ignored:3;
- ULONG BaseAddress:20;
- } Fine;
- } L1;
- union
- {
- struct
- {
- ULONG Type:2;
- ULONG Unused:30;
- } Fault;
- struct
- {
- ULONG Type:2;
- ULONG Buffered:1;
- ULONG Cached:1;
- ULONG Access0:2;
- ULONG Access1:2;
- ULONG Access2:2;
- ULONG Access3:2;
- ULONG Ignored:4;
- ULONG BaseAddress:16;
- } Large;
- struct
- {
- ULONG Type:2;
- ULONG Buffered:1;
- ULONG Cached:1;
- ULONG Access0:2;
- ULONG Access1:2;
- ULONG Access2:2;
- ULONG Access3:2;
- ULONG BaseAddress:20;
- } Small;
- struct
- {
- ULONG Type:2;
- ULONG Buffered:1;
- ULONG Cached:1;
- ULONG Access0:2;
- ULONG Ignored:4;
- ULONG BaseAddress:22;
- } Tiny;
- } L2;
- ULONG AsUlong;
-} ARM_PTE, *PARM_PTE;
-
-typedef struct _ARM_TRANSLATION_TABLE
-{
- ARM_PTE Pte[4096];
-} ARM_TRANSLATION_TABLE, *PARM_TRANSLATION_TABLE;
-
-typedef union _ARM_TTB_REGISTER
-{
- struct
- {
- ULONG Reserved:14;
- ULONG BaseAddress:18;
- };
- ULONG AsUlong;
-} ARM_TTB_REGISTER;
-
-typedef enum _ARM_L1_PTE_TYPE
-{
- FaultPte,
- CoarsePte,
- SectionPte,
- FinePte
-} ARM_L1_PTE_TYPE;
-
-typedef enum _ARM_PTE_ACCESS
-{
- FaultAccess,
- SupervisorAccess,
- SharedAccess,
- UserAccess
-} ARM_PTE_ACCESS;
-
-typedef enum _ARM_DOMAIN
-{
- FaultDomain,
- ClientDomain,
- InvalidDomain,
- ManagerDomain
-} ARM_DOMAIN;
-
-typedef union _ARM_DOMAIN_REGISTER
-{
- struct
- {
- ULONG Domain0:2;
- ULONG Domain1:2;
- ULONG Domain2:2;
- ULONG Domain3:2;
- ULONG Domain4:2;
- ULONG Domain5:2;
- ULONG Domain6:2;
- ULONG Domain7:2;
- ULONG Domain8:2;
- ULONG Domain9:2;
- ULONG Domain10:2;
- ULONG Domain11:2;
- ULONG Domain12:2;
- ULONG Domain13:2;
- ULONG Domain14:2;
- ULONG Domain15:2;
- };
- ULONG AsUlong;
-} ARM_DOMAIN_REGISTER;
-
-typedef union _ARM_CONTROL_REGISTER
-{
- struct
- {
- ULONG MmuEnabled:1;
- ULONG AlignmentFaultsEnabled:1;
- ULONG DCacheEnabled:1;
- ULONG Sbo:3;
- ULONG BigEndianEnabled:1;
- ULONG System:1;
- ULONG Rom:1;
- ULONG Sbz:2;
- ULONG ICacheEnabled:1;
- ULONG HighVectors:1;
- ULONG RoundRobinReplacementEnabled:1;
- ULONG Armv4Compat:1;
- ULONG Sbo1:1;
- ULONG Sbz1:1;
- ULONG Sbo2:1;
- ULONG Reserved:14;
- };
- ULONG AsUlong;
-} ARM_CONTROL_REGISTER, *PARM_CONTROL_REGISTER;
-
-typedef enum _ARM_DOMAINS
-{
- Domain0
-} ARM_DOMAINS;
-
-#define TTB_SHIFT 20
-
ULONG PageDirectoryStart, PageDirectoryEnd;
LOADER_PARAMETER_BLOCK ArmLoaderBlock;
LOADER_PARAMETER_EXTENSION ArmExtension;
return FALSE;
}
-ARM_CONTROL_REGISTER
-FORCEINLINE
-ArmControlRegisterGet(VOID)
-{
- ARM_CONTROL_REGISTER Value;
- __asm__ __volatile__ ("mrc p15, 0, %0, c1, c0, 0" : "=r"(Value.AsUlong) : : "cc");
- return Value;
-}
-
-VOID
-FORCEINLINE
-ArmControlRegisterSet(IN ARM_CONTROL_REGISTER ControlRegister)
-{
- __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ControlRegister.AsUlong) : "cc");
-}
-
-VOID
-FORCEINLINE
-ArmMmuTtbSet(IN ARM_TTB_REGISTER Ttb)
-{
- __asm__ __volatile__ ("mcr p15, 0, %0, c2, c0, 0" : : "r"(Ttb.AsUlong) : "cc");
-}
-
-VOID
-FORCEINLINE
-ArmMmuDomainRegisterSet(IN ARM_DOMAIN_REGISTER DomainRegister)
-{
- __asm__ __volatile__ ("mcr p15, 0, %0, c3, c0, 0" : : "r"(DomainRegister.AsUlong) : "cc");
-}
-
VOID
ArmSetupPageDirectory(VOID)
{
//
TtbRegister.AsUlong = (ULONG)TranslationTable;
ASSERT(TtbRegister.Reserved == 0);
- ArmMmuTtbSet(TtbRegister);
+ KeArmTranslationTableRegisterSet(TtbRegister);
//
// Use Domain 0, enforce AP bits (client)
//
DomainRegister.AsUlong = 0;
DomainRegister.Domain0 = ClientDomain;
- ArmMmuDomainRegisterSet(DomainRegister);
+ KeArmDomainRegisterSet(DomainRegister);
//
// Set Fault PTEs everywhere
//
// Enable MMU, DCache and ICache
//
- ControlRegister = ArmControlRegisterGet();
+ ControlRegister = KeArmControlRegisterGet();
ControlRegister.MmuEnabled = TRUE;
ControlRegister.ICacheEnabled = TRUE;
ControlRegister.DCacheEnabled = TRUE;
- ArmControlRegisterSet(ControlRegister);
+ KeArmControlRegisterSet(ControlRegister);
//
// Jump to Kernel
#ifndef _INTRIN_INTERNAL_
#define _INTRIN_INTERNAL_
-static __inline__ __attribute__((always_inline)) void KeArchHaltProcessor(void)
+FORCEINLINE
+VOID
+KeArmHaltProcessor(void)
{
//
// Enter Wait-For-Interrupt Mode
//
- __asm__ __volatile__
- (
- "mov r1, #0;"
- "mcr p15, 0, r1, c7, c0, 4;"
- );
+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c0, 4" : : "r"(0) : "cc");
}
-#endif
+FORCEINLINE
+ARM_CONTROL_REGISTER
+KeArmControlRegisterGet(VOID)
+{
+ ARM_CONTROL_REGISTER Value;
+ __asm__ __volatile__ ("mrc p15, 0, %0, c1, c0, 0" : "=r"(Value.AsUlong) : : "cc");
+ return Value;
+}
-/* EOF */
+FORCEINLINE
+VOID
+KeArmControlRegisterSet(IN ARM_CONTROL_REGISTER ControlRegister)
+{
+ __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ControlRegister.AsUlong) : "cc");
+}
+
+FORCEINLINE
+VOID
+KeArmTranslationTableRegisterSet(IN ARM_TTB_REGISTER Ttb)
+{
+ __asm__ __volatile__ ("mcr p15, 0, %0, c2, c0, 0" : : "r"(Ttb.AsUlong) : "cc");
+}
+
+FORCEINLINE
+VOID
+KeArmDomainRegisterSet(IN ARM_DOMAIN_REGISTER DomainRegister)
+{
+ __asm__ __volatile__ ("mcr p15, 0, %0, c3, c0, 0" : : "r"(DomainRegister.AsUlong) : "cc");
+}
+
+#define KeArchHaltProcessor KeArmHaltProcessor
+#endif
#pragma GCC system_header
#endif
+typedef union _ARM_TTB_REGISTER
+{
+ struct
+ {
+ ULONG Reserved:14;
+ ULONG BaseAddress:18;
+ };
+ ULONG AsUlong;
+} ARM_TTB_REGISTER;
+
+typedef union _ARM_DOMAIN_REGISTER
+{
+ struct
+ {
+ ULONG Domain0:2;
+ ULONG Domain1:2;
+ ULONG Domain2:2;
+ ULONG Domain3:2;
+ ULONG Domain4:2;
+ ULONG Domain5:2;
+ ULONG Domain6:2;
+ ULONG Domain7:2;
+ ULONG Domain8:2;
+ ULONG Domain9:2;
+ ULONG Domain10:2;
+ ULONG Domain11:2;
+ ULONG Domain12:2;
+ ULONG Domain13:2;
+ ULONG Domain14:2;
+ ULONG Domain15:2;
+ };
+ ULONG AsUlong;
+} ARM_DOMAIN_REGISTER;
+
+typedef union _ARM_CONTROL_REGISTER
+{
+ struct
+ {
+ ULONG MmuEnabled:1;
+ ULONG AlignmentFaultsEnabled:1;
+ ULONG DCacheEnabled:1;
+ ULONG Sbo:3;
+ ULONG BigEndianEnabled:1;
+ ULONG System:1;
+ ULONG Rom:1;
+ ULONG Sbz:2;
+ ULONG ICacheEnabled:1;
+ ULONG HighVectors:1;
+ ULONG RoundRobinReplacementEnabled:1;
+ ULONG Armv4Compat:1;
+ ULONG Sbo1:1;
+ ULONG Sbz1:1;
+ ULONG Sbo2:1;
+ ULONG Reserved:14;
+ };
+ ULONG AsUlong;
+} ARM_CONTROL_REGISTER, *PARM_CONTROL_REGISTER;
+
+typedef enum _ARM_DOMAINS
+{
+ Domain0,
+ Domain1,
+ Domain2,
+ Domain3,
+ Domain4,
+ Domain5,
+ Domain6,
+ Domain7,
+ Domain8,
+ Domain9,
+ Domain10,
+ Domain11,
+ Domain12,
+ Domain13,
+ Domain14,
+ Domain15
+} ARM_DOMAINS;
+
VOID
NTAPI
KeArmInitThreadWithContext(
#define KeArchInitThreadWithContext KeArmInitThreadWithContext
-#endif
\ No newline at end of file
+#endif