#define MI_SYSTEM_PTE_START (PVOID)0xFFFFFAA000000000ULL
#define MI_PAGED_POOL_START (PVOID)0xFFFFFA8000000000ULL
#define MI_NON_PAGED_SYSTEM_START_MIN 0xFFFFFAA000000000ULL
+#define MI_PFN_DATABASE (PVOID)0xFFFFFAC000000000ULL
#define MI_NONPAGED_POOL_END (PVOID)0xFFFFFAE000000000ULL
#define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
return (PVOID)Temp;
}
+BOOLEAN
+FORCEINLINE
+MiIsPdeForAddressValid(PVOID Address)
+{
+ return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
+ (MiAddressToPpe(Address)->u.Hard.Valid) &&
+ (MiAddressToPde(Address)->u.Hard.Valid));
+}
+
//#define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
//#define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
//#define ADDR_TO_PTE_OFFSET(v) ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
IN PVOID TrapInformation)
{
KIRQL OldIrql = KeGetCurrentIrql(), LockIrql;
- PMMPTE PointerPde, PointerPte;
+ PMMPTE PointerPte;
MMPTE TempPte;
PETHREAD CurrentThread;
NTSTATUS Status;
// Get the PTE and PDE
//
PointerPte = MiAddressToPte(Address);
- PointerPde = MiAddressToPde(Address);
//
// Check for dispatch-level snafu
//
// Is the PDE valid?
//
- if (!PointerPde->u.Hard.Valid == 0)
+ if (!MiIsPdeForAddressValid(Address))
{
//
// Debug spew (eww!)
//
// Now we SHOULD be good
//
- if (PointerPde->u.Hard.Valid == 0)
+ if (!MiIsPdeForAddressValid(Address))
{
//
// FIXFIX: Do the S-LIST hack
//
// Check for a fault on the page table or hyperspace itself
- // FIXME: Use MmHyperSpaceEnd
//
- if ((Address >= (PVOID)PTE_BASE) && (Address <= (PVOID)0xC0800000))
+ if ((Address >= (PVOID)PTE_BASE) && (Address <= (PVOID)HYPER_SPACE_END))
{
//
// This might happen...not sure yet
}
VOID
+NTAPI
MxMapPage(PVOID Address)
{
MMPTE TmplPte, *Pte;
MxPfnSizeInBytes = ROUND_TO_PAGES((MmHighestPhysicalPage + 1) * sizeof(MMPFN));
MxPfnAllocation = MxPfnSizeInBytes >> PAGE_SHIFT;
- /* Sinply start at hardcoded address */
- MmPfnDatabase = (PVOID)0xFFFFFAC000000000ULL;
+ /* Simply start at hardcoded address */
+ MmPfnDatabase = MI_PFN_DATABASE;
/* Loop the memory descriptors */
for (ListEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
MiInitializePageTable()
{
ULONG64 PageFrameOffset;
- PMMPTE Pte, StartPte, EndPte;
- MMPTE TmplPte;
+ MMPTE TmplPte, *Pte;
PFN_NUMBER PageCount;
/* HACK: don't use freeldr debug print anymore */
__writecr4(__readcr4() | CR4_PGE);
ASSERT(__readcr4() & CR4_PGE);
- /* Set user mode address range */
- StartPte = MiAddressToPxe(0);
- EndPte = MiAddressToPxe(MmHighestUserAddress);
-
/* Loop the user mode PXEs */
- for (Pte = StartPte; Pte <= EndPte; Pte++)
+ for (Pte = MiAddressToPxe(0);
+ Pte <= MiAddressToPxe(MmHighestUserAddress);
+ Pte++)
{
/* Zero the PXE, clear all mappings */
Pte->u.Long = 0;
/* Create PDPTs (72 KB) for shared system address space,
* skip page tables and hyperspace */
- /* Set the range */
- StartPte = MiAddressToPxe((PVOID)(HYPER_SPACE_END + 1));
- EndPte = MiAddressToPxe(MI_HIGHEST_SYSTEM_ADDRESS);
-
/* Loop the PXEs */
- for (Pte = StartPte; Pte <= EndPte; Pte++)
+ for (Pte = MiAddressToPxe((PVOID)(HYPER_SPACE_END + 1));
+ Pte <= MiAddressToPxe(MI_HIGHEST_SYSTEM_ADDRESS);
+ Pte++)
{
/* Is the PXE already valid? */
if (!Pte->u.Hard.Valid)
ExAllocatePoolWithTag(NonPagedPool, Size, ' mM');
ASSERT(MmPagedPoolInfo.PagedPoolAllocationMap);
- DPRINT1("BitMapSize = 0x%lx, Size = 0x%lx\n", BitMapSize, Size);
// Initialize it such that at first, only the first page's worth of PTEs is
// marked as allocated (incidentially, the first PDE we allocated earlier).
RtlInitializeBitMap(MmPagedPoolInfo.PagedPoolAllocationMap,
ExAllocatePoolWithTag(NonPagedPool, Size, ' mM');
ASSERT(MmPagedPoolInfo.EndOfPagedPoolBitmap);
- DPRINT1("PagedPoolAllocationMap=%p, EndOfPagedPoolBitmap=%p\n",
- MmPagedPoolInfo.PagedPoolAllocationMap, MmPagedPoolInfo.EndOfPagedPoolBitmap);
-
/* Initialize the bitmap */
RtlInitializeBitMap(MmPagedPoolInfo.EndOfPagedPoolBitmap,
(PULONG)(MmPagedPoolInfo.EndOfPagedPoolBitmap + 1),