<?xml version="1.0"?>
<!DOCTYPE group SYSTEM "../tools/rbuild/project.dtd">
<group xmlns:xi="http://www.w3.org/2001/XInclude">
- <if property="ARCH" value="i386">
- <directory name="halx86">
- <xi:include href="halx86/hal_generic.rbuild" />
- <xi:include href="halx86/hal_generic_up.rbuild" />
- <xi:include href="halx86/hal_generic_pc.rbuild" />
- <xi:include href="halx86/halup.rbuild" />
- <if property="BUILD_MP" value="1">
- <xi:include href="halx86/halmp.rbuild" />
- </if>
- <xi:include href="halx86/halxbox.rbuild" />
- </directory>
- </if>
+ <directory name="halx86">
+ <xi:include href="halx86/directory.rbuild" />
+ </directory>
+
<if property="ARCH" value="powerpc">
<directory name="halppc">
<xi:include href="halppc/directory.rbuild" />
</directory>
</if>
<if property="ARCH" value="amd64">
- <directory name="halx86">
- <xi:include href="halx86/hal_generic.rbuild" />
- </directory>
<directory name="halamd64">
<xi:include href="halamd64/directory.rbuild" />
</directory>
--- /dev/null
+<?xml version="1.0"?>
+<!DOCTYPE group SYSTEM "../tools/rbuild/project.dtd">
+<group xmlns:xi="http://www.w3.org/2001/XInclude">
+
+ <xi:include href="hal_generic.rbuild" />
+ <xi:include href="hal_generic_pc.rbuild" />
+ <xi:include href="hal_generic_up.rbuild" />
+
+ <if property="ARCH" value="i386">
+ <xi:include href="halup.rbuild" />
+ <xi:include href="halxbox.rbuild" />
+ <if property="BUILD_MP" value="1">
+ <xi:include href="halmp.rbuild" />
+ </if>
+ </if>
+
+ <!-- if property="ARCH" value="amd64">
+ <xi:include href="halamd64.rbuild" />
+ </if -->
+
+</group>
<include base="ntoskrnl">include</include>
<define name="_NTHAL_" />
<directory name="up">
- <file>irq.S</file>
<file>processor.c</file>
- <file>spinlock.c</file>
+ <if property="ARCH" value="i386">
+ <file>irq.S</file>
+ <file>spinlock.c</file>
+ </if>
</directory>
</module>
</group>
IN PLOADER_PARAMETER_BLOCK LoaderBlock)
{
/* Set default IDR and stall count */
+#ifdef _M_IX86
KeGetPcr()->IDR = 0xFFFFFFFB;
+#endif
KeGetPcr()->StallScaleFactor = INITIAL_STALL_COUNT;
/* Update the interrupt affinity and processor mask */