[UNIATA]
authorAleksey Bragin <aleksey@reactos.org>
Thu, 23 Dec 2010 16:59:55 +0000 (16:59 +0000)
committerAleksey Bragin <aleksey@reactos.org>
Thu, 23 Dec 2010 16:59:55 +0000 (16:59 +0000)
- Update uniata to 0.40a1. Prepared by Samuel Serapion, edited by me.
See issue #5762 for more details.

svn path=/trunk/; revision=50115

17 files changed:
reactos/drivers/storage/ide/uniata/atapi.h
reactos/drivers/storage/ide/uniata/bm_devs.h
reactos/drivers/storage/ide/uniata/bsmaster.h
reactos/drivers/storage/ide/uniata/config.h
reactos/drivers/storage/ide/uniata/id_ata.cpp
reactos/drivers/storage/ide/uniata/id_dma.cpp
reactos/drivers/storage/ide/uniata/id_init.cpp
reactos/drivers/storage/ide/uniata/id_probe.cpp
reactos/drivers/storage/ide/uniata/id_queue.cpp
reactos/drivers/storage/ide/uniata/id_sata.cpp
reactos/drivers/storage/ide/uniata/id_sata.h
reactos/drivers/storage/ide/uniata/idedma.rc
reactos/drivers/storage/ide/uniata/inc/CrossNt.h
reactos/drivers/storage/ide/uniata/scsi.h
reactos/drivers/storage/ide/uniata/srb.h
reactos/drivers/storage/ide/uniata/todo.txt [new file with mode: 0644]
reactos/drivers/storage/ide/uniata/uniata_ver.h

index 2648d4b..1252df9 100644 (file)
@@ -952,7 +952,7 @@ AtapiSoftReset(
     AtapiWritePort1(&BaseIoAddress->AltStatus,IDE_DC_DISABLE_INTERRUPTS | IDE_DC_RESET_CONTROLLER );\
     ScsiPortStallExecution(50 * 1000);\
     AtapiWritePort1(&BaseIoAddress->AltStatus,IDE_DC_REENABLE_CONTROLLER);\
-     5 seconds for reset  \
+    // 5 seconds for reset \
     for (i = 0; i < 1000 * (1+11); i++) {\
         statusByte = AtapiReadPort1(&BaseIoAddress->AltStatus);\
         if (statusByte != IDE_STATUS_IDLE && statusByte != IDE_STATUS_SUCCESS) {\
index a001ef0..dbcbfa9 100644 (file)
@@ -1,6 +1,6 @@
 /*++
 
-Copyright (c) 2002-2005 Alexandr A. Telyatnikov (Alter)
+Copyright (c) 2002-2010 Alexandr A. Telyatnikov (Alter)
 
 Module Name:
     bm_devs.h
@@ -74,6 +74,7 @@ Revision History:
 
 #define         ATA_SA150               0x47 /*0x80*/
 #define         ATA_SA300               0x48 /*0x81*/
+#define         ATA_SA600               0x49 /*0x82*/
 
 // define PIO timings in nanoseconds
 #define         PIO0_TIMING             600
@@ -136,6 +137,7 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 
 #define ATA_ACER_LABS_ID       0x10b9
 #define ATA_ALI_1533            0x153310b9
+#define ATA_ALI_5228            0x522810b9
 #define ATA_ALI_5229            0x522910b9
 #define ATA_ALI_5281            0x528110b9
 #define ATA_ALI_5287            0x528710b9
@@ -153,6 +155,11 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define ATA_ATI_IXP600_S1       0x43801002
 #define ATA_ATI_IXP700          0x439c1002
 #define ATA_ATI_IXP700_S1       0x43901002
+#define        ATA_ATI_IXP700_S2       0x43911002
+#define        ATA_ATI_IXP700_S3       0x43921002
+#define        ATA_ATI_IXP700_S4       0x43931002
+#define        ATA_ATI_IXP800_S1       0x43941002
+#define        ATA_ATI_IXP800_S2       0x43951002
 
 #define ATA_CENATEK_ID          0x16ca
 #define ATA_CENATEK_ROCKET      0x000116ca
@@ -190,11 +197,11 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define ATA_I82801DB           0x24cb8086
 #define ATA_I82801DB_1         0x24ca8086
 #define ATA_I82801EB           0x24db8086
-#define ATA_I82801EB_1         0x24d18086
-#define ATA_I82801EB_2         0x24df8086
-#define ATA_I6300ESB           0x25a28086
-#define ATA_I6300ESB_1         0x25a38086
-#define ATA_I6300ESB_2         0x25b08086
+#define ATA_I82801EB_S1         0x24d18086
+#define ATA_I82801EB_R1         0x24df8086
+#define ATA_I6300ESB            0x25a28086
+#define ATA_I6300ESB_S1         0x25a38086
+#define ATA_I6300ESB_R1         0x25b08086
 #define ATA_I63XXESB2           0x269e8086
 #define ATA_I63XXESB2_S1        0x26808086
 #define ATA_I63XXESB2_S2        0x26818086
@@ -206,9 +213,71 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define ATA_I82801FB_M          0x26538086
 #define ATA_I82801GB            0x27df8086
 #define ATA_I82801GB_S1         0x27c08086
-#define ATA_I82801GB_R1         0x27c38086
 #define ATA_I82801GB_AH         0x27c18086
-#define ATA_I82801GB_M          0x27c58086
+#define ATA_I82801GB_R1         0x27c38086
+#define ATA_I82801GBM_S1        0x27c48086
+#define ATA_I82801GBM_AH        0x27c58086
+#define ATA_I82801GBM_R1        0x27c68086
+#define ATA_I82801HB_S1         0x28208086
+#define ATA_I82801HB_AH6        0x28218086
+#define ATA_I82801HB_R1         0x28228086
+#define ATA_I82801HB_AH4        0x28248086
+#define ATA_I82801HB_S2         0x28258086
+#define ATA_I82801HBM           0x28508086
+#define ATA_I82801HBM_S1        0x28288086
+#define ATA_I82801HBM_S2        0x28298086
+#define ATA_I82801HBM_S3        0x282a8086
+#define ATA_I82801IB_S1         0x29208086
+#define ATA_I82801IB_AH2        0x29218086
+#define ATA_I82801IB_AH6        0x29228086
+#define ATA_I82801IB_AH4        0x29238086
+#define ATA_I82801IB_R1         0x29258086
+#define ATA_I82801IB_S2         0x29268086
+#define ATA_I82801JIB_S1        0x3a208086
+#define ATA_I82801JIB_AH        0x3a228086
+#define ATA_I82801JIB_R1        0x3a258086
+#define ATA_I82801JIB_S2        0x3a268086
+#define ATA_I82801JD_S1         0x3a008086
+#define ATA_I82801JD_AH         0x3a028086
+#define ATA_I82801JD_R1         0x3a058086
+#define ATA_I82801JD_S2         0x3a068086
+#define ATA_I82801JI_S1         0x3a208086
+#define ATA_I82801JI_AH         0x3a228086
+#define ATA_I82801JI_R1         0x3a258086
+#define ATA_I82801JI_S2         0x3a268086
+
+#define ATA_5Series_S1          0x3b208086
+#define ATA_5Series_S2          0x3b218086
+#define ATA_5Series_AH1         0x3b228086
+#define ATA_5Series_AH2         0x3b238086
+#define ATA_5Series_R1          0x3b258086
+#define ATA_5Series_S3          0x3b268086
+#define ATA_5Series_S4          0x3b288086
+#define ATA_5Series_AH3         0x3b298086
+#define ATA_5Series_R2          0x3b2c8086
+#define ATA_5Series_S5          0x3b2d8086
+#define ATA_5Series_S6          0x3b2e8086
+#define ATA_5Series_AH4         0x3b2f8086
+
+#define ATA_CPT_S1              0x1c008086
+#define ATA_CPT_S2              0x1c018086
+#define ATA_CPT_AH1             0x1c028086
+#define ATA_CPT_AH2             0x1c038086
+#define ATA_CPT_R1              0x1c048086
+#define ATA_CPT_R2              0x1c058086
+#define ATA_CPT_S3              0x1c088086
+#define ATA_CPT_S4              0x1c098086
+
+#define ATA_I31244              0x32008086
+#define ATA_ISCH                0x811a8086
+
+#define ATA_JMICRON_ID          0x197b
+#define ATA_JMB360              0x2360197b
+#define ATA_JMB361              0x2361197b
+#define ATA_JMB363              0x2363197b
+#define ATA_JMB365              0x2365197b
+#define ATA_JMB366              0x2366197b
+#define ATA_JMB368              0x2368197b
 
 #define ATA_MARVELL_ID          0x11ab
 #define ATA_M88SX5040           0x504011ab
@@ -216,9 +285,16 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define ATA_M88SX5080           0x508011ab
 #define ATA_M88SX5081           0x508111ab
 #define ATA_M88SX6041           0x604111ab
+#define ATA_M88SX6042           0x604211ab
 #define ATA_M88SX6081           0x608111ab
+#define ATA_M88SX7042           0x704211ab
 #define ATA_M88SX6101           0x610111ab
+#define ATA_M88SX6102           0x610211ab
+#define ATA_M88SX6111           0x611111ab
+#define ATA_M88SX6121           0x612111ab
+#define ATA_M88SX6141           0x614111ab
 #define ATA_M88SX6145           0x614511ab
+#define ATA_MARVELL2_ID         0x1b4b
 
 #define ATA_MICRON_ID           0x1042
 #define ATA_MICRON_RZ1000       0x10001042
@@ -256,9 +332,78 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define ATA_NFORCE_MCP61_S2     0x03f610de
 #define ATA_NFORCE_MCP61_S3     0x03f710de
 #define ATA_NFORCE_MCP65        0x044810de
+#define ATA_NFORCE_MCP65_A0     0x044c10de
+#define ATA_NFORCE_MCP65_A1     0x044d10de
+#define ATA_NFORCE_MCP65_A2     0x044e10de
+#define ATA_NFORCE_MCP65_A3     0x044f10de
+#define ATA_NFORCE_MCP65_A4     0x045c10de
+#define ATA_NFORCE_MCP65_A5     0x045d10de
+#define ATA_NFORCE_MCP65_A6     0x045e10de
+#define ATA_NFORCE_MCP65_A7     0x045f10de
 #define ATA_NFORCE_MCP67        0x056010de
+#define ATA_NFORCE_MCP67_A0     0x055010de
+#define ATA_NFORCE_MCP67_A1     0x055110de
+#define ATA_NFORCE_MCP67_A2     0x055210de
+#define ATA_NFORCE_MCP67_A3     0x055310de
+#define ATA_NFORCE_MCP67_A4     0x055410de
+#define ATA_NFORCE_MCP67_A5     0x055510de
+#define ATA_NFORCE_MCP67_A6     0x055610de
+#define ATA_NFORCE_MCP67_A7     0x055710de
+#define ATA_NFORCE_MCP67_A8     0x055810de
+#define ATA_NFORCE_MCP67_A9     0x055910de
+#define ATA_NFORCE_MCP67_AA     0x055A10de
+#define ATA_NFORCE_MCP67_AB     0x055B10de
+#define ATA_NFORCE_MCP67_AC     0x058410de
 #define ATA_NFORCE_MCP73        0x056c10de
+#define ATA_NFORCE_MCP73_A0     0x07f010de
+#define ATA_NFORCE_MCP73_A1     0x07f110de
+#define ATA_NFORCE_MCP73_A2     0x07f210de
+#define ATA_NFORCE_MCP73_A3     0x07f310de
+#define ATA_NFORCE_MCP73_A4     0x07f410de
+#define ATA_NFORCE_MCP73_A5     0x07f510de
+#define ATA_NFORCE_MCP73_A6     0x07f610de
+#define ATA_NFORCE_MCP73_A7     0x07f710de
+#define ATA_NFORCE_MCP73_A8     0x07f810de
+#define ATA_NFORCE_MCP73_A9     0x07f910de
+#define ATA_NFORCE_MCP73_AA     0x07fa10de
+#define ATA_NFORCE_MCP73_AB     0x07fb10de
 #define ATA_NFORCE_MCP77        0x075910de
+#define ATA_NFORCE_MCP77_A0     0x0ad010de
+#define ATA_NFORCE_MCP77_A1     0x0ad110de
+#define ATA_NFORCE_MCP77_A2     0x0ad210de
+#define ATA_NFORCE_MCP77_A3     0x0ad310de
+#define ATA_NFORCE_MCP77_A4     0x0ad410de
+#define ATA_NFORCE_MCP77_A5     0x0ad510de
+#define ATA_NFORCE_MCP77_A6     0x0ad610de
+#define ATA_NFORCE_MCP77_A7     0x0ad710de
+#define ATA_NFORCE_MCP77_A8     0x0ad810de
+#define ATA_NFORCE_MCP77_A9     0x0ad910de
+#define ATA_NFORCE_MCP77_AA     0x0ada10de
+#define ATA_NFORCE_MCP77_AB     0x0adb10de
+#define ATA_NFORCE_MCP79_A0     0x0ab410de
+#define ATA_NFORCE_MCP79_A1     0x0ab510de
+#define ATA_NFORCE_MCP79_A2     0x0ab610de
+#define ATA_NFORCE_MCP79_A3     0x0ab710de
+#define ATA_NFORCE_MCP79_A4     0x0ab810de
+#define ATA_NFORCE_MCP79_A5     0x0ab910de
+#define ATA_NFORCE_MCP79_A6     0x0aba10de
+#define ATA_NFORCE_MCP79_A7     0x0abb10de
+#define ATA_NFORCE_MCP79_A8     0x0abc10de
+#define ATA_NFORCE_MCP79_A9     0x0abd10de
+#define ATA_NFORCE_MCP79_AA     0x0abe10de
+#define ATA_NFORCE_MCP79_AB     0x0abf10de
+#define ATA_NFORCE_MCP89_A0     0x0d8410de
+#define ATA_NFORCE_MCP89_A1     0x0d8510de
+#define ATA_NFORCE_MCP89_A2     0x0d8610de
+#define ATA_NFORCE_MCP89_A3     0x0d8710de
+#define ATA_NFORCE_MCP89_A4     0x0d8810de
+#define ATA_NFORCE_MCP89_A5     0x0d8910de
+#define ATA_NFORCE_MCP89_A6     0x0d8a10de
+#define ATA_NFORCE_MCP89_A7     0x0d8b10de
+#define ATA_NFORCE_MCP89_A8     0x0d8c10de
+#define ATA_NFORCE_MCP89_A9     0x0d8d10de
+#define ATA_NFORCE_MCP89_AA     0x0d8e10de
+#define ATA_NFORCE_MCP89_AB     0x0d8f10de
 
 #define ATA_PROMISE_ID         0x105a
 #define ATA_PDC20246           0x4d33105a
@@ -281,12 +426,24 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define ATA_PDC20377           0x3377105a
 #define ATA_PDC20378           0x3373105a
 #define ATA_PDC20379           0x3372105a
+#define ATA_PDC20571            0x3571105a
+#define ATA_PDC20575            0x3d75105a
+#define ATA_PDC20579            0x3574105a
+#define ATA_PDC20771            0x3570105a
+#define ATA_PDC40518            0x3d18105a
+#define ATA_PDC40519            0x3519105a
+#define ATA_PDC40718            0x3d17105a
+#define ATA_PDC40719            0x3515105a
+#define ATA_PDC40775            0x3d73105a
+#define ATA_PDC40779            0x3577105a
 #define ATA_PDC20617           0x6617105a
 #define ATA_PDC20618           0x6626105a
 #define ATA_PDC20619           0x6629105a
 #define ATA_PDC20620           0x6620105a
 #define ATA_PDC20621           0x6621105a
 #define ATA_PDC20622           0x6622105a
+#define ATA_PDC20624            0x6624105a
+#define ATA_PDC81518            0x8002105a
 
 #define ATA_SERVERWORKS_ID     0x1166
 #define ATA_ROSB4_ISA          0x02001166
@@ -306,6 +463,10 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define ATA_SII3512            0x35121095
 #define ATA_SII3112            0x31121095
 #define ATA_SII3112_1          0x02401095
+#define ATA_SII3124            0x31241095
+#define ATA_SII3132            0x31321095
+#define ATA_SII3132_1          0x02421095
+#define ATA_SII3132_2          0x02441095
 #define ATA_SII0680            0x06801095
 #define ATA_CMD646             0x06461095
 #define ATA_CMD648             0x06481095
@@ -355,7 +516,11 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define ATA_SIS962             0x09621039
 #define ATA_SIS963             0x09631039
 #define ATA_SIS964             0x09641039
+#define ATA_SIS965              0x09651039
 #define ATA_SIS964_1           0x01801039
+#define ATA_SIS180              0x01801039
+#define ATA_SIS181              0x01811039
+#define ATA_SIS182              0x01821039
 
 #define ATA_VIA_ID             0x1106
 #define ATA_VIA82C571          0x05711106
@@ -370,6 +535,8 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define ATA_VIA8237            0x32271106
 #define ATA_VIA8237A            0x05911106
 #define ATA_VIA8237S           0x53371106
+#define ATA_VIA8237_5372       0x53721106
+#define ATA_VIA8237_7372       0x73721106
 #define ATA_VIA8251             0x33491106
 #define ATA_VIA8361            0x31121106
 #define ATA_VIA8363            0x03051106
@@ -379,9 +546,17 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define ATA_VIA6420            0x31491106
 #define ATA_VIA6421             0x32491106
 
+#define ATA_VIACX700IDE         0x05811106
+#define ATA_VIACX700            0x83241106
+#define ATA_VIASATAIDE          0x53241106
+#define ATA_VIAVX800            0x83531106
+#define ATA_VIAVX855            0x84091106
+
 #define ATA_ITE_ID             0x1283
 #define ATA_IT8172G            0x81721283
-#define ATA_IT8212F            0x82121283
+#define ATA_IT8211F             0x82111283
+#define ATA_IT8212F             0x82121283
+#define ATA_IT8213F             0x82131283
 
 #define ATA_OPTI_ID             0x1045
 #define ATA_OPTI82C621          0xc6211045
@@ -455,7 +630,14 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define SIS_BASE        0x0100
 #define SIS_SOUTH       0x0200
 
+#define INTEL_STD       0
+#define INTEL_IDX       1
+
 #define ICH4_FIX        0x0100
+#define ICH5            0x0200
+#define I6CH            0x0400
+#define I6CH2           0x0800
+#define I1CH            0x1000
 
 #define NV4OFF          0x0100
 #define NVQ             0x0200
@@ -473,9 +655,11 @@ typedef struct _BUSMASTER_CONTROLLER_INFORMATION {
 #define VIASOUTH       0x2000
 #define VIAAST         0x4000
 #define VIAPRQ         0x8000
+#define VIASATA         0x10000
 
 #define ITE_33          0
 #define ITE_133         1
+#define ITE_133_NEW     2
 
 #ifdef USER_MODE
   #define PCI_DEV_HW_SPEC_BM(idhi, idlo, rev, mode, name, flags) \
@@ -499,6 +683,7 @@ BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
     PCI_DEV_HW_SPEC_BM( 5288, 10b9, 0x00, ATA_SA300, "ALI M5288"        , UNIATA_SATA | UNIATA_NO_SLAVE           ),
     PCI_DEV_HW_SPEC_BM( 5287, 10b9, 0x00, ATA_SA150, "ALI M5287"        , UNIATA_SATA | UNIATA_NO_SLAVE           ),
     PCI_DEV_HW_SPEC_BM( 5281, 10b9, 0x00, ATA_SA150, "ALI M5281"        , UNIATA_SATA | UNIATA_NO_SLAVE           ),
+    PCI_DEV_HW_SPEC_BM( 5228, 10b9, 0xc5, ATA_UDMA6, "ALI M5228 UDMA6"  , ALINEW                                  ),
     PCI_DEV_HW_SPEC_BM( 5229, 10b9, 0xc5, ATA_UDMA6, "ALI M5229 UDMA6"  , ALINEW                                  ),
     PCI_DEV_HW_SPEC_BM( 5229, 10b9, 0xc4, ATA_UDMA5, "ALI M5229 UDMA5"  , ALINEW                                  ),
     PCI_DEV_HW_SPEC_BM( 5229, 10b9, 0xc2, ATA_UDMA4, "ALI M5229 UDMA4"  , ALINEW                                  ),
@@ -521,8 +706,7 @@ BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
     PCI_DEV_HW_SPEC_BM( 438c, 1002, 0x00, ATA_UDMA6, "ATI IXP600"       , 0                                       ),
     PCI_DEV_HW_SPEC_BM( 4380, 1002, 0x00, ATA_SA150, "ATI IXP600"       , UNIATA_SATA | UNIATA_AHCI               ),
     PCI_DEV_HW_SPEC_BM( 439c, 1002, 0x00, ATA_UDMA6, "ATI IXP700"       , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 4390, 1002, 0x00, ATA_UDMA6, "ATI IXP700"       , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 4391, 1002, 0x00, ATA_SA150, "ATI IXP700"       , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 4390, 1002, 0x00, ATA_SA150, "ATI IXP700"       , UNIATA_SATA | UNIATA_AHCI               ),
 
     PCI_DEV_HW_SPEC_BM( 0004, 1103, 0x05, ATA_UDMA6, "HighPoint HPT372" , HPT372 | 0x00   | UNIATA_RAID_CONTROLLER),
     PCI_DEV_HW_SPEC_BM( 0004, 1103, 0x03, ATA_UDMA5, "HighPoint HPT370" , HPT370 | 0x00   | UNIATA_RAID_CONTROLLER),
@@ -540,78 +724,111 @@ BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
     PCI_DEV_HW_SPEC_BM( 7199, 8086, 0x00, ATA_UDMA2, "Intel PIIX4"      , 0                                       ),
     PCI_DEV_HW_SPEC_BM( 84ca, 8086, 0x00, ATA_UDMA2, "Intel PIIX4"      , 0                                       ),
     PCI_DEV_HW_SPEC_BM( 7601, 8086, 0x00, ATA_UDMA2, "Intel ICH0"       , 0                                       ),
+
     PCI_DEV_HW_SPEC_BM( 2421, 8086, 0x00, ATA_UDMA4, "Intel ICH"        , 0                                       ),
     PCI_DEV_HW_SPEC_BM( 2411, 8086, 0x00, ATA_UDMA4, "Intel ICH"        , 0                                       ),
+
     PCI_DEV_HW_SPEC_BM( 244a, 8086, 0x00, ATA_UDMA5, "Intel ICH2"       , 0                                       ),
     PCI_DEV_HW_SPEC_BM( 244b, 8086, 0x00, ATA_UDMA5, "Intel ICH2"       , 0                                       ),
+
     PCI_DEV_HW_SPEC_BM( 248a, 8086, 0x00, ATA_UDMA5, "Intel ICH3"       , 0                                       ),
     PCI_DEV_HW_SPEC_BM( 248b, 8086, 0x00, ATA_UDMA5, "Intel ICH3"       , 0                                       ),
+
     PCI_DEV_HW_SPEC_BM( 24cb, 8086, 0x00, ATA_UDMA5, "Intel ICH4"       , ICH4_FIX | UNIATA_NO_DPC                ),
     PCI_DEV_HW_SPEC_BM( 24ca, 8086, 0x00, ATA_UDMA5, "Intel ICH4"       , ICH4_FIX | UNIATA_NO_DPC                ),
+
     PCI_DEV_HW_SPEC_BM( 24db, 8086, 0x00, ATA_UDMA5, "Intel ICH5 EB"    , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 24d1, 8086, 0x00, ATA_SA150, "Intel ICH5 EB1"   , UNIATA_SATA                             ),
-    PCI_DEV_HW_SPEC_BM( 24df, 8086, 0x00, ATA_SA150, "Intel ICH5 EB2"   , UNIATA_SATA                             ),
+    PCI_DEV_HW_SPEC_BM( 24d1, 8086, 0x00, ATA_SA150, "Intel ICH5 EB1"   , ICH5 | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( 24df, 8086, 0x00, ATA_SA150, "Intel ICH5 EB2"   , ICH5 | UNIATA_SATA                      ),
+
     PCI_DEV_HW_SPEC_BM( 25a2, 8086, 0x00, ATA_UDMA5, "Intel 6300ESB"    , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 25a3, 8086, 0x00, ATA_SA150, "Intel 6300ESB1"   , UNIATA_SATA                             ),
-    PCI_DEV_HW_SPEC_BM( 25b0, 8086, 0x00, ATA_SA150, "Intel 6300ESB2"   , UNIATA_SATA                             ),
+    PCI_DEV_HW_SPEC_BM( 25a3, 8086, 0x00, ATA_SA150, "Intel 6300ESB1"   , ICH5 | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( 25b0, 8086, 0x00, ATA_SA150, "Intel 6300ESB2"   , ICH5 | UNIATA_SATA                      ),
+
     PCI_DEV_HW_SPEC_BM( 266f, 8086, 0x00, ATA_UDMA5, "Intel ICH6"       , 0                                       ),
     PCI_DEV_HW_SPEC_BM( 2651, 8086, 0x00, ATA_SA150, "Intel ICH6"       , UNIATA_SATA | UNIATA_AHCI               ),
     PCI_DEV_HW_SPEC_BM( 2652, 8086, 0x00, ATA_SA150, "Intel ICH6"       , UNIATA_SATA | UNIATA_AHCI               ),
     PCI_DEV_HW_SPEC_BM( 2653, 8086, 0x00, ATA_SA150, "Intel ICH6M"      , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 27c0, 8086, 0x00, ATA_SA300, "Intel ICH7"       , UNIATA_SATA | UNIATA_AHCI               ),
+
+    PCI_DEV_HW_SPEC_BM( 27df, 8086, 0x00, ATA_UDMA5, "Intel ICH7"       , I1CH                                    ),
+    PCI_DEV_HW_SPEC_BM( 27c0, 8086, 0x00, ATA_SA300, "Intel ICH7 S1"    , UNIATA_SATA                             ),
     PCI_DEV_HW_SPEC_BM( 27c1, 8086, 0x00, ATA_SA300, "Intel ICH7"       , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 27c3, 8086, 0x00, ATA_SA300, "Intel ICH7"       , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 27c4, 8086, 0x00, ATA_SA300, "Intel ICH7M"      , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 27c5, 8086, 0x00, ATA_SA300, "Intel ICH7M"      , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 27c6, 8086, 0x00, ATA_SA300, "Intel ICH7M"      , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 27df, 8086, 0x00, ATA_UDMA5, "Intel ICH7"       , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 269e, 8086, 0x00, ATA_UDMA5, "Intel 63XXESB2"   , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 2680, 8086, 0x00, ATA_SA300, "Intel 63XXESB2"   , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 27c3, 8086, 0x00, ATA_SA300, "Intel ICH7"       , UNIATA_SATA                             ),
+    PCI_DEV_HW_SPEC_BM( 27c4, 8086, 0x00, ATA_SA150, "Intel ICH7M R1"   , UNIATA_SATA                             ),
+    PCI_DEV_HW_SPEC_BM( 27c5, 8086, 0x00, ATA_SA150, "Intel ICH7M"      , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 27c6, 8086, 0x00, ATA_SA150, "Intel ICH7M"      , UNIATA_SATA                             ),
+
+    PCI_DEV_HW_SPEC_BM( 269e, 8086, 0x00, ATA_UDMA5, "Intel 63XXESB2"   , I1CH                                    ),
+    PCI_DEV_HW_SPEC_BM( 2680, 8086, 0x00, ATA_SA300, "Intel 63XXESB2"   , UNIATA_SATA                             ),
     PCI_DEV_HW_SPEC_BM( 2681, 8086, 0x00, ATA_SA300, "Intel 63XXESB2"   , UNIATA_SATA | UNIATA_AHCI               ),
     PCI_DEV_HW_SPEC_BM( 2682, 8086, 0x00, ATA_SA300, "Intel 63XXESB2"   , UNIATA_SATA | UNIATA_AHCI               ),
     PCI_DEV_HW_SPEC_BM( 2683, 8086, 0x00, ATA_SA300, "Intel 63XXESB2"   , UNIATA_SATA | UNIATA_AHCI               ),
 
-    PCI_DEV_HW_SPEC_BM( 2820, 8086, 0x00, ATA_UDMA5, "Intel ICH8"       , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 2820, 8086, 0x00, ATA_SA300, "Intel ICH8"       , I6CH                                    ),
     PCI_DEV_HW_SPEC_BM( 2821, 8086, 0x00, ATA_SA300, "Intel ICH8"       , UNIATA_SATA | UNIATA_AHCI               ),
     PCI_DEV_HW_SPEC_BM( 2822, 8086, 0x00, ATA_SA300, "Intel ICH8"       , UNIATA_SATA | UNIATA_AHCI               ),
     PCI_DEV_HW_SPEC_BM( 2824, 8086, 0x00, ATA_SA300, "Intel ICH8"       , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 2825, 8086, 0x00, ATA_UDMA5, "Intel ICH8"       , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 2828, 8086, 0x00, ATA_UDMA5, "Intel ICH8M"      , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 2825, 8086, 0x00, ATA_SA300, "Intel ICH8"       , I6CH2 | UNIATA_SATA                     ),
+    PCI_DEV_HW_SPEC_BM( 2828, 8086, 0x00, ATA_SA300, "Intel ICH8M"      , I6CH | UNIATA_SATA                      ),
     PCI_DEV_HW_SPEC_BM( 2829, 8086, 0x00, ATA_SA300, "Intel ICH8M"      , UNIATA_SATA | UNIATA_AHCI               ),
     PCI_DEV_HW_SPEC_BM( 282a, 8086, 0x00, ATA_SA300, "Intel ICH8M"      , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 2850, 8086, 0x00, ATA_UDMA5, "Intel ICH8M"      , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 2850, 8086, 0x00, ATA_UDMA5, "Intel ICH8M"      , I1CH                                    ),
 
-    PCI_DEV_HW_SPEC_BM( 2920, 8086, 0x00, ATA_UDMA5, "Intel ICH9R/DO/DH", 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 2921, 8086, 0x00, ATA_UDMA5, "Intel ICH9"       , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 2920, 8086, 0x00, ATA_SA300, "Intel ICH9"       , I6CH | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( 2926, 8086, 0x00, ATA_SA300, "Intel ICH9"       , I6CH2 | UNIATA_SATA                     ),
+    PCI_DEV_HW_SPEC_BM( 2921, 8086, 0x00, ATA_SA300, "Intel ICH9"       , UNIATA_SATA | UNIATA_AHCI               ),
     PCI_DEV_HW_SPEC_BM( 2922, 8086, 0x00, ATA_SA300, "Intel ICH9"       , UNIATA_SATA | UNIATA_AHCI               ),
     PCI_DEV_HW_SPEC_BM( 2923, 8086, 0x00, ATA_SA300, "Intel ICH9"       , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 2926, 8086, 0x00, ATA_SA300, "Intel ICH9"       , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 2928, 8086, 0x00, ATA_UDMA5, "Intel ICH9M/M-E"  , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 2929, 8086, 0x00, ATA_SA300, "Intel ICH9M/M-E"  , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 292d, 8086, 0x00, ATA_UDMA5, "Intel ICH9M/M-E"  , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 292e, 8086, 0x00, ATA_UDMA5, "Intel ICH9M/M-E"  , 0                                       ),
-
-    PCI_DEV_HW_SPEC_BM( 3a00, 8086, 0x00, ATA_UDMA5, "Intel ICH10"      , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 3a02, 8086, 0x00, ATA_SA300, "Intel ICH10"      , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 3a03, 8086, 0x00, ATA_SA300, "Intel ICH10"      , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 3a06, 8086, 0x00, ATA_UDMA5, "Intel ICH10"      , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 3a20, 8086, 0x00, ATA_UDMA5, "Intel ICH10"      , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 3a22, 8086, 0x00, ATA_SA300, "Intel ICH10"      , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 3a23, 8086, 0x00, ATA_SA300, "Intel ICH10"      , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 3a26, 8086, 0x00, ATA_UDMA5, "Intel ICH10"      , 0                                       ),
-
-    PCI_DEV_HW_SPEC_BM( 3b20, 8086, 0x00, ATA_UDMA5, "Intel PCH"        , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 3b21, 8086, 0x00, ATA_UDMA5, "Intel PCH"        , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 3b22, 8086, 0x00, ATA_SA300, "Intel PCH"        , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 3b23, 8086, 0x00, ATA_SA300, "Intel PCH"        , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 3b26, 8086, 0x00, ATA_UDMA5, "Intel PCH"        , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 3b28, 8086, 0x00, ATA_UDMA5, "Intel PCH"        , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 3b29, 8086, 0x00, ATA_SA300, "Intel PCH"        , UNIATA_SATA | UNIATA_AHCI               ),
-    PCI_DEV_HW_SPEC_BM( 3b2D, 8086, 0x00, ATA_UDMA5, "Intel PCH"        , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 3b2E, 8086, 0x00, ATA_UDMA5, "Intel PCH"        , 0                                       ),
-    PCI_DEV_HW_SPEC_BM( 3b2F, 8086, 0x00, ATA_SA300, "Intel PCH"        , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 2925, 8086, 0x00, ATA_SA300, "Intel ICH9"       , UNIATA_SATA | UNIATA_AHCI               ),
+
+    PCI_DEV_HW_SPEC_BM( 3a20, 8086, 0x00, ATA_SA300, "Intel ICH10"       , I6CH | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( 3a26, 8086, 0x00, ATA_SA300, "Intel ICH10"       , I6CH2 | UNIATA_SATA                     ),
+    PCI_DEV_HW_SPEC_BM( 3a22, 8086, 0x00, ATA_SA300, "Intel ICH10"       , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 3a25, 8086, 0x00, ATA_SA300, "Intel ICH10"       , UNIATA_SATA | UNIATA_AHCI               ),
+
+    PCI_DEV_HW_SPEC_BM( 3a00, 8086, 0x00, ATA_SA300, "Intel ICH10"       , I6CH | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( 3a06, 8086, 0x00, ATA_SA300, "Intel ICH10"       , I6CH2 | UNIATA_SATA                     ),
+    PCI_DEV_HW_SPEC_BM( 3a02, 8086, 0x00, ATA_SA300, "Intel ICH10"       , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 3a05, 8086, 0x00, ATA_SA300, "Intel ICH10"       , UNIATA_SATA | UNIATA_AHCI               ),
+/*
+    PCI_DEV_HW_SPEC_BM( ????, 8086, 0x00, ATA_SA300, "Intel ICH10"       , I6CH | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( ????, 8086, 0x00, ATA_SA300, "Intel ICH10"       , I6CH2 | UNIATA_SATA                     ),
+    PCI_DEV_HW_SPEC_BM( ????, 8086, 0x00, ATA_SA300, "Intel ICH10"       , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( ????, 8086, 0x00, ATA_SA300, "Intel ICH10"       , UNIATA_SATA | UNIATA_AHCI               ),
+*/
+    PCI_DEV_HW_SPEC_BM( 3b20, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , I6CH | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( 3b21, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , I6CH2 | UNIATA_SATA                     ),
+    PCI_DEV_HW_SPEC_BM( 3b22, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 3b23, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 3b25, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 3b26, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , I6CH2 | UNIATA_SATA                     ),
+    PCI_DEV_HW_SPEC_BM( 3b28, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , I6CH | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( 3b29, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 3b2c, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 3b2d, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , I6CH2 | UNIATA_SATA                     ),
+    PCI_DEV_HW_SPEC_BM( 3b2e, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , I6CH | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( 3b2f, 8086, 0x00, ATA_SA300, "Intel 5 Series/3400" , UNIATA_SATA | UNIATA_AHCI               ),
+
+    PCI_DEV_HW_SPEC_BM( 1c00, 8086, 0x00, ATA_SA300, "Intel Cougar Point"  , I6CH | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( 1c01, 8086, 0x00, ATA_SA300, "Intel Cougar Point"  , I6CH | UNIATA_SATA                      ),
+    PCI_DEV_HW_SPEC_BM( 1c02, 8086, 0x00, ATA_SA300, "Intel Cougar Point"  , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 1c03, 8086, 0x00, ATA_SA300, "Intel Cougar Point"  , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 1c04, 8086, 0x00, ATA_SA300, "Intel Cougar Point"  , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 1c05, 8086, 0x00, ATA_SA300, "Intel Cougar Point"  , UNIATA_SATA | UNIATA_AHCI               ),
+    PCI_DEV_HW_SPEC_BM( 1c08, 8086, 0x00, ATA_SA300, "Intel Cougar Point"  , I6CH2 | UNIATA_SATA                     ),
+    PCI_DEV_HW_SPEC_BM( 1c09, 8086, 0x00, ATA_SA300, "Intel Cougar Point"  , I6CH2 | UNIATA_SATA                     ),
 
 //    PCI_DEV_HW_SPEC_BM( 3200, 8086, 0x00, ATA_SA150, "Intel 31244"      , UNIATA_SATA                             ),
+    PCI_DEV_HW_SPEC_BM( 3200, 8086, 0x00, ATA_UDMA5, "Intel SCH"           , I1CH                                    ),
+
+/*
+    PCI_DEV_HW_SPEC_BM( 2360, 197b, 0x00, ATA_SA300, "JMB360"           , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 2361, 197b, 0x00, ATA_SA300, "JMB361"           , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 2363, 197b, 0x00, ATA_SA300, "JMB363"           , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 2365, 197b, 0x00, ATA_SA300, "JMB365"           , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 2366, 197b, 0x00, ATA_SA300, "JMB366"           , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 2368, 197b, 0x00, ATA_UDMA6, "JMB368"           , 0                                       ),
+*/
 /*    
     PCI_DEV_HW_SPEC_BM( 5040, 11ab, 0x00, ATA_SA150, "Marvell 88SX5040" , UNIATA_SATA                             ),
     PCI_DEV_HW_SPEC_BM( 5041, 11ab, 0x00, ATA_SA150, "Marvell 88SX5041" , UNIATA_SATA                             ),
@@ -620,6 +837,7 @@ BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
     PCI_DEV_HW_SPEC_BM( 6041, 11ab, 0x00, ATA_SA300, "Marvell 88SX6041" , UNIATA_SATA                             ),
     PCI_DEV_HW_SPEC_BM( 6081, 11ab, 0x00, ATA_SA300, "Marvell 88SX6081" , UNIATA_SATA                             ),*/
     PCI_DEV_HW_SPEC_BM( 6101, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6101" , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 6121, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6121" , 0                                       ),
     PCI_DEV_HW_SPEC_BM( 6145, 11ab, 0x00, ATA_UDMA6, "Marvell 88SX6145" , 0                                       ),
 
     PCI_DEV_HW_SPEC_BM( 01bc, 10de, 0x00, ATA_UDMA5, "nVidia nForce"    , AMDNVIDIA                               ),
@@ -760,11 +978,16 @@ BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
     PCI_DEV_HW_SPEC_BM( 3177, 1106, 0x00, ATA_UDMA6, "VIA 8235"         , VIA133 | VIAAST                         ),
 */
     PCI_DEV_HW_SPEC_BM( 0571, 1106, 0x00, ATA_UDMA2, "VIA ATA-xxx"      , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 0581, 1106, 0x00, ATA_UDMA6, "VIA UATA-xxx"     , 0                                       ),
+    /* has no SATA registers, all mapped to PATA-style regs */
+    PCI_DEV_HW_SPEC_BM( 5324, 1106, 0x00, ATA_SA150, "VIA SATA-xxx"     , 0                                       ),
     PCI_DEV_HW_SPEC_BM( 3164, 1106, 0x00, ATA_UDMA6, "VIA 6410"         , 0                                       ),
     PCI_DEV_HW_SPEC_BM( 3149, 1106, 0x00, ATA_SA150, "VIA 6420"         , 0      | UNIATA_SATA                    ),
     PCI_DEV_HW_SPEC_BM( 3249, 1106, 0x00, ATA_SA150, "VIA 6421"         , VIABAR | UNIATA_SATA                    ),
     PCI_DEV_HW_SPEC_BM( 0591, 1106, 0x00, ATA_SA150, "VIA 8237A"        , 0      | UNIATA_SATA                    ),
     PCI_DEV_HW_SPEC_BM( 5337, 1106, 0x00, ATA_SA150, "VIA 8237S"        , 0      | UNIATA_SATA                    ),
+    PCI_DEV_HW_SPEC_BM( 5372, 1106, 0x00, ATA_SA300, "VIA 8237"         , 0      | UNIATA_SATA                    ),
+    PCI_DEV_HW_SPEC_BM( 7372, 1106, 0x00, ATA_SA300, "VIA 8237"         , 0      | UNIATA_SATA                    ),
     //PCI_DEV_HW_SPEC_BM( 3349, 1106, 0x00, ATA_SA150, "VIA 8251"         , VIAAHCI| UNIATA_SATA                    ),
 
     PCI_DEV_HW_SPEC_BM( c693, 1080, 0x00, ATA_WDMA2, "Cypress 82C693"   ,0                                        ),
@@ -797,7 +1020,9 @@ BUSMASTER_CONTROLLER_INFORMATION const BusMasterAdapters[] = {
     PCI_DEV_HW_SPEC_BM( 0102, 1042, 0x00, ATA_PIO4,  "RZ 100x"          , 0                                       ),
 
     PCI_DEV_HW_SPEC_BM( 8172, 1283, 0x00, ATA_UDMA2, "IT8172"           , 0                                       ),
+    PCI_DEV_HW_SPEC_BM( 8213, 1283, 0x00, ATA_UDMA6, "IT8213F"          , ITE_133_NEW                             ),
     PCI_DEV_HW_SPEC_BM( 8212, 1283, 0x00, ATA_UDMA6, "IT8212F"          , ITE_133                                 ),
+    PCI_DEV_HW_SPEC_BM( 8211, 1283, 0x00, ATA_UDMA6, "IT8211F"          , ITE_133                                 ),
 
     PCI_DEV_HW_SPEC_BM( 0044, 169c, 0x00, ATA_UDMA2, "Netcell SR3000/5000", 0                                     ),
 
index c0bcc22..365f076 100644 (file)
@@ -1,6 +1,6 @@
 /*++
 
-Copyright (c) 2002-2008 Alexandr A. Telyatnikov (Alter)
+Copyright (c) 2002-2010 Alexandr A. Telyatnikov (Alter)
 
 Module Name:
     bsmaster.h
@@ -188,6 +188,7 @@ typedef struct _IDE_AHCI_REGISTERS {
         ULONG AE:1;    // AHCI enable
     } GHC;
 
+#define AHCI_GHC   0x04
 #define AHCI_GHC_HR    0x00000001
 #define AHCI_GHC_IE    0x00000002
 #define AHCI_GHC_AE    0x80000000
@@ -347,7 +348,14 @@ typedef struct _IDE_SATA_REGISTERS {
 #define IDX_SATA_SActive                (3+IDX_SATA_IO)
 #define IDX_SATA_SNTF_PMN               (4+IDX_SATA_IO)
 
-#define IDX_MAX_REG                     (IDX_SATA_IO+IDX_SATA_IO_SZ)
+#define IDX_INDEXED_IO                  (IDX_SATA_IO+IDX_SATA_IO_SZ)
+#define IDX_INDEXED_IO_SZ               2
+
+#define IDX_INDEXED_ADDR                (0+IDX_INDEXED_IO)
+#define IDX_INDEXED_DATA                (1+IDX_INDEXED_IO)
+
+#define IDX_MAX_REG                     (IDX_INDEXED_IO+IDX_INDEXED_IO_SZ)
+
 
 typedef union _AHCI_IS_REG {
     struct {
@@ -712,9 +720,10 @@ struct _HW_DEVICE_EXTENSION;
 struct _HW_LU_EXTENSION;
 
 typedef struct _IORES {
-    ULONG Addr;
-    ULONG MemIo:1;
-    ULONG Reserved:31;
+    ULONG Addr;          /* Base address*/
+    ULONG MemIo:1;       /* Memory mapping (1) vs IO ports (0) */
+    ULONG Proc:1;        /* Need special process via IO_Proc */
+    ULONG Reserved:30;
 } IORES, *PIORES;
 
 // Channel extension
@@ -825,6 +834,9 @@ typedef struct _HW_CHANNEL {
 #define CTRFLAGS_LBA48                  0x0040
 #define CTRFLAGS_DSC_BSY                0x0080
 #define CTRFLAGS_NO_SLAVE               0x0100
+//#define CTRFLAGS_PATA                   0x0200
+
+#define CTRFLAGS_PERMANENT  (CTRFLAGS_DMA_RO | CTRFLAGS_NO_SLAVE)
 
 #define GEOM_AUTO                       0xffffffff
 #define GEOM_STD                        0x0000
@@ -883,6 +895,13 @@ typedef struct _HW_LU_EXTENSION {
     struct _SBadBlockRange* arrBadBlocks;
     ULONG           nBadBlocks;
 
+    // Controller-specific LUN options
+    union {
+        /* for tricky controllers, those can change Logical-to-Physical LUN mapping.
+           mainly for mapping SATA ports to compatible PATA registers */
+        ULONG          SATA_lun_map; 
+    };
+
     struct _HW_DEVICE_EXTENSION* DeviceExtension;
 
 #ifdef IO_STATISTICS
@@ -989,6 +1008,11 @@ typedef struct _HW_DEVICE_EXTENSION {
 
     PCCH           FullDevName;
 
+    // Controller specific state/options
+    union {
+        ULONG      HwCfg;
+    };
+
 } HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
 
 typedef struct _ISR2_DEVICE_EXTENSION {
@@ -1210,7 +1234,7 @@ UniataChipDetectChannels(
     IN PPORT_CONFIGURATION_INFORMATION ConfigInfo
     );
 
-extern BOOLEAN
+extern NTSTATUS
 NTAPI
 UniataChipDetect(
     IN PVOID HwDeviceExtension,
index c0b9f4f..17768e4 100644 (file)
 /*  Compiler dependencies                          */
 /***************************************************/
 
-#define DDKFASTAPI      __fastcall
+/* ReactOS-specific defines */
+#ifdef DDKAPI
+ #define USE_REACTOS_DDK
+#endif //DDKAPI
 
 /* Are we under GNU C (mingw) ??? */
-#ifdef __GNUC__
+#if __GNUC__ >=3
 
  #define  DEF_U64(x)     (x##ULL)
  #define  DEF_I64(x)     (x##LL)
 
+ /* ReactOS-specific defines */
+ #ifdef USE_REACTOS_DDK
+  #define DDKFASTAPI __attribute__((fastcall))
+ #else //USE_REACTOS_DDK
+
+  #define DDKAPI          __attribute__((stdcall))
+  #define DDKFASTAPI      __attribute__((fastcall))
+  #define DDKCDECLAPI     __attribute__((cdecl))
+
+ #endif  //DDKAPI
+
+ #define DECLSPEC_NAKED   __attribute__((naked))
+
 #else // !__GNUC__ => MSVC/Intel
 
  #define  DEF_U64(x)     (x##UI64)
  #define  DEF_I64(x)     (x##I64)
 
+ /* ReactOS-specific defines */
+ #ifdef USE_REACTOS_DDK
+ #else //USE_REACTOS_DDK
+
+  #define DDKAPI          __stdcall
+  #define DDKFASTAPI      __fastcall
+  #define DDKCDECLAPI     _cdecl
+
+ #endif  //DDKAPI
+
+ #define DECLSPEC_NAKED   __declspec(naked)
+
 #endif //__GNUC__
 
 
index 1d141b5..70aaed3 100644 (file)
@@ -1,6 +1,6 @@
 /*++
 
-Copyright (c) 2002-2008 Alexandr A. Telyatnikov (Alter)
+Copyright (c) 2002-2010 Alexandr A. Telyatnikov (Alter)
 
 Module Name:
     id_ata.cpp
@@ -88,6 +88,7 @@ BOOLEAN InDriverEntry = TRUE;
 BOOLEAN g_opt_Verbose = 0;
 
 BOOLEAN WinVer_WDM_Model = FALSE;
+
 //UCHAR EnableDma = FALSE;
 //UCHAR EnableReorder = FALSE;
 
@@ -234,7 +235,6 @@ UniataNanoSleep(
     } while(t);
 } // end UniataNanoSleep()
 
-
 #define AtapiWritePortN_template(_type, _Type, sz) \
 VOID \
 DDKFASTAPI \
@@ -254,6 +254,8 @@ AtapiWritePort##sz( \
         KdPrint(("invalid io write request @ ch %x, res* %x\n", chan, _port)); \
         return; \
     } \
+    if(res->Proc) {             \
+    } else  \
     if(!res->MemIo) {             \
         ScsiPortWritePort##_Type((_type*)(res->Addr), data); \
     } else {                                      \
@@ -287,6 +289,8 @@ AtapiWritePortEx##sz( \
         KdPrint(("invalid io write request @ ch %x, res* %x, offs %x\n", chan, _port, offs)); \
         return; \
     } \
+    if(res->Proc) {             \
+    } else  \
     if(!res->MemIo) {             \
         ScsiPortWritePort##_Type((_type*)(res->Addr+offs), data); \
     } else {                                      \
@@ -318,6 +322,9 @@ AtapiReadPort##sz( \
         KdPrint(("invalid io read request @ ch %x, res* %x\n", chan, _port)); \
         return (_type)(-1); \
     } \
+    if(res->Proc) {             \
+        return 0; \
+    } else  \
     if(!res->MemIo) {             \
         /*KdPrint(("r_io @ (%x) %x\n", _port, res->Addr));*/ \
         return ScsiPortReadPort##_Type((_type*)(res->Addr)); \
@@ -350,6 +357,9 @@ AtapiReadPortEx##sz( \
         KdPrint(("invalid io read request @ ch %x, res* %x, offs %x\n", chan, _port, offs)); \
         return (_type)(-1); \
     } \
+    if(res->Proc) {             \
+        return 0; \
+    } else  \
     if(!res->MemIo) {             \
         return ScsiPortReadPort##_Type((_type*)(res->Addr+offs)); \
     } else {                                      \
@@ -719,7 +729,10 @@ AtapiSoftReset(
         GetBaseStatus(chan, statusByte2);
     }
     if(chan->DeviceExtension->HwFlags & UNIATA_SATA) {
-        UniataSataClearErr(chan->DeviceExtension, chan->lChannel, UNIATA_SATA_IGNORE_CONNECT);
+        UniataSataClearErr(chan->DeviceExtension, chan->lChannel, UNIATA_SATA_IGNORE_CONNECT, DeviceNumber);
+/*        if(!(chan->ChannelCtrlFlags & CTRFLAGS_NO_SLAVE)) {
+            UniataSataClearErr(chan->DeviceExtension, chan->lChannel, UNIATA_SATA_IGNORE_CONNECT, 1);
+        }*/
     }
     return;
 
@@ -1319,14 +1332,16 @@ IssueIdentify(
             KdPrint2((PRINT_PREFIX "IssueIdentify: IDE_STATUS_DRQ (%#x)\n", statusByte));
             GetBaseStatus(chan, statusByte);
             // One last check for Atapi.
-            signatureLow = AtapiReadPort1(chan, IDX_IO1_i_CylinderLow);
-            signatureHigh = AtapiReadPort1(chan, IDX_IO1_i_CylinderHigh);
+            if (Command == IDE_COMMAND_IDENTIFY) {
+                signatureLow = AtapiReadPort1(chan, IDX_IO1_i_CylinderLow);
+                signatureHigh = AtapiReadPort1(chan, IDX_IO1_i_CylinderHigh);
 
-            if (signatureLow == ATAPI_MAGIC_LSB &&
-                signatureHigh == ATAPI_MAGIC_MSB) {
-                KdPrint2((PRINT_PREFIX "IssueIdentify: this is ATAPI (3) (ldev %d)\n", ldev));
-                // Device is Atapi.
-                return FALSE;
+                if (signatureLow == ATAPI_MAGIC_LSB &&
+                    signatureHigh == ATAPI_MAGIC_MSB) {
+                    KdPrint2((PRINT_PREFIX "IssueIdentify: this is ATAPI (3) (ldev %d)\n", ldev));
+                    // Device is Atapi.
+                    return FALSE;
+                }
             }
             break;
         } else {
@@ -1342,6 +1357,11 @@ IssueIdentify(
                     KdPrint2((PRINT_PREFIX "IssueIdentify: this is ATAPI (4) (ldev %d)\n", ldev));
                     return FALSE;
                 }
+            } else {
+                if(!(statusByte & IDE_STATUS_ERROR) && (statusByte & IDE_STATUS_BUSY)) {
+                    KdPrint2((PRINT_PREFIX "IssueIdentify: DRQ not asserted immediately, BUSY -> WaitForDrq\n"));
+                    break;
+                }
             }
             // Device didn't respond correctly. It will be given one more chances.
             KdPrint2((PRINT_PREFIX "IssueIdentify: DRQ never asserted (%#x). Error reg (%#x)\n",
@@ -1388,20 +1408,20 @@ IssueIdentify(
         // ATI/SII chipsets with memory-mapped IO hangs when
         // I call ReadBuffer(), probably due to PCI burst/prefetch enabled
         // Unfortunately, I don't know yet how to workaround it except the way you see below.
-        KdPrint2((PRINT_PREFIX
+        KdPrint2((PRINT_PREFIX 
                    "  IO_%#x (%#x), %s:\n",
                    IDX_IO1_i_Data,
                    chan->RegTranslation[IDX_IO1_i_Data].Addr,
                    chan->RegTranslation[IDX_IO1_i_Data].MemIo ? "Mem" : "IO"));
         for(i=0; i<256; i++) {
 /*
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "  IO_%#x (%#x):\n",
                        IDX_IO1_i_Data,
                        chan->RegTranslation[IDX_IO1_i_Data].Addr));
 */
             w = AtapiReadPort2(chan, IDX_IO1_i_Data);
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "    %x\n", w));
             AtapiStallExecution(1);
             ((PUSHORT)&deviceExtension->FullIdentifyData)[i] = w;
@@ -1464,7 +1484,7 @@ IssueIdentify(
         ULONGLONG cylinders=0;
         ULONGLONG tmp_cylinders=0;
         // Read very-old-style drive geometry
-        KdPrint2((PRINT_PREFIX "CHS %#x:%#x:%#x\n",
+        KdPrint2((PRINT_PREFIX "CHS %#x:%#x:%#x\n", 
                 deviceExtension->FullIdentifyData.NumberOfCylinders,
                 deviceExtension->FullIdentifyData.NumberOfHeads,
                 deviceExtension->FullIdentifyData.SectorsPerTrack
@@ -1478,7 +1498,7 @@ IssueIdentify(
 /*            (deviceExtension->FullIdentifyData.TranslationFieldsValid) &&*/
             (NumOfSectors < deviceExtension->FullIdentifyData.UserAddressableSectors)) {
             KdPrint2((PRINT_PREFIX "NumberOfCylinders == 0x3fff\n"));
-            cylinders =
+            cylinders = 
                 (deviceExtension->FullIdentifyData.UserAddressableSectors /
                     (deviceExtension->FullIdentifyData.NumberOfHeads *
                        deviceExtension->FullIdentifyData.SectorsPerTrack));
@@ -1516,13 +1536,13 @@ IssueIdentify(
                (deviceExtension->FullIdentifyData.UserAddressableSectors48 > NumOfSectors)
                ) {
                 KdPrint2((PRINT_PREFIX "LBA48\n"));
-                cylinders =
+                cylinders = 
                     (deviceExtension->FullIdentifyData.UserAddressableSectors48 /
                         (deviceExtension->FullIdentifyData.NumberOfHeads *
                            deviceExtension->FullIdentifyData.SectorsPerTrack));
 
                 KdPrint2((PRINT_PREFIX "cylinders %#I64x\n", cylinders));
-
+                
                 NativeNumOfSectors = cylinders *
                                deviceExtension->FullIdentifyData.NumberOfHeads *
                                deviceExtension->FullIdentifyData.SectorsPerTrack;
@@ -1554,7 +1574,7 @@ IssueIdentify(
                     KdPrint2((PRINT_PREFIX "Read high order bytes\n"));
                     NativeNumOfSectors |=
                                         ((ULONG)AtapiReadPort1(chan, IDX_IO1_i_BlockNumber)  << 24 );
-                    hNativeNumOfSectors=
+                    hNativeNumOfSectors= 
                                          (ULONG)AtapiReadPort1(chan, IDX_IO1_i_CylinderLow) |
                                         ((ULONG)AtapiReadPort1(chan, IDX_IO1_i_CylinderHigh) << 8) ;
                     ((PULONG)&NativeNumOfSectors)[1] = hNativeNumOfSectors;
@@ -1577,7 +1597,7 @@ IssueIdentify(
                                                 ((ULONGLONG)AtapiReadPort1(chan, IDX_IO1_i_CylinderLow)  << 8 ) |
                                                 ((ULONGLONG)AtapiReadPort1(chan, IDX_IO1_i_CylinderLow)  << 32) |
                                                 ((ULONGLONG)AtapiReadPort1(chan, IDX_IO1_i_CylinderHigh) << 16) |
-                                                ((ULONGLONG)AtapiReadPort1(chan, IDX_IO1_i_CylinderHigh) << 40)
+                                                ((ULONGLONG)AtapiReadPort1(chan, IDX_IO1_i_CylinderHigh) << 40) 
                                                 ;
                         }
 
@@ -1601,7 +1621,7 @@ IssueIdentify(
                     }
                 }
             }
-
+    
             if(NumOfSectors < 0x2100000 /*&& NumOfSectors > 31*1000*1000*/) {
                 // check for native LBA size
                 // some drives report ~32Gb in Identify Block
@@ -1893,7 +1913,7 @@ AtapiResetController__(
 #endif
     //ULONG RevID    =  deviceExtension->RevID;
     ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
-    UCHAR tmp8;
+    //UCHAR tmp8;
     UCHAR tmp16;
 
     KdPrint2((PRINT_PREFIX "AtapiResetController: Reset IDE %#x/%#x @ %#x\n", VendorID, DeviceID, slotNumber));
@@ -1975,7 +1995,7 @@ AtapiResetController__(
 
                     // Indicate ready for next request.
                     ScsiPortNotification(NextLuRequest,
-                                         deviceExtension,
+                                         deviceExtension, 
                                          PathId,
                                          TargetId,
                                          Lun);
@@ -1994,7 +2014,7 @@ AtapiResetController__(
         chan->ChannelCtrlFlags = 0;
         InterlockedExchange(&(chan->CheckIntr),
                                       CHECK_INTR_IDLE);
-
+        
         // Reset controller
         KdPrint2((PRINT_PREFIX "  disable intr (0)\n"));
         AtapiDisableInterrupts(deviceExtension, j);
@@ -2009,6 +2029,7 @@ AtapiResetController__(
                 goto default_reset;
             }
 
+#if 0
             /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
             if(ChipFlags & UNIATA_AHCI) {
                 mask = 0x0005 << j;
@@ -2021,14 +2042,27 @@ AtapiResetController__(
                     mask = 0x0001 << j;
                 }
             }
+#else
+            mask = 1 << chan->lun[0]->SATA_lun_map;
+            if (max_ldev > 1) {
+               mask |= (1 << chan->lun[1]->SATA_lun_map);
+            }
+#endif
             ChangePciConfig2(0x92, a & ~mask);
             AtapiStallExecution(10);
             ChangePciConfig2(0x92, a | mask);
             timeout = 100;
+
+            /* Wait up to 1 sec for "connect well". */
+            if (ChipFlags & (I6CH | I6CH2))
+                mask = mask << 8;
+            else
+                mask = mask << 4;
+
             while (timeout--) {
                 AtapiStallExecution(10000);
                 GetPciConfig2(0x92, tmp16);
-                if ((tmp16 & (mask << 4)) == (mask << 4)) {
+                if ((tmp16 & mask) == mask) {
                     AtapiStallExecution(10000);
                     break;
                 }
@@ -2065,7 +2099,7 @@ AtapiResetController__(
         default:
             if(ChipFlags & UNIATA_SATA) {
                 KdPrint2((PRINT_PREFIX "  SATA generic reset\n"));
-                UniataSataClearErr(HwDeviceExtension, j, UNIATA_SATA_IGNORE_CONNECT);
+                UniataSataClearErr(HwDeviceExtension, j, UNIATA_SATA_IGNORE_CONNECT, 0);
             }
 default_reset:
             KdPrint2((PRINT_PREFIX "  send reset\n"));
@@ -2084,7 +2118,7 @@ default_reset:
             KdPrint2((PRINT_PREFIX "  done\n"));
 
             break;
-        }
+        } // end switch()
 
         //if(!(ChipFlags & UNIATA_SATA)) {
         if(!UniataIsSATARangeAvailable(deviceExtension, j)) {
@@ -2129,7 +2163,7 @@ default_reset:
             statusByte = WaitOnBusyLong(chan);
             statusByte = UniataIsIdle(deviceExtension, statusByte);
             if(statusByte == 0xff) {
-                KdPrint2((PRINT_PREFIX
+                KdPrint2((PRINT_PREFIX 
                            "no drive, status %#x\n",
                            statusByte));
                 UniataForgetDevice(&(deviceExtension->lun[i + (j * 2)]));
@@ -2154,7 +2188,7 @@ default_reset:
                                   IDE_COMMAND_ATAPI_IDENTIFY, FALSE);
                 } else {
 
-                    KdPrint2((PRINT_PREFIX
+                    KdPrint2((PRINT_PREFIX 
                                "AtapiResetController: Status after soft reset %#x\n",
                                statusByte));
                 }
@@ -2235,7 +2269,7 @@ MapError(
     // Read the error register.
 
     errorByte = AtapiReadPort1(chan, IDX_IO1_i_Error);
-    KdPrint2((PRINT_PREFIX
+    KdPrint2((PRINT_PREFIX 
                "MapError: Error register is %#x\n",
                errorByte));
 
@@ -2244,7 +2278,7 @@ MapError(
         switch (errorByte >> 4) {
         case SCSI_SENSE_NO_SENSE:
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "ATAPI: No sense information\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2252,7 +2286,7 @@ MapError(
 
         case SCSI_SENSE_RECOVERED_ERROR:
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "ATAPI: Recovered error\n"));
             scsiStatus = 0;
             srbStatus = SRB_STATUS_SUCCESS;
@@ -2260,7 +2294,7 @@ MapError(
 
         case SCSI_SENSE_NOT_READY:
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "ATAPI: Device not ready\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2268,7 +2302,7 @@ MapError(
 
         case SCSI_SENSE_MEDIUM_ERROR:
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "ATAPI: Media error\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2276,7 +2310,7 @@ MapError(
 
         case SCSI_SENSE_HARDWARE_ERROR:
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "ATAPI: Hardware error\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2284,7 +2318,7 @@ MapError(
 
         case SCSI_SENSE_ILLEGAL_REQUEST:
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "ATAPI: Illegal request\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2292,7 +2326,7 @@ MapError(
 
         case SCSI_SENSE_UNIT_ATTENTION:
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "ATAPI: Unit attention\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2300,7 +2334,7 @@ MapError(
 
         case SCSI_SENSE_DATA_PROTECT:
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "ATAPI: Data protect\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2308,14 +2342,14 @@ MapError(
 
         case SCSI_SENSE_BLANK_CHECK:
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "ATAPI: Blank check\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
             break;
 
         case SCSI_SENSE_ABORTED_COMMAND:
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                         "Atapi: Command Aborted\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2323,7 +2357,7 @@ MapError(
 
         default:
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "ATAPI: Invalid sense information\n"));
             scsiStatus = 0;
             srbStatus = SRB_STATUS_ERROR;
@@ -2338,7 +2372,7 @@ MapError(
         chan->ReturningMediaStatus = errorByte;
 
         if (errorByte & IDE_ERROR_MEDIA_CHANGE_REQ) {
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "IDE: Media change\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2358,7 +2392,7 @@ MapError(
             }
 
         } else if (errorByte & IDE_ERROR_COMMAND_ABORTED) {
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "IDE: Command abort\n"));
             srbStatus = SRB_STATUS_ABORTED;
             scsiStatus = SCSISTAT_CHECK_CONDITION;
@@ -2381,7 +2415,7 @@ MapError(
 
         } else if (errorByte & IDE_ERROR_END_OF_MEDIA) {
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "IDE: End of media\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2407,7 +2441,7 @@ MapError(
 
         } else if (errorByte & IDE_ERROR_ILLEGAL_LENGTH) {
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "IDE: Illegal length\n"));
             srbStatus = SRB_STATUS_INVALID_REQUEST;
 
@@ -2428,7 +2462,7 @@ MapError(
 
         } else if (errorByte & IDE_ERROR_BAD_BLOCK) {
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "IDE: Bad block\n"));
             srbStatus = SRB_STATUS_ERROR;
             scsiStatus = SCSISTAT_CHECK_CONDITION;
@@ -2448,7 +2482,7 @@ MapError(
 
         } else if (errorByte & IDE_ERROR_ID_NOT_FOUND) {
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "IDE: Id not found\n"));
             srbStatus = SRB_STATUS_ERROR;
             scsiStatus = SCSISTAT_CHECK_CONDITION;
@@ -2471,7 +2505,7 @@ MapError(
 
         } else if (errorByte & IDE_ERROR_MEDIA_CHANGE) {
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                        "IDE: Media change\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2492,7 +2526,7 @@ MapError(
 
         } else if (errorByte & IDE_ERROR_DATA_ERROR) {
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                    "IDE: Data error\n"));
             scsiStatus = SCSISTAT_CHECK_CONDITION;
             srbStatus = SRB_STATUS_ERROR;
@@ -2520,18 +2554,18 @@ MapError(
         if (deviceExtension->lun[ldev].ErrorCount >= MAX_ERRORS) {
 //            deviceExtension->DWordIO = FALSE;
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                         "MapError: ErrorCount >= MAX_ERRORS\n"));
 
             deviceExtension->lun[ldev].DeviceFlags &= ~DFLAGS_DWORDIO_ENABLED;
             deviceExtension->lun[ldev].MaximumBlockXfer = 0;
             BrutePoint();
 
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                         "MapError: Disabling 32-bit PIO and Multi-sector IOs\n"));
 
             // Log the error.
-            KdPrint2((PRINT_PREFIX
+            KdPrint2((PRINT_PREFIX 
                         "ScsiPortLogError: devExt %#x, Srb %#x, P:T:D=%d:%d:%d, MsgId %#x (%d)\n",
                               HwDeviceExtension,
                               Srb,
@@ -2703,7 +2737,7 @@ AtapiHwInitialize__(
             }
 
             if(LunExt->IdentifyData.MajorRevision) {
-
+            
                 if(LunExt->opt_ReadCacheEnable) {
                     KdPrint2((PRINT_PREFIX "  Try Enable Read Cache\n"));
                     // If supported, setup read/write cacheing
@@ -2713,7 +2747,7 @@ AtapiHwInitialize__(
 
                     // Check for errors.
                     if (statusByte & IDE_STATUS_ERROR) {
-                        KdPrint2((PRINT_PREFIX
+                        KdPrint2((PRINT_PREFIX 
                                     "AtapiHwInitialize: Enable read/write cacheing on Device %d failed\n",
                                     i));
                         LunExt->DeviceFlags &= ~DFLAGS_RCACHE_ENABLED;
@@ -2735,7 +2769,7 @@ AtapiHwInitialize__(
                                         0, ATA_C_F_ENAB_WCACHE, ATA_WAIT_BASE_READY);
                     // Check for errors.
                     if (statusByte & IDE_STATUS_ERROR) {
-                        KdPrint2((PRINT_PREFIX
+                        KdPrint2((PRINT_PREFIX 
                                     "AtapiHwInitialize: Enable write cacheing on Device %d failed\n",
                                     i));
                         LunExt->DeviceFlags &= ~DFLAGS_WCACHE_ENABLED;
@@ -3085,7 +3119,7 @@ AtapiCallBack__(
         goto ReturnCallback;
     }
 
-#if DBG
+#ifdef DBG
     if (!IS_RDP((srb->Cdb[0]))) {
         KdPrint2((PRINT_PREFIX "AtapiCallBack: Invalid CDB marked as RDP - %#x\n", srb->Cdb[0]));
     }
@@ -3114,7 +3148,7 @@ AtapiCallBack__(
 
         // Ask for next request.
         ScsiPortNotification(NextLuRequest,
-                             deviceExtension,
+                             deviceExtension, 
                              PathId,
                              TargetId,
                              Lun);
@@ -3228,7 +3262,7 @@ AtapiInterrupt(
     for(_c=0; _c<deviceExtension->NumberChannels; _c++) {
         checked[_c] = FALSE;
     }
-//    fc =
+//    fc = 
 //    atapiDev = (deviceExtension->lun[ldev].DeviceFlags & DFLAGS_ATAPI_DEVICE) ? TRUE : FALSE;
     for(pass=0; pass<2; pass++) {
         for(_c=0; _c<deviceExtension->NumberChannels; _c++) {
@@ -3418,7 +3452,7 @@ AtapiInterruptDpc(
                                           CHECK_INTR_DETECTED) != CHECK_INTR_DETECTED) {
                 continue;
             }
-
+                        
         } else {
             deviceExtension->chan[c].ChannelCtrlFlags &= ~CTRFLAGS_DPC_REQ;
         }
@@ -3604,7 +3638,7 @@ AtapiCheckInterrupt__(
 
     if((ChipFlags & UNIATA_AHCI) &&
         UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
-        OurInterrupt = UniataAhciStatus(HwDeviceExtension, lChannel);
+        OurInterrupt = UniataAhciStatus(HwDeviceExtension, lChannel, -1);
         return OurInterrupt;
     }
 
@@ -3622,7 +3656,7 @@ AtapiCheckInterrupt__(
             status = AtapiReadPortEx4(chan, (ULONG_PTR)&deviceExtension->BaseIoAddressBM_0,0x1c);
             if (!DmaTransfer)
                 break;
-            if (!(status &
+            if (!(status & 
                   ((Channel) ? 0x00004000 : 0x00000400))) {
                 KdPrint2((PRINT_PREFIX "  Promise old/new unexpected\n"));
                 return FALSE;
@@ -3678,18 +3712,18 @@ AtapiCheckInterrupt__(
 
         /* check for and handle connect events */
         if(((pr_status & (0x0cUL << shift)) == (0x04UL << shift)) ) {
-            UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_ATTACH);
+            UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_ATTACH, 0);
         }
         /* check for and handle disconnect events */
         if((pr_status & (0x08UL << shift)) &&
             !((pr_status & (0x04UL << shift) &&
-            AtapiReadPort4(chan, IDX_SATA_SStatus))) ) {
-            UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_DETACH);
+            UniataSataReadPort4(chan, IDX_SATA_SStatus, 0))) ) {
+            UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_DETACH, 0);
         }
         /* do we have any device action ? */
         if(!(pr_status & (0x01UL << shift))) {
             KdPrint2((PRINT_PREFIX "  nVidia unexpected\n"));
-            if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT)) {
+            if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
                 OurInterrupt = 2;
             } else {
                 return FALSE;
@@ -3726,7 +3760,7 @@ AtapiCheckInterrupt__(
                     * controllers continue to assert IRQ as long as
                     * SError bits are pending.  Clear SError immediately.
                     */
-                    if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT)) {
+                    if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
                         OurInterrupt = 2;
                     }
                 }
@@ -3771,13 +3805,30 @@ AtapiCheckInterrupt__(
         AtapiWritePort1(chan, IDX_BM_Command,
             AtapiReadPort1(chan, IDX_BM_Command) & ~BM_COMMAND_START_STOP);
         goto skip_dma_stat_check;
+    case ATA_INTEL_ID:
+        if(UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
+            if(ChipFlags & UNIATA_AHCI) {
+                // Do nothing here
+            } else
+            if(ChipFlags & UNIATA_SATA) {
+                if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
+                    OurInterrupt = 2;
+                }
+                if(!(chan->ChannelCtrlFlags & CTRFLAGS_NO_SLAVE)) {
+                    if(UniataSataClearErr(chan->DeviceExtension, chan->lChannel, UNIATA_SATA_IGNORE_CONNECT, 1)) {
+                        OurInterrupt = 2;
+                    }
+                }
+            }
+        }
+        break;
     default:
         if(UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
             if(ChipFlags & UNIATA_AHCI) {
                 // Do nothing here
             } else
             if(ChipFlags & UNIATA_SATA) {
-                if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT)) {
+                if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
                     OurInterrupt = 2;
                 }
             }
@@ -3882,7 +3933,7 @@ skip_dma_stat_check:
     KdPrint2((PRINT_PREFIX "  base status %#x\n", statusByte));
     if (statusByte == 0xff) {
         // interrupt from empty controller ?
-    } else
+    } else 
     if(!(statusByte & (IDE_STATUS_DRQ | IDE_STATUS_DRDY))) {
         KdPrint2((PRINT_PREFIX "  no DRQ/DRDY set\n"));
         return OurInterrupt;
@@ -4545,12 +4596,9 @@ IntrPrepareResetController:
 
             // IDE path. Check if words left is at least DEV_BSIZE/2 = 256.
             if (AtaReq->WordsLeft < wordsThisInterrupt) {
-
                // Transfer only words requested.
                wordCount = AtaReq->WordsLeft;
-
             } else {
-
                // Transfer next block.
                wordCount = wordsThisInterrupt;
             }
@@ -4637,12 +4685,9 @@ IntrPrepareResetController:
 
             // Check if words left is at least 256.
             if (AtaReq->WordsLeft < wordsThisInterrupt) {
-
                // Transfer only words requested.
                wordCount = AtaReq->WordsLeft;
-
             } else {
-
                // Transfer next block.
                wordCount = wordsThisInterrupt;
             }
@@ -8388,7 +8433,6 @@ DriverEntry(
         } while(t0.QuadPart == t1.QuadPart);
         g_PerfDt = (ULONG)((t1.QuadPart - t0.QuadPart)/10);
         KdPrint(("Performance calibration: dt=%d, counter=%I64d\n", g_PerfDt, g_Perf ));
-
     } else {
         KdPrint(("UniATA Init: ReEnter\n"));
         ReEnter = TRUE;
@@ -8544,7 +8588,7 @@ DriverEntry(
                                                Argument2,
                                                &hwInitializationData.comm,
                                                (PVOID)(i | (alt ? 0x80000000 : 0)));
-                KdPrint2((PRINT_PREFIX "Status %#x\n", newStatus));
+                KdPrint2((PRINT_PREFIX "ScsiPortInitialize Status %#x\n", newStatus));
                 if (newStatus < statusToReturn) {
                     statusToReturn = newStatus;
                 }
@@ -8592,7 +8636,7 @@ DriverEntry(
                                            Argument2,
                                            &hwInitializationData.comm,
                                            (PVOID)i);
-            KdPrint2((PRINT_PREFIX "Status %#x\n", newStatus));
+            KdPrint2((PRINT_PREFIX "ScsiPortInitialize Status %#x\n", newStatus));
         }
 #endif //0
         if(g_opt_Verbose) {
@@ -8646,6 +8690,7 @@ DriverEntry(
                                        Argument2,
                                        &hwInitializationData.comm,
                                        (PVOID)i);
+        KdPrint2((PRINT_PREFIX "ScsiPortInitialize Status %#x\n", newStatus));
         if (newStatus < statusToReturn)
             statusToReturn = newStatus;
 
@@ -8689,6 +8734,7 @@ DriverEntry(
                                         Argument2,
                                         &hwInitializationData.comm,
                                         &adapterCount);
+        KdPrint2((PRINT_PREFIX "ScsiPortInitialize Status %#x\n", newStatus));
         if (newStatus < statusToReturn)
             statusToReturn = newStatus;
     }
@@ -8702,12 +8748,13 @@ DriverEntry(
                                         Argument2,
                                         &hwInitializationData.comm,
                                         &adapterCount);
+        KdPrint2((PRINT_PREFIX "ScsiPortInitialize Status %#x\n", newStatus));
         if (newStatus < statusToReturn)
             statusToReturn = newStatus;
     }
     InDriverEntry = FALSE;
 
-    KdPrint2((PRINT_PREFIX "\n\nLeave ATAPI IDE MiniPort DriverEntry with status %#x\n", statusToReturn));
+    KdPrint2((PRINT_PREFIX "\n\nLeave UNIATA MiniPort DriverEntry with status %#x\n", statusToReturn));
 
     return statusToReturn;
 
@@ -9181,4 +9228,3 @@ _PrintNtConsole(
 
 } // end PrintNtConsole()
 
-
index d52fef2..64d8d0b 100644 (file)
@@ -1,6 +1,6 @@
 /*++
 
-Copyright (c) 2002-2008 Alexander A. Telyatnikov (Alter)
+Copyright (c) 2002-2010 Alexander A. Telyatnikov (Alter)
 
 Module Name:
     id_dma.cpp
@@ -182,7 +182,7 @@ err_1:
             }
         }
     }
-#endif //USE_OWN_DMA
+
 
     if(deviceExtension->HwFlags & UNIATA_AHCI) {
         if(chan->AHCI_CL) {
@@ -206,7 +206,7 @@ err_1:
             }
         }
     }
-
+    #endif //USE_OWN_DMA
     return;
 } // end AtapiDmaAlloc()
 
@@ -289,7 +289,7 @@ retry_DB_IO:
     if(!dma_count || ((LONG)(dma_base) == -1)) {
         KdPrint2((PRINT_PREFIX "AtapiDmaSetup: No 1st block\n" ));
         //AtaReq->dma_base = NULL;
-        AtaReq->ahci_base64 = 0;
+        AtaReq->ahci_base64 = NULL;
         return FALSE;
     }
 
@@ -311,7 +311,7 @@ retry_DB_IO:
         if (i >= max_entries) {
             KdPrint2((PRINT_PREFIX "too many segments in DMA table\n" ));
             //AtaReq->dma_base = NULL;
-            AtaReq->ahci_base64 = 0;
+            AtaReq->ahci_base64 = NULL;
             return FALSE;
         }
         KdPrint2((PRINT_PREFIX "  get Phys(data[n]=%x)\n", data ));
@@ -1028,6 +1028,13 @@ set_new_acard:
         /********************/
         /* AMD, nVidia, VIA */
         /********************/
+        if((VendorID == ATA_VIA_ID) &&
+           (ChipFlags & VIASATA) &&
+           (Channel == 0)) {
+            AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_SA150);
+            return;
+        }
+
         static const UCHAR via_modes[5][7] = {
             { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 },        /* ATA33 and New Chips */
             { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 },        /* ATA66 */
@@ -1052,11 +1059,14 @@ set_new_acard:
                 return;
             }
         }
-        for(i = wdmamode; i>=0; i--) {
-            SetPciConfig1(reg-0x08, via_pio[5+i]);
-            if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
-                SetPciConfig1(reg, 0x8b);
-                return;
+        if(!(ChipFlags & VIABAR)) {
+           /* This chip can't do WDMA. */
+            for(i = wdmamode; i>=0; i--) {
+                SetPciConfig1(reg-0x08, via_pio[5+i]);
+                if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
+                    SetPciConfig1(reg, 0x8b);
+                    return;
+                }
             }
         }
         /* set PIO mode timings */
@@ -1247,6 +1257,48 @@ set_new_acard:
             break;
         }
 
+        if(deviceExtension->DevID == ATA_ISCH) {
+            ULONG tim;
+            GetPciConfig4(0x80 + dev*4, tim);
+
+            for(i=udmamode; i>=0; i--) {
+                if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
+                    tim |= (0x1 << 31);
+                    tim &= ~(0x7 << 16);
+                    tim |= (i << 16);
+
+                    idx = i+8;
+                    udma_ok = TRUE;
+                    apiomode = ATA_PIO4;
+                    break;
+                }
+            }
+            if(!udma_ok) {
+                for(i=wdmamode; i>=0; i--) {
+                    if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
+                        tim &= ~(0x1 << 31);
+                        tim &= ~(0x3 << 8);
+                        tim |= (i << 8);
+
+                        idx = i+5;
+                        udma_ok = TRUE;
+                        apiomode = (i == 0) ? ATA_PIO0 :
+                            (i == 1) ? ATA_PIO3 : ATA_PIO4;
+                        break;
+                    }
+                }
+            }
+            if(!udma_ok) {
+                AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
+                idx = apiomode;
+            }
+            tim &= ~(0x7);
+            tim |= (apiomode & 0x7);
+            SetPciConfig4(0x80 + dev*4, tim);
+
+            break;
+        }
+
         GetPciConfig2(0x48, reg48);
         if(!(ChipFlags & ICH4_FIX)) {
             GetPciConfig2(0x4a, reg4a);
@@ -1751,6 +1803,94 @@ setup_drive_ite:
                 SetPciConfig1(0x54 + offset, chtiming[apiomode]);
             }
             return;
+        } else
+        if(ChipType == ITE_133_NEW) {
+            //static const USHORT reg54_timings[] = { 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x1001, 0x1001 };
+            static const UCHAR udmatiming[] =
+                { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10  };
+            static const UCHAR timings[] =
+                { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
+                          0x23, 0x23, 0x23, 0x23, 0x23, 0x02, 0x02 };
+            BOOLEAN udma_ok = FALSE;
+            BOOLEAN ok = FALSE;
+            UCHAR timing = 0;
+
+            WCHAR reg40;
+            UCHAR reg44;
+            USHORT reg4a;
+            USHORT reg54;
+            USHORT mask40=0, new40=0;
+            UCHAR mask44=0, new44=0;
+
+            GetPciConfig2(0x40, reg40);
+            GetPciConfig1(0x44, reg44);
+            GetPciConfig2(0x4a, reg4a);
+            GetPciConfig2(0x54, reg54);
+
+            if(!(reg54 & (0x10 << dev))) {
+                // 80-pin check
+                udmamode = min(udmamode, 2);
+            }
+
+            for(i=udmamode; i>=0; i--) {
+                if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
+                    ChangePciConfig1(0x48, a | (1 << dev) );
+                   ChangePciConfig2(0x4a,
+                                    (a & ~(0x3 << (dev*4))) |
+                                    (udmatiming[i] << (dev*4)) );
+                    ok=TRUE;
+                    udma_ok=TRUE;
+                    timing = timings[i+8];
+                    break;
+                }
+            }
+             
+            for(i=wdmamode; !ok && i>=0; i--) {
+                if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
+
+                    ok=TRUE;
+                    timing = timings[i+5];
+                    break;
+                }
+            }
+
+            if(!ok) {
+                AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
+                timing = timings[apiomode];
+            }
+
+            if(!udma_ok) {
+                ChangePciConfig1(0x48, a & ~(1 << dev) );
+                ChangePciConfig2(0x4a, a & ~(0x3 << (dev << 2)) );
+            }
+            if (udma_ok && udmamode >= ATA_UDMA2) {
+                reg54 |= (0x1 << dev);
+            } else {
+                reg54 &= ~(0x1 << dev);
+            }
+            if (udma_ok && udmamode >= ATA_UDMA5) {
+                reg54 |= (0x1000 << dev);
+            } else {
+                reg54 &= ~(0x1000 << dev);
+            }
+            SetPciConfig2(0x54, reg54 );
+
+            reg40 &= 0xff00;
+            reg40 |= 0x4033;
+
+            if(!(ldev & 1)) {
+                reg40 |= (ATAPI_DEVICE(deviceExtension, ldev) ? 0x04 : 0x00);
+                mask40 = 0x3300;
+                new40 = timing << 8;
+            } else {
+                reg40 |= (ATAPI_DEVICE(deviceExtension, ldev) ? 0x40 : 0x00);
+                mask44 = 0x0f;
+                new44 = ((timing & 0x30) >> 2) |
+                        (timing & 0x03);
+            }
+            SetPciConfig2(0x40, (reg40 & ~mask40) | new40);
+            SetPciConfig1(0x44, (reg44 & ~mask44) | new44);
+            return;
         }
 
         return;
@@ -2092,7 +2232,8 @@ via82c_timing(
     }
 
     // Newer chips dislike this:
-    if(!(deviceExtension->HwFlags & VIAAST)) {
+    if(/*!(deviceExtension->HwFlags & VIAAST)*/
+        deviceExtension->MaxTransferMode < ATA_UDMA6) {
         /* PIO address setup */
         GetPciConfig1(0x4c, t);
         t = (t & ~(3 << ((3 - dev) << 1))) | (FIT(setup - 1, 0, 3) << ((3 - dev) << 1));
index a426991..6dce17c 100644 (file)
@@ -1,6 +1,6 @@
 /*++
 
-Copyright (c) 2004-2008 Alexandr A. Telyatnikov (Alter)
+Copyright (c) 2004-2010 Alexandr A. Telyatnikov (Alter)
 
 Module Name:
     id_init.cpp
@@ -62,6 +62,12 @@ UniataChipDetectChannels(
     ULONG ChipFlags= deviceExtension->HwFlags & CHIPFLAG_MASK;
 
     KdPrint2((PRINT_PREFIX "UniataChipDetectChannels:\n" ));
+
+    if(deviceExtension->MasterDev) {
+        KdPrint2((PRINT_PREFIX "MasterDev -> 1 chan\n"));
+        deviceExtension->NumberChannels = 1;
+    }
+
     switch(VendorID) {
     case ATA_ACER_LABS_ID:
         switch(deviceExtension->DevID) {
@@ -96,8 +102,8 @@ UniataChipDetectChannels(
     case ATA_ATI_ID:
         KdPrint2((PRINT_PREFIX "ATI\n"));
         switch(deviceExtension->DevID) {
-        case ATA_ATI_IXP600
-        case ATA_ATI_IXP700:
+        case 0x438c1002
+        case 0x439c1002:
             /* IXP600 & IXP700 only have 1 PATA channel */
             if(BMList[deviceExtension->DevIndex].channel) {
                 KdPrint2((PRINT_PREFIX "New ATI no 2nd PATA chan\n"));
@@ -129,18 +135,57 @@ UniataChipDetectChannels(
         }
         break;
     case ATA_VIA_ID:
-        if((deviceExtension->DevID == 0x32491106) &&
-           ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[5].RangeStart)) {
+        if(/*(deviceExtension->DevID == 0x32491106) &&
+           ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[5].RangeStart)*/
+           deviceExtension->HwFlags & VIABAR) {
             deviceExtension->NumberChannels = 3;
             KdPrint2((PRINT_PREFIX "VIA 3 chan\n"));
         }
         break;
+    case ATA_ITE_ID:
+        /* ITE ATA133 controller */
+        if(deviceExtension->DevID == 0x82131283) { 
+            if(BMList[deviceExtension->DevIndex].channel) {
+                KdPrint2((PRINT_PREFIX "New ITE has no 2nd PATA chan\n"));
+                return FALSE;
+            }
+            deviceExtension->NumberChannels = 1;
+            KdPrint2((PRINT_PREFIX "New ITE PATA 1 chan\n"));
+        }
+        break;
+    case ATA_INTEL_ID:
+        /* New Intel PATA controllers */
+        if(/*deviceExtension->DevID == 0x27df8086 ||
+           deviceExtension->DevID == 0x269e8086 ||
+           deviceExtension->DevID == ATA_I82801HBM*/
+           ChipFlags & I1CH) { 
+            if(BMList[deviceExtension->DevIndex].channel) {
+                KdPrint2((PRINT_PREFIX "New Intel PATA has no 2nd chan\n"));
+                return FALSE;
+            }
+            deviceExtension->NumberChannels = 1;
+            KdPrint2((PRINT_PREFIX "New Intel PATA 1 chan\n"));
+        }
+        break;
+    case ATA_JMICRON_ID:
+        /* New JMicron PATA controllers */
+        if(deviceExtension->DevID == ATA_JMB361 ||
+           deviceExtension->DevID == ATA_JMB363 ||
+           deviceExtension->DevID == ATA_JMB368) { 
+            if(BMList[deviceExtension->DevIndex].channel) {
+                KdPrint2((PRINT_PREFIX "New JMicron has no 2nd chan\n"));
+                return FALSE;
+            }
+            deviceExtension->NumberChannels = 1;
+            KdPrint2((PRINT_PREFIX "New JMicron PATA 1 chan\n"));
+        }
+        break;
     } // end switch(VendorID)
     return TRUE;
 
 } // end UniataChipDetectChannels()
 
-BOOLEAN
+NTSTATUS
 NTAPI
 UniataChipDetect(
     IN PVOID HwDeviceExtension,
@@ -189,18 +234,19 @@ UniataChipDetect(
     if(i != BMLIST_TERMINATOR) {
         DevTypeInfo = (PBUSMASTER_CONTROLLER_INFORMATION)&BusMasterAdapters[i];
     } else {
+unknown_dev:
         KdPrint2((PRINT_PREFIX "  unknown dev, BM addr %#x", BaseIoAddressBM));
         DevTypeInfo = NULL;
         KdPrint2((PRINT_PREFIX "  MaxTransferMode %#x\n", deviceExtension->MaxTransferMode));
 
         if(!UniataChipDetectChannels(HwDeviceExtension, pciData, DeviceNumber, ConfigInfo)) {
-            return FALSE;
+            return STATUS_UNSUCCESSFUL;
         }
         if(!UniataAllocateLunExt(deviceExtension, UNIATA_ALLOCATE_NEW_LUNS)) {
-            return FALSE;
+            return STATUS_UNSUCCESSFUL;
         }
 
-        return FALSE;
+        return STATUS_NOT_FOUND;
     }
 
     static BUSMASTER_CONTROLLER_INFORMATION const SiSAdapters[] = {
@@ -254,11 +300,18 @@ UniataChipDetect(
         PCI_DEV_HW_SPEC_BM( 8231, 1106, 0x00, ATA_UDMA5, "VIA 8231"   , VIA100 | VIABUG ),
         PCI_DEV_HW_SPEC_BM( 3074, 1106, 0x00, ATA_UDMA5, "VIA 8233"   , VIA100 | 0x00   ),
         PCI_DEV_HW_SPEC_BM( 3109, 1106, 0x00, ATA_UDMA5, "VIA 8233C"  , VIA100 | 0x00   ),
-        PCI_DEV_HW_SPEC_BM( 3147, 1106, 0x00, ATA_UDMA6, "VIA 8233A"  , VIA133 | VIAAST ),
-        PCI_DEV_HW_SPEC_BM( 3177, 1106, 0x00, ATA_UDMA6, "VIA 8235"   , VIA133 | VIAAST ),
-        PCI_DEV_HW_SPEC_BM( 3227, 1106, 0x00, ATA_UDMA6, "VIA 8237"   , VIA133 | VIAAST ),
-        PCI_DEV_HW_SPEC_BM( 0591, 1106, 0x00, ATA_UDMA6, "VIA 8237A"  , VIA133 | VIAAST ),
-        PCI_DEV_HW_SPEC_BM( 3349, 1106, 0x00, ATA_UDMA6, "VIA 8251"   , VIA133 | VIAAST ),
+        PCI_DEV_HW_SPEC_BM( 3147, 1106, 0x00, ATA_UDMA6, "VIA 8233A"  , VIA133 | 0x00 ),
+        PCI_DEV_HW_SPEC_BM( 3177, 1106, 0x00, ATA_UDMA6, "VIA 8235"   , VIA133 | 0x00 ),
+        PCI_DEV_HW_SPEC_BM( 3227, 1106, 0x00, ATA_UDMA6, "VIA 8237"   , VIA133 | 0x00 ),
+        PCI_DEV_HW_SPEC_BM( 0591, 1106, 0x00, ATA_UDMA6, "VIA 8237A"  , VIA133 | 0x00 ),
+        // presence of AHCI controller means something about isa-mapped part
+        PCI_DEV_HW_SPEC_BM( 5337, 1106, 0x00, ATA_UDMA6, "VIA 8237S"  , VIA133 | 0x00 ),
+        PCI_DEV_HW_SPEC_BM( 5372, 1106, 0x00, ATA_UDMA6, "VIA 8237"   , VIA133 | 0x00 ),
+        PCI_DEV_HW_SPEC_BM( 7372, 1106, 0x00, ATA_UDMA6, "VIA 8237"   , VIA133 | 0x00 ),
+        PCI_DEV_HW_SPEC_BM( 3349, 1106, 0x00, ATA_UDMA6, "VIA 8251"   , VIA133 | 0x00 ),
+        PCI_DEV_HW_SPEC_BM( 8324, 1106, 0x00, ATA_SA150, "VIA CX700"  , VIA133 | VIASATA),
+        PCI_DEV_HW_SPEC_BM( 8353, 1106, 0x00, ATA_SA150, "VIA VX800"  , VIA133 | VIASATA),
+        PCI_DEV_HW_SPEC_BM( 8409, 1106, 0x00, ATA_UDMA6, "VIA VX855"  , VIA133 | 0x00 ),
         PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, BMLIST_TERMINATOR       , NULL         , BMLIST_TERMINATOR )
         };
 
@@ -286,20 +339,30 @@ UniataChipDetect(
     case ATA_VIA_ID: 
         KdPrint2((PRINT_PREFIX "ATA_VIA_ID\n"));
         // New chips have own DeviceId
-        if(deviceExtension->DevID != ATA_VIA82C571)
+        if(deviceExtension->DevID != ATA_VIA82C571 &&
+           deviceExtension->DevID != ATA_VIACX700IDE &&
+           deviceExtension->DevID != ATA_VIASATAIDE) {
+            KdPrint2((PRINT_PREFIX "Via new\n"));
             break;
-        // Old chips have same DeviceId, we can distinguish between them
-        // only by SouthBridge DeviceId
+        }
+        KdPrint2((PRINT_PREFIX "Via-old-style %x\n", deviceExtension->DevID));
+        // Traditionally, chips have same DeviceId, we can distinguish between them
+        // only by ISA Bridge DeviceId
         DevTypeInfo = (BUSMASTER_CONTROLLER_INFORMATION*)&ViaSouthAdapters[0];
-        i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber, slotNumber, NULL);
+        i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber,
+                               PCISLOTNUM_NOT_SPECIFIED/*slotNumber*/, NULL);
+/*        if(i == BMLIST_TERMINATOR) {
+            i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, NULL);
+        }*/
         if(i != BMLIST_TERMINATOR) {
             KdPrint2((PRINT_PREFIX "VIASOUTH\n"));
             deviceExtension->HwFlags |= VIASOUTH;
         }
         DevTypeInfo = (BUSMASTER_CONTROLLER_INFORMATION*)&ViaAdapters[0];
-        i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber, slotNumber, NULL);
+        i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber,
+                               PCISLOTNUM_NOT_SPECIFIED/*slotNumber*/, NULL);
         if(i != BMLIST_TERMINATOR) {
-            deviceExtension->FullDevName = SiSAdapters[i].FullDevName;
+            deviceExtension->FullDevName = ViaAdapters[i].FullDevName;
         }
         goto for_ugly_chips;
 
@@ -351,13 +414,13 @@ UniataChipDetect(
 
         case 0x81721283:        /* IT8172 IDE controller */
             deviceExtension->MaxTransferMode = ATA_UDMA2;
-            *simplexOnly = TRUE;
+            *simplexOnly = TRUE; 
             break;
 
         default:
-            return FALSE;
+            return STATUS_NOT_FOUND;
         }
-        return TRUE;
+        return STATUS_SUCCESS;
 #endif
     }
 
@@ -365,7 +428,8 @@ UniataChipDetect(
 for_ugly_chips:
     KdPrint2((PRINT_PREFIX "i: %#x\n", i));
     if(i == BMLIST_TERMINATOR) {
-        return FALSE;
+        goto unknown_dev;
+        //return STATUS_NOT_FOUND;
     }
     deviceExtension->MaxTransferMode =  DevTypeInfo[i].MaxTransferMode;
     deviceExtension->HwFlags         |= DevTypeInfo[i].RaidFlags;
@@ -404,10 +468,10 @@ for_ugly_chips:
     ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
 
     if(!UniataChipDetectChannels(HwDeviceExtension, pciData, DeviceNumber, ConfigInfo)) {
-        return FALSE;
+        return STATUS_UNSUCCESSFUL;
     }
     if(!UniataAllocateLunExt(deviceExtension, UNIATA_ALLOCATE_NEW_LUNS)) {
-        return FALSE;
+        return STATUS_UNSUCCESSFUL;
     }
 
     switch(VendorID) {
@@ -733,6 +797,12 @@ for_ugly_chips:
 
     case ATA_VIA_ID: {
 
+        if(ChipFlags & VIASATA) {
+            /* 2 SATA without SATA registers on first channel + 1 PATA on second */
+            // do nothing, generic PATA INIT
+            KdPrint2((PRINT_PREFIX "VIA SATA without SATA regs\n"));
+            break;
+        }
         if(ChipFlags & UNIATA_SATA) {
 
             ULONG IoSize = 0;
@@ -752,7 +822,7 @@ for_ugly_chips:
                 KdPrint2((PRINT_PREFIX "IoSize %x\n", IoSize));
                 /*deviceExtension->*/BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
                                         5, 0, IoSize * deviceExtension->NumberChannels);
-                if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
+                if(BaseMemAddress && (*ConfigInfo->AccessRanges)[5].RangeInMemory) {
                     KdPrint2((PRINT_PREFIX "MemIo\n"));
                     MemIo = TRUE;
                 }
@@ -775,36 +845,46 @@ for_ugly_chips:
 
                         chan = &deviceExtension->chan[c];
 
-                        BaseIo = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, c, 0, 0x80);
+                        BaseIo = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, c, 0, /*0x80*/ sizeof(IDE_REGISTERS_1) + sizeof(IDE_REGISTERS_2)*2);
 
                         for (i=0; i<=IDX_IO1_SZ; i++) {
                             chan->RegTranslation[IDX_IO1+i].Addr           = BaseIo + i;
                         }
-                        chan->RegTranslation[IDX_IO2_AltStatus].Addr       = BaseIo + sizeof(IDE_REGISTERS_1) + 2 + FIELD_OFFSET(IDE_REGISTERS_2, AltStatus   );
+                        chan->RegTranslation[IDX_IO2_AltStatus].Addr       = BaseIo + sizeof(IDE_REGISTERS_1) + 2;
                         UniataInitSyncBaseIO(chan);
 
                         for (i=0; i<=IDX_BM_IO_SZ; i++) {
                             chan->RegTranslation[IDX_BM_IO+i].Addr         = BaseIoAddressBM_0 + sizeof(IDE_BUSMASTER_REGISTERS)*c + i;
                         }
-                        if(c < 2) {
-                            // Do not setup SATA registers for PATA part
-                            chan->RegTranslation[IDX_SATA_SStatus].Addr        = BaseMemAddress + (c * IoSize);
-                            chan->RegTranslation[IDX_SATA_SStatus].MemIo       = MemIo;
-                            chan->RegTranslation[IDX_SATA_SError].Addr         = BaseMemAddress + 4 + (c * IoSize);
-                            chan->RegTranslation[IDX_SATA_SError].MemIo        = MemIo;
-                            chan->RegTranslation[IDX_SATA_SControl].Addr       = BaseMemAddress + 8 + (c * IoSize);
-                            chan->RegTranslation[IDX_SATA_SControl].MemIo      = MemIo;
-
-                            chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
-                        }
 
                     }
                 }
+                for(c=0; c<deviceExtension->NumberChannels; c++) {
+                    chan = &deviceExtension->chan[c];
+                    if((ChipFlags & VIABAR) && (c==2)) {
+                        // Do not setup SATA registers for PATA part
+                        for (i=0; i<=IDX_SATA_IO_SZ; i++) {
+                            chan->RegTranslation[IDX_SATA_IO+i].Addr = 0;
+                            chan->RegTranslation[IDX_SATA_IO+i].MemIo = 0;
+                        }
+                        break;
+                    }
+                    chan->RegTranslation[IDX_SATA_SStatus].Addr        = BaseMemAddress + (c * IoSize);
+                    chan->RegTranslation[IDX_SATA_SStatus].MemIo       = MemIo;
+                    chan->RegTranslation[IDX_SATA_SError].Addr         = BaseMemAddress + 4 + (c * IoSize);
+                    chan->RegTranslation[IDX_SATA_SError].MemIo        = MemIo;
+                    chan->RegTranslation[IDX_SATA_SControl].Addr       = BaseMemAddress + 8 + (c * IoSize);
+                    chan->RegTranslation[IDX_SATA_SControl].MemIo      = MemIo;
+
+                    chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
+                }
+
             }
         }
         break; }
     case ATA_INTEL_ID: {
 
+        BOOLEAN IsPata;
         if(!(ChipFlags & UNIATA_SATA)) {
             break;
         }
@@ -870,45 +950,144 @@ for_ugly_chips:
 
             break;
         }
-        /* SATA parts can be either compat or AHCI */
-        if(ChipFlags & UNIATA_AHCI) {
-
+        if(deviceExtension->MaxTransferMode >= ATA_SA150) {
             GetPciConfig1(0x90, tmp8);
-            if(tmp8 & 0xc0) {
-                KdPrint2((PRINT_PREFIX "AHCI not supported yet\n"));
-                return FALSE;
+            /* SATA parts can be either compat or AHCI */
+            if(ChipFlags & UNIATA_AHCI) {
+
+                if(tmp8 & 0xc0) {
+                    //KdPrint2((PRINT_PREFIX "AHCI not supported yet\n"));
+                    //return FALSE;
+                    KdPrint2((PRINT_PREFIX "try run AHCI\n"));
+                    break;
+                }
+                KdPrint2((PRINT_PREFIX "Compatible mode\n"));
             }
             deviceExtension->HwFlags &= ~UNIATA_AHCI;
-        }
-#if 0
-        if(ChipFlags & UNIATA_SATA) {
-            //BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
-            //                        0, 0, 0x0c00);
-            BaseMemAddress = NULL; // HACK-HACK
-            if(!BaseMemAddress) {
-                KdPrint2((PRINT_PREFIX "Intel: no SATA I/O space, operate in PATA Compatible mode\n"));
-                deviceExtension->HwFlags &= ~UNIATA_SATA;
-                break;
-            }
-            if((*ConfigInfo->AccessRanges)[0].RangeInMemory) {
+
+            /* if BAR(5) is IO it should point to SATA interface registers */
+            BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
+                                    5, 0, 0x10);
+            if(BaseMemAddress && (*ConfigInfo->AccessRanges)[5].RangeInMemory) {
                 KdPrint2((PRINT_PREFIX "MemIo\n"));
                 MemIo = TRUE;
             }
             deviceExtension->BaseIoAddressSATA_0.Addr  = BaseMemAddress;
             deviceExtension->BaseIoAddressSATA_0.MemIo = MemIo;
-        }
-#endif
+
+            for(c=0; c<deviceExtension->NumberChannels; c++) {
+                chan = &deviceExtension->chan[c];
+                IsPata = FALSE;
+                if(ChipFlags & ICH5) {
+                    if ((tmp8 & 0x04) == 0) {
+                        //ch->flags |= ATA_SATA;
+                        //ch->flags |= ATA_NO_SLAVE;
+                        //smap[0] = (map & 0x01) ^ ch->unit;
+                        //smap[1] = 0;
+                        chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
+                        chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ^ c;
+                        chan->lun[1]->SATA_lun_map = 0;
+                    } else if ((tmp8 & 0x02) == 0) {
+                               //ch->flags |= ATA_SATA;
+                               //smap[0] = (map & 0x01) ? 1 : 0;
+                               //smap[1] = (map & 0x01) ? 0 : 1;
+                        if(c == 0) {
+                            chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ? 1 : 0;
+                            chan->lun[1]->SATA_lun_map = (tmp8 & 0x01) ? 0 : 1;
+                        } else {
+                            IsPata = TRUE;
+                            //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
+                        }
+                    } else if ((tmp8 & 0x02) != 0) {
+                               //ch->flags |= ATA_SATA;
+                               //smap[0] = (map & 0x01) ? 1 : 0;
+                               //smap[1] = (map & 0x01) ? 0 : 1;
+                        if(c == 1) {
+                            chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ? 1 : 0;
+                            chan->lun[1]->SATA_lun_map = (tmp8 & 0x01) ? 0 : 1;
+                        } else {
+                            IsPata = TRUE;
+                            //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
+                        }
+                    }
+                } else
+                if(ChipFlags & I6CH2) {
+                    chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
+                    chan->lun[0]->SATA_lun_map = c ? 4 : 5;
+                    chan->lun[1]->SATA_lun_map = 0;
+                } else {
+                    switch(tmp8 & 0x03) {
+                    case 0:
+                        chan->lun[0]->SATA_lun_map = 0+c;
+                        chan->lun[1]->SATA_lun_map = 2+c;
+                        break;
+                    case 2:
+                        if(c==0) {
+                            chan->lun[0]->SATA_lun_map = 0;
+                            chan->lun[1]->SATA_lun_map = 2;
+                        } else {
+                            // PATA
+                            IsPata = TRUE;
+                        }
+                        break;
+                    case 1:
+                        if(c==1) {
+                            chan->lun[0]->SATA_lun_map = 1;
+                            chan->lun[1]->SATA_lun_map = 3;
+                        } else {
+                            // PATA
+                            IsPata = TRUE;
+                        }
+                        break;
+                    }
+                }
+
+                if(IsPata) {
+                    chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
+                } else {
+
+                    if((ChipFlags & ICH5) && BaseMemAddress) {
+                        chan->RegTranslation[IDX_INDEXED_ADDR].Addr        = BaseMemAddress + 0;
+                        chan->RegTranslation[IDX_INDEXED_ADDR].MemIo       = MemIo;
+                        chan->RegTranslation[IDX_INDEXED_DATA].Addr        = BaseMemAddress + 4;
+                        chan->RegTranslation[IDX_INDEXED_DATA].MemIo       = MemIo;
+                    }
+                    if((ChipFlags & ICH5) || BaseMemAddress) {
+
+                        // Rather interesting way of register access...
+                        ChipType = INTEL_IDX;
+                        deviceExtension->HwFlags &= ~CHIPTYPE_MASK;
+                        deviceExtension->HwFlags |= ChipType;
+
+                        chan->RegTranslation[IDX_SATA_SStatus].Addr        = 0x200*c + 0;
+                        chan->RegTranslation[IDX_SATA_SStatus].Proc        = 1;
+                        chan->RegTranslation[IDX_SATA_SError].Addr         = 0x200*c + 2;
+                        chan->RegTranslation[IDX_SATA_SError].Proc         = 1;
+                        chan->RegTranslation[IDX_SATA_SControl].Addr       = 0x200*c + 1;
+                        chan->RegTranslation[IDX_SATA_SControl].Proc       = 1;
+                    }
+                }
+
+            } // end for()
+
+            // rest of INIT staff is in AtapiChipInit()
+
+        } // ATA_SA150
         break; }
-    case 0x1078:
+    case ATA_CYRIX_ID:
         /* Cyrix 5530 ATA33 controller */
-        if(deviceExtension->DevID == 0x01021078) {
+        if(deviceExtension->DevID == 0x01021078) { 
             ConfigInfo->AlignmentMask = 0x0f;
             deviceExtension->MaximumDmaTransferLength = 63*1024;
         }
         break;
     }
 
-    return TRUE;
+    if(ChipFlags & UNIATA_AHCI) {
+        return UniataAhciInit(HwDeviceExtension) ? STATUS_SUCCESS : STATUS_UNSUCCESSFUL;
+    }
+
+    return STATUS_SUCCESS;
 
 } // end UniataChipDetect()
 
@@ -1023,7 +1202,7 @@ AtapiRosbSouthBridgeFixup(
         DeviceID  = pciData.DeviceID;
         dev_id = (VendorID | (DeviceID << 16));
 
-        if (dev_id == ATA_ROSB4_ISA) {         /* VIA VT8361 */
+        if (dev_id == ATA_ROSB4_ISA) {         /*  */
             ChangePciConfig4(0x64, ((a & ~0x00002000) | 0x00004000));
             break;
         }
@@ -1404,11 +1583,13 @@ AtapiChipInit(
             if(c == CHAN_NOT_SPECIFIED) {
                 /* use device interrupt as byte count end */
                 ChangePciConfig1(0x4a, (a | 0x20));
-                /* enable cable detection and UDMA support on newer chips */
-                ChangePciConfig1(0x4b, (a | 0x09));
+                /* enable cable detection and UDMA support on newer chips, rev < 0xc7 */
+                if(RevID < 0xc7) {
+                    ChangePciConfig1(0x4b, (a | 0x09));
+                }
 
                 /* enable ATAPI UDMA mode */
-                ChangePciConfig1(0x53, (a | 0x01));
+                ChangePciConfig1(0x53, (a | (RevID >= 0xc7 ? 0x03 : 0x01)));
 
             } else {
                 // check 80-pin cable
@@ -1476,32 +1657,26 @@ AtapiChipInit(
     case ATA_INTEL_ID: {
         USHORT reg54;
         if(ChipFlags & UNIATA_SATA) {
-            if(c != CHAN_NOT_SPECIFIED)
+
+            if(ChipFlags & UNIATA_AHCI)
                 break;
-#if 0
-            /* force all ports active "the legacy way" */
-            ChangePciConfig2(0x92, (a | 0x0f));
-            /* enable PCI interrupt */
-            ChangePciConfig2(/*PCIR_COMMAND*/0x04, (a & ~0x0400));
-
-            if(!(ChipFlags & UNIATA_AHCI)) {
-                /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
-                GetPciConfig1(0x90, tmp8);
-                if(!(tmp8 & 0x04)) {
-                   /* XXX SOS should be in intel_allocate if we grow it */
-                    if(c == CHAN_NOT_SPECIFIED) {
-                        for(c=0; c<deviceExtension->NumberChannels; c++) {
-                            deviceExtension->chan[c].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
+            if(c == CHAN_NOT_SPECIFIED) {
+                /* force all ports active "the legacy way" */
+                ChangePciConfig2(0x92, (a | 0x0f));
+                /* enable PCI interrupt */
+                ChangePciConfig2(/*PCIR_COMMAND*/0x04, (a & ~0x0400));
+            } else {
+                if(ChipType == INTEL_IDX) {
+                    for(c=0; c<deviceExtension->NumberChannels; c++) {
+                        chan = &deviceExtension->chan[c];
+                        UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 0);
+                        if(!(chan->ChannelCtrlFlags & CTRFLAGS_NO_SLAVE)) {
+                            UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 1);
                         }
-                    } else {
-                        deviceExtension->chan[c].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
                     }
                 }
             }
-#else
-            /* enable PCI interrupt */
-            ChangePciConfig2(/*PCIR_COMMAND*/0x04, (a & ~0x0400));
-#endif
+
             break;
         }
         if(deviceExtension->MaxTransferMode < ATA_UDMA2)
@@ -1523,6 +1698,8 @@ AtapiChipInit(
                 ULONG offs = (ChipFlags & NV4OFF) ? 0x0440 : 0x0010;
                 /* enable control access */
                 ChangePciConfig1(0x50, (a | 0x04));
+                /* MCP55 seems to need some time to allow r_res2 read. */
+                AtapiStallExecution(10);
                 KdPrint2((PRINT_PREFIX "BaseIoAddressSATA_0=%x\n", deviceExtension->BaseIoAddressSATA_0.Addr));
                 if(ChipFlags & NVQ) {
                     /* clear interrupt status */
@@ -1803,13 +1980,16 @@ AtapiChipInit(
         break;
     case ATA_VIA_ID:
 
+/*        if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI | VIASATA) {
+            break;
+        }*/
         if(c == CHAN_NOT_SPECIFIED) {
             /* prepare for ATA-66 on the 82C686a and 82C596b */
             if(ChipFlags & VIACLK) {
                 ChangePciConfig4(0x50, (a | 0x030b030b));
             }
             // no init for SATA
-            if(ChipFlags & UNIATA_SATA) {
+            if(ChipFlags & (UNIATA_SATA | VIASATA)) {
                 /* enable PCI interrupt */
                 ChangePciConfig2(/*PCIR_COMMAND*/0x04, (a & ~0x0400));
                 break;
@@ -1838,8 +2018,18 @@ AtapiChipInit(
             SetPciConfig2(0x60, DEV_BSIZE);
             SetPciConfig2(0x68, DEV_BSIZE);
         } else {
-            // check 80-pin cable
+
             chan = &deviceExtension->chan[c];
+            // no init for SATA
+            if(ChipFlags & (UNIATA_SATA | VIASATA)) {
+                if((ChipFlags & VIABAR) && (c >= 2)) {
+                    break;
+                }
+                UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 0);
+                break;
+            }
+
+            // check 80-pin cable
             if(!via_cable80(deviceExtension, channel)) {
                 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
             }
@@ -1848,25 +2038,28 @@ AtapiChipInit(
         break;
 
     case ATA_ITE_ID:
-        // Old chip
-        if(ChipType == ITE_33)
+        if(ChipType == ITE_33 || ChipType == ITE_133_NEW) {
             break;
-        if(c == CHAN_NOT_SPECIFIED) {
-            /* set PCI mode and 66Mhz reference clock */
-            ChangePciConfig1(0x50, a & ~0x83);
+        }
+        if(ChipType == ITE_133) {
+            if(c == CHAN_NOT_SPECIFIED) {
+                /* set PCI mode and 66Mhz reference clock */
+                ChangePciConfig1(0x50, a & ~0x83);
 
-            /* set default active & recover timings */
-            SetPciConfig1(0x54, 0x31);
-            SetPciConfig1(0x56, 0x31);
-        } else {
-            // check 80-pin cable
-            GetPciConfig2(0x40, tmp16);
-            chan = &deviceExtension->chan[c];
-            if(!(tmp16 & (channel ? 0x08 : 0x04))) {
-                chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
+                /* set default active & recover timings */
+                SetPciConfig1(0x54, 0x31);
+                SetPciConfig1(0x56, 0x31);
+            } else {
+                // check 80-pin cable
+                GetPciConfig2(0x40, tmp16);
+                chan = &deviceExtension->chan[c];
+                if(!(tmp16 & (channel ? 0x08 : 0x04))) {
+                    chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
+                }
             }
+        } else
+        if(ChipType == ITE_133_NEW) {
         }
-
         break;
     default:
         if(c != CHAN_NOT_SPECIFIED) {
index f254236..2752b2a 100644 (file)
@@ -1,6 +1,6 @@
 /*++
 
-Copyright (c) 2002-2008 Alexandr A. Telyatnikov (Alter)
+Copyright (c) 2002-2010 Alexandr A. Telyatnikov (Alter)
 
 Module Name:
     id_probe.cpp
@@ -628,6 +628,8 @@ AtapiFindListedDev(
 
     ULONG i;
 
+    KdPrint2((PRINT_PREFIX "AtapiFindListedDev: lim=%x, Bus=%x, Slot=%x\n", lim, BusNumber, SlotNumber));
+
     // set start/end bus
     if(BusNumber == PCIBUSNUM_NOT_SPECIFIED) {
         busNumber  = 0;
@@ -646,6 +648,8 @@ AtapiFindListedDev(
     }
     slotData.u.AsULONG = 0;
 
+    KdPrint2((PRINT_PREFIX " scanning range Bus %x-%x, Slot %x-%x\n", busNumber, busNumber2-1, slotNumber, slotNumber2-1));
+
     for(            ; busNumber  < busNumber2       ; busNumber++ ) {
     for(            ; slotNumber < slotNumber2      ; slotNumber++) {
     for(funcNumber=0; funcNumber < PCI_MAX_FUNCTION ; funcNumber++) {
@@ -653,9 +657,9 @@ AtapiFindListedDev(
         slotData.u.bits.DeviceNumber   = slotNumber;
         slotData.u.bits.FunctionNumber = funcNumber;
 
-    busDataRead = HalGetBusData(
+        busDataRead = HalGetBusData(
             //ScsiPortGetBusData(HwDeviceExtension,
-                                    PCIConfiguration, busNumber, slotData.u.AsULONG,
+                                    PCIConfiguration, busNumber, slotData.u.AsULONG, 
                                     &pciData, PCI_COMMON_HDR_LENGTH);
         // no more buses (this should not happen)
         if(!busDataRead) {
@@ -667,11 +671,19 @@ AtapiFindListedDev(
 
         if(busDataRead < (ULONG)PCI_COMMON_HDR_LENGTH)
             continue;
-
+/*
+        KdPrint2((PRINT_PREFIX "AtapiFindListedDev: b:s:f(%x:%x:%x) %4.4x/%4.4x/%2.2x\n",
+                  busNumber, slotNumber, funcNumber,
+                  pciData.VendorID, pciData.DeviceID, pciData.RevisionID));
+                  */
         i = Ata_is_dev_listed(BusMasterAdapters, pciData.VendorID, pciData.DeviceID, pciData.RevisionID, lim);
         if(i != BMLIST_TERMINATOR) {
             if(_slotData)
                 *_slotData = slotData;
+            KdPrint2((PRINT_PREFIX "AtapiFindListedDev: found\n"));
+            KdPrint2((PRINT_PREFIX "AtapiFindListedDev: b:s:f(%x:%x:%x) %4.4x/%4.4x/%2.2x\n",
+                      busNumber, slotNumber, funcNumber,
+                      pciData.VendorID, pciData.DeviceID, pciData.RevisionID));
             return i;
         }
 
@@ -809,6 +821,8 @@ UniataAllocateLunExt(
     
     deviceExtension->chan = (PHW_CHANNEL)ExAllocatePool(NonPagedPool, sizeof(HW_CHANNEL) * (deviceExtension->NumberChannels+1));
     if (!deviceExtension->chan) {
+        ExFreePool(deviceExtension->lun);
+        deviceExtension->lun = NULL;
         KdPrint2((PRINT_PREFIX "!deviceExtension->chan => SP_RETURN_ERROR\n"));
         return FALSE;
     }
@@ -963,7 +977,6 @@ UniataFindBusMasterController(
         KdPrint2((PRINT_PREFIX "!deviceExtension => SP_RETURN_ERROR\n"));
         return SP_RETURN_ERROR;
     }
-
     RtlZeroMemory(deviceExtension, sizeof(HW_DEVICE_EXTENSION));
 
     vendorStrPtr = vendorString;
@@ -1044,10 +1057,21 @@ UniataFindBusMasterController(
 
     if(MasterDev) {
         KdPrint2((PRINT_PREFIX "MasterDev (1)\n"));
-        deviceExtension->NumberChannels = 1;
+        deviceExtension->MasterDev = TRUE;
     }
 
-    found = UniataChipDetect(HwDeviceExtension, &pciData, i, ConfigInfo, &simplexOnly);
+    status = UniataChipDetect(HwDeviceExtension, &pciData, i, ConfigInfo, &simplexOnly);
+    switch(status) {
+    case STATUS_SUCCESS:
+        found = TRUE;
+        break;
+    case STATUS_NOT_FOUND:
+        found = FALSE;
+        break;
+    default:
+        KdPrint2((PRINT_PREFIX "FAILED => SP_RETURN_ERROR\n"));
+        goto exit_error;
+    }
     KdPrint2((PRINT_PREFIX "ForceSimplex = %d\n", simplexOnly));
     KdPrint2((PRINT_PREFIX "HwFlags = %x\n (0)", deviceExtension->HwFlags));
     switch(dev_id) {
@@ -1241,7 +1265,7 @@ UniataFindBusMasterController(
         deviceExtension->UseDpc = FALSE;
     }
 
-    if(simplexOnly && MasterDev /*|| (WinVer_Id() > WinVer_NT)*/) {
+    if(simplexOnly && MasterDev) {
         if(deviceExtension->NumberChannels < 2) {
             KdPrint2((PRINT_PREFIX "set NumberChannels = 2\n"));
             deviceExtension->NumberChannels = 2;
@@ -1764,7 +1788,7 @@ UniataFindFakeBusMasterController(
 
     PIDE_BUSMASTER_REGISTERS BaseIoAddressBM_0 = NULL;
 
-//    NTSTATUS status;
+    NTSTATUS status;
     PPORT_CONFIGURATION_INFORMATION_COMMON _ConfigInfo =
         (PPORT_CONFIGURATION_INFORMATION_COMMON)ConfigInfo;
 
@@ -1791,7 +1815,6 @@ UniataFindFakeBusMasterController(
         KdPrint2((PRINT_PREFIX "!deviceExtension => SP_RETURN_ERROR\n"));
         return SP_RETURN_ERROR;
     }
-
     RtlZeroMemory(deviceExtension, sizeof(HW_DEVICE_EXTENSION));
 
     vendorStrPtr = vendorString;
@@ -1813,7 +1836,7 @@ UniataFindFakeBusMasterController(
                                      &pciData,
                                      PCI_COMMON_HDR_LENGTH);
 
-    if (busDataRead < (ULONG)PCI_COMMON_HDR_LENGTH) {
+    if (busDataRead < PCI_COMMON_HDR_LENGTH) {
         KdPrint2((PRINT_PREFIX "busDataRead < PCI_COMMON_HDR_LENGTH => SP_RETURN_ERROR\n"));
         goto exit_error;
     }
@@ -1877,7 +1900,18 @@ UniataFindFakeBusMasterController(
 
     ConfigInfo->AlignmentMask = 0x00000003;
 
-    found = UniataChipDetect(HwDeviceExtension, &pciData, i, ConfigInfo, &simplexOnly);
+    status = UniataChipDetect(HwDeviceExtension, &pciData, i, ConfigInfo, &simplexOnly);
+    switch(status) {
+    case STATUS_SUCCESS:
+        found = TRUE;
+        break;
+    case STATUS_NOT_FOUND:
+        found = FALSE;
+        break;
+    default:
+        KdPrint2((PRINT_PREFIX "FAILED => SP_RETURN_ERROR\n"));
+        goto exit_error;
+    }
     KdPrint2((PRINT_PREFIX "ForceSimplex = %d\n", simplexOnly));
     KdPrint2((PRINT_PREFIX "HwFlags = %x\n (0)", deviceExtension->HwFlags));
     switch(dev_id) {
@@ -2091,7 +2125,7 @@ UniataConnectIntr2(
 
     KdPrint2((PRINT_PREFIX "Create DO\n"));
 
-    devname.Length =
+    devname.Length = 
         _snwprintf(devname_str, sizeof(devname_str)/sizeof(WCHAR),
               L"\\Device\\uniata%d_2ch", i);
     devname.Length *= sizeof(WCHAR);
@@ -2686,7 +2720,7 @@ UniataAnybodyHome(
         }
     } else {
 
-        SStatus.Reg = AtapiReadPort4(chan, IDX_SATA_SStatus);
+        SStatus.Reg = UniataSataReadPort4(chan, IDX_SATA_SStatus, deviceNumber);
         KdPrint2((PRINT_PREFIX "SStatus %x\n", SStatus.Reg));
         if(SStatus.DET <= SStatus_DET_Dev_NoPhy) {
             KdPrint2((PRINT_PREFIX "  SATA DET <= SStatus_DET_Dev_NoPhy\n"));
@@ -2772,7 +2806,7 @@ CheckDevice(
         //if(deviceExtension->HwFlags & UNIATA_SATA) {
             KdPrint2((PRINT_PREFIX
                         "CheckDevice: try enable SATA Phy\n"));
-            statusByte = UniataSataPhyEnable(HwDeviceExtension, lChannel);
+            statusByte = UniataSataPhyEnable(HwDeviceExtension, lChannel, deviceNumber);
             if(statusByte == 0xff) {
                 KdPrint2((PRINT_PREFIX "CheckDevice: status %#x (no dev)\n", statusByte));
                 UniataForgetDevice(LunExt);
@@ -2791,7 +2825,7 @@ CheckDevice(
 
     GetBaseStatus(chan, statusByte);
     if(deviceExtension->HwFlags & UNIATA_SATA) {
-        UniataSataClearErr(HwDeviceExtension, lChannel, UNIATA_SATA_IGNORE_CONNECT);
+        UniataSataClearErr(HwDeviceExtension, lChannel, UNIATA_SATA_IGNORE_CONNECT, deviceNumber);
     }
 
     KdPrint2((PRINT_PREFIX "CheckDevice: status %#x\n", statusByte));
index 1f791e7..4753eb3 100644 (file)
@@ -1,3 +1,36 @@
+/*++
+
+Copyright (c) 2008-2010 Alexandr A. Telyatnikov (Alter)
+
+Module Name:
+    id_probe.cpp
+
+Abstract:
+    This module handles comamnd queue reordering and channel load balance
+
+Author:
+    Alexander A. Telyatnikov (Alter)
+
+Environment:
+    kernel mode only
+
+Notes:
+
+    THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+    IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+    OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+    IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+    INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+    NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+    DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+    THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+    THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Revision History:
+
+--*/
+
 #include "stdafx.h"
 
 /*
index b067961..c6dd47d 100644 (file)
@@ -1,10 +1,44 @@
+/*++
+
+Copyright (c) 2008-2010 Alexandr A. Telyatnikov (Alter)
+
+Module Name:
+    id_probe.cpp
+
+Abstract:
+    This module handles SATA-related staff
+
+Author:
+    Alexander A. Telyatnikov (Alter)
+
+Environment:
+    kernel mode only
+
+Notes:
+
+    THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+    IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+    OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+    IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+    INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+    NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+    DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+    THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+    THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Revision History:
+
+--*/
+
 #include "stdafx.h"
 
 UCHAR
 NTAPI
 UniataSataConnect(
     IN PVOID HwDeviceExtension,
-    IN ULONG lChannel          // logical channel
+    IN ULONG lChannel,          // logical channel
+    IN ULONG pm_port /* for port multipliers */
     )
 {
     PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
@@ -26,11 +60,11 @@ UniataSataConnect(
     }
 
     /* clear SATA error register, some controllers need this */
-    AtapiWritePort4(chan, IDX_SATA_SError,
-        AtapiReadPort4(chan, IDX_SATA_SError));
+    UniataSataWritePort4(chan, IDX_SATA_SError,
+        UniataSataReadPort4(chan, IDX_SATA_SError, pm_port), pm_port);
     /* wait up to 1 second for "connect well" */
     for(i=0; i<100; i++) {
-        SStatus.Reg = AtapiReadPort4(chan, IDX_SATA_SStatus);
+        SStatus.Reg = UniataSataReadPort4(chan, IDX_SATA_SStatus, pm_port);
         if(SStatus.SPD == SStatus_SPD_Gen1 ||
            SStatus.SPD == SStatus_SPD_Gen2) {
             deviceExtension->lun[lChannel*2].TransferMode = ATA_SA150 + (UCHAR)(SStatus.SPD - 1);
@@ -43,8 +77,8 @@ UniataSataConnect(
         return 0xff;
     }
     /* clear SATA error register */
-    AtapiWritePort4(chan, IDX_SATA_SError,
-        AtapiReadPort4(chan, IDX_SATA_SError));
+    UniataSataWritePort4(chan, IDX_SATA_SError,
+        UniataSataReadPort4(chan, IDX_SATA_SError, pm_port), pm_port);
 
     Status = WaitOnBaseBusyLong(chan);
     if(Status & IDE_STATUS_BUSY) {
@@ -65,7 +99,8 @@ UCHAR
 NTAPI
 UniataSataPhyEnable(
     IN PVOID HwDeviceExtension,
-    IN ULONG lChannel          // logical channel
+    IN ULONG lChannel,          // logical channel
+    IN ULONG pm_port /* for port multipliers */
     )
 {
     PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
@@ -80,10 +115,10 @@ UniataSataPhyEnable(
         return IDE_STATUS_IDLE;
     }
 
-    SControl.Reg = AtapiReadPort4(chan, IDX_SATA_SControl);
+    SControl.Reg = UniataSataReadPort4(chan, IDX_SATA_SControl, pm_port);
     KdPrint2((PRINT_PREFIX "SControl %x\n", SControl.Reg));
     if(SControl.DET == SControl_DET_Idle) {
-        return UniataSataConnect(HwDeviceExtension, lChannel);
+        return UniataSataConnect(HwDeviceExtension, lChannel, pm_port);
     }
 
     for (retry = 0; retry < 10; retry++) {
@@ -91,9 +126,9 @@ UniataSataPhyEnable(
        for (loop = 0; loop < 10; loop++) {
            SControl.Reg = 0;
            SControl.DET = SControl_DET_Init;
-            AtapiWritePort4(chan, IDX_SATA_SControl, SControl.Reg);
+            UniataSataWritePort4(chan, IDX_SATA_SControl, SControl.Reg, pm_port);
             AtapiStallExecution(100);
-            SControl.Reg = AtapiReadPort4(chan, IDX_SATA_SControl);
+            SControl.Reg = UniataSataReadPort4(chan, IDX_SATA_SControl, pm_port);
             KdPrint2((PRINT_PREFIX "  SControl %8.8%x\n", SControl.Reg));
             if(SControl.DET == SControl_DET_Init) {
                break;
@@ -105,12 +140,12 @@ UniataSataPhyEnable(
            SControl.Reg = 0;
            SControl.DET = SControl_DET_DoNothing;
            SControl.IPM = SControl_IPM_NoPartialSlumber;
-            AtapiWritePort4(chan, IDX_SATA_SControl, SControl.Reg);
+            UniataSataWritePort4(chan, IDX_SATA_SControl, SControl.Reg, pm_port);
             AtapiStallExecution(100);
-            SControl.Reg = AtapiReadPort4(chan, IDX_SATA_SControl);
+            SControl.Reg = UniataSataReadPort4(chan, IDX_SATA_SControl, pm_port);
             KdPrint2((PRINT_PREFIX "  SControl %8.8%x\n", SControl.Reg));
             if(SControl.DET == SControl_DET_Idle) {
-                return UniataSataConnect(HwDeviceExtension, lChannel);
+                return UniataSataConnect(HwDeviceExtension, lChannel, pm_port);
            }
        }
     }
@@ -124,7 +159,8 @@ NTAPI
 UniataSataClearErr(
     IN PVOID HwDeviceExtension,
     IN ULONG lChannel,          // logical channel
-    IN BOOLEAN do_connect
+    IN BOOLEAN do_connect,
+    IN ULONG pm_port /* for port multipliers */
     )
 {
     PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
@@ -136,8 +172,8 @@ UniataSataClearErr(
     if(UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
     //if(ChipFlags & UNIATA_SATA) {
 
-        SStatus.Reg = AtapiReadPort4(chan, IDX_SATA_SStatus);
-        SError.Reg  = AtapiReadPort4(chan, IDX_SATA_SError); 
+        SStatus.Reg = UniataSataReadPort4(chan, IDX_SATA_SStatus, pm_port);
+        SError.Reg  = UniataSataReadPort4(chan, IDX_SATA_SError, pm_port); 
 
         if(SStatus.Reg) {
             KdPrint2((PRINT_PREFIX "  SStatus %x\n", SStatus.Reg));
@@ -145,16 +181,16 @@ UniataSataClearErr(
         if(SError.Reg) {
             KdPrint2((PRINT_PREFIX "  SError %x\n", SError.Reg));
             /* clear error bits/interrupt */
-            AtapiWritePort4(chan, IDX_SATA_SError, SError.Reg);
+            UniataSataWritePort4(chan, IDX_SATA_SError, SError.Reg, pm_port);
 
             if(do_connect) {
                 /* if we have a connection event deal with it */
                 if(SError.DIAG.N) {
                     KdPrint2((PRINT_PREFIX "  catch SATA connect/disconnect\n"));
                     if(SStatus.SPD >= SStatus_SPD_Gen1) {
-                        UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_ATTACH);
+                        UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_ATTACH, pm_port);
                     } else {
-                        UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_DETACH);
+                        UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_DETACH, pm_port);
                     }
                     return TRUE;
                 }
@@ -169,12 +205,13 @@ NTAPI
 UniataSataEvent(
     IN PVOID HwDeviceExtension,
     IN ULONG lChannel,          // logical channel
-    IN ULONG Action
+    IN ULONG Action,
+    IN ULONG pm_port /* for port multipliers */
     )
 {
     PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
     UCHAR Status;
-    ULONG ldev = lChannel*2;
+    ULONG ldev = lChannel*2 + (pm_port ? 1 : 0);
 
     if(!UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
         return FALSE;
@@ -183,12 +220,12 @@ UniataSataEvent(
     switch(Action) {
     case UNIATA_SATA_EVENT_ATTACH:
         KdPrint2((PRINT_PREFIX "  CONNECTED\n"));
-        Status = UniataSataConnect(HwDeviceExtension, lChannel);
+        Status = UniataSataConnect(HwDeviceExtension, lChannel, pm_port);
         KdPrint2((PRINT_PREFIX "  Status %x\n", Status));
         if(Status != IDE_STATUS_IDLE) {
             return FALSE;
         }
-        CheckDevice(HwDeviceExtension, lChannel, 0 /*dev*/, FALSE);
+        CheckDevice(HwDeviceExtension, lChannel, pm_port ? 1 : 0 /*dev*/, FALSE);
         return TRUE;
         break;
     case UNIATA_SATA_EVENT_DETACH:
@@ -200,6 +237,135 @@ UniataSataEvent(
     return FALSE;
 } // end UniataSataEvent()
 
+ULONG
+UniataSataReadPort4(
+    IN PHW_CHANNEL chan,
+    IN ULONG io_port_ndx,
+    IN ULONG pm_port /* for port multipliers */
+    )
+{
+    if(chan && (io_port_ndx < IDX_MAX_REG) &&
+       chan->RegTranslation[io_port_ndx].Proc) {
+
+        PHW_DEVICE_EXTENSION deviceExtension = chan->DeviceExtension;
+        PVOID HwDeviceExtension = (PVOID)deviceExtension;
+        ULONG slotNumber = deviceExtension->slotNumber;
+        ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
+        ULONG VendorID =  deviceExtension->DevID        & 0xffff;
+        ULONG offs;
+        ULONG p;
+
+        switch(VendorID) {
+        case ATA_INTEL_ID: {
+            p = pm_port ? 1 : 0;
+            if(deviceExtension->HwFlags & ICH5) {
+                offs = 0x50+chan->lun[p]->SATA_lun_map*0x10;
+                switch(io_port_ndx) {
+                case IDX_SATA_SStatus:
+                    offs += 0;
+                    break;
+                case IDX_SATA_SError:
+                    offs += 1*4;
+                    break;
+                case IDX_SATA_SControl:
+                    offs += 2*4;
+                    break;
+                default:
+                    return -1;
+                }
+                SetPciConfig4(0xa0, offs);
+                GetPciConfig4(0xa4, offs);
+                return offs;
+            } else {
+                offs = ((deviceExtension->Channel+chan->lChannel)*2+p) * 0x100;
+                switch(io_port_ndx) {
+                case IDX_SATA_SStatus:
+                    offs += 0;
+                    break;
+                case IDX_SATA_SControl:
+                    offs += 1;
+                    break;
+                case IDX_SATA_SError:
+                    offs += 2;
+                    break;
+                default:
+                    return -1;
+                }
+                AtapiWritePort4(chan, IDX_INDEXED_ADDR, offs);
+                return AtapiReadPort4(chan, IDX_INDEXED_DATA);
+            }
+        } // ATA_INTEL_ID
+        } // end switch(VendorID)
+        return -1;
+    }
+    return AtapiReadPort4(chan, io_port_ndx);
+} // end UniataSataReadPort4()
+
+VOID
+UniataSataWritePort4(
+    IN PHW_CHANNEL chan,
+    IN ULONG io_port_ndx,
+    IN ULONG data,
+    IN ULONG pm_port /* for port multipliers */
+    )
+{
+    if(chan && (io_port_ndx < IDX_MAX_REG) &&
+       chan->RegTranslation[io_port_ndx].Proc) {
+
+        PHW_DEVICE_EXTENSION deviceExtension = chan->DeviceExtension;
+        PVOID HwDeviceExtension = (PVOID)deviceExtension;
+        ULONG slotNumber = deviceExtension->slotNumber;
+        ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
+        ULONG VendorID =  deviceExtension->DevID        & 0xffff;
+        ULONG offs;
+        ULONG p;
+
+        switch(VendorID) {
+        case ATA_INTEL_ID: {
+            p = pm_port ? 1 : 0;
+            if(deviceExtension->HwFlags & ICH5) {
+                offs = 0x50+chan->lun[p]->SATA_lun_map*0x10;
+                switch(io_port_ndx) {
+                case IDX_SATA_SStatus:
+                    offs += 0;
+                    break;
+                case IDX_SATA_SError:
+                    offs += 1*4;
+                    break;
+                case IDX_SATA_SControl:
+                    offs += 2*4;
+                    break;
+                default:
+                    return;
+                }
+                SetPciConfig4(0xa0, offs);
+                SetPciConfig4(0xa4, data);
+                return;
+            } else {
+                offs = ((deviceExtension->Channel+chan->lChannel)*2+p) * 0x100;
+                switch(io_port_ndx) {
+                case IDX_SATA_SStatus:
+                    offs += 0;
+                    break;
+                case IDX_SATA_SControl:
+                    offs += 1;
+                    break;
+                case IDX_SATA_SError:
+                    offs += 2;
+                    break;
+                default:
+                    return;
+                }
+                AtapiWritePort4(chan, IDX_INDEXED_ADDR, offs);
+                AtapiWritePort4(chan, IDX_INDEXED_DATA, data);
+            }
+        } // ATA_INTEL_ID
+        } // end switch(VendorID)
+        return;
+    }
+    AtapiWritePort4(chan, io_port_ndx, data);
+} // end UniataSataWritePort4()
+
 BOOLEAN
 NTAPI
 UniataAhciInit(
@@ -316,7 +482,8 @@ UCHAR
 NTAPI
 UniataAhciStatus(
     IN PVOID HwDeviceExtension,
-    IN ULONG lChannel
+    IN ULONG lChannel,
+    IN ULONG DeviceNumber
     )
 {
     PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
@@ -451,4 +618,3 @@ UniataAhciSetupFIS(
     fis[19] = 0x00;
     return 20;
 } // end UniataAhciSetupFIS()
-
index 0471604..a53fee9 100644 (file)
@@ -5,14 +5,16 @@ UCHAR
 NTAPI
 UniataSataConnect(
     IN PVOID HwDeviceExtension,
-    IN ULONG lChannel          // logical channel
+    IN ULONG lChannel,          // logical channel
+    IN ULONG pm_port = 0 /* for port multipliers */
     );
 
 UCHAR
 NTAPI
 UniataSataPhyEnable(
     IN PVOID HwDeviceExtension,
-    IN ULONG lChannel          // logical channel
+    IN ULONG lChannel,          // logical channel
+    IN ULONG pm_port = 0 /* for port multipliers */
     );
 
 #define UNIATA_SATA_DO_CONNECT        TRUE
@@ -23,7 +25,8 @@ NTAPI
 UniataSataClearErr(
     IN PVOID HwDeviceExtension,
     IN ULONG lChannel,          // logical channel
-    IN BOOLEAN do_connect
+    IN BOOLEAN do_connect,
+    IN ULONG pm_port = 0 /* for port multipliers */
     );
 
 #define UNIATA_SATA_EVENT_ATTACH      0x01
@@ -34,7 +37,8 @@ NTAPI
 UniataSataEvent(
     IN PVOID HwDeviceExtension,
     IN ULONG lChannel,          // logical channel
-    IN ULONG Action
+    IN ULONG Action,
+    IN ULONG pm_port = 0 /* for port multipliers */
     );
 
 #define UniataIsSATARangeAvailable(deviceExtension, lChannel) \
@@ -42,6 +46,23 @@ UniataSataEvent(
       deviceExtension->BaseIoAHCI_0.Addr) && \
         (deviceExtension->chan[lChannel].RegTranslation[IDX_SATA_SStatus].Addr))
 
+ULONG
+NTAPI
+UniataSataReadPort4(
+    IN PHW_CHANNEL chan,
+    IN ULONG io_port_ndx,
+    IN ULONG pm_port=0 /* for port multipliers */
+    );
+
+VOID
+NTAPI
+UniataSataWritePort4(
+    IN PHW_CHANNEL chan,
+    IN ULONG io_port_ndx,
+    IN ULONG data,
+    IN ULONG pm_port=0 /* for port multipliers */
+    );
+
 BOOLEAN
 NTAPI
 UniataAhciInit(
@@ -52,7 +73,8 @@ UCHAR
 NTAPI
 UniataAhciStatus(
     IN PVOID HwDeviceExtension,
-    IN ULONG lChannel
+    IN ULONG lChannel,
+    IN ULONG DeviceNumber
     );
 
 ULONG
index 8553f0f..06297f2 100644 (file)
@@ -1,6 +1,6 @@
 #include "uniata_ver.h"
 
-#define VERSION                         0,39,6,0
+#define VERSION                         UNIATA_VER_DOT_COMMA
 #define VERSION_STR                     "0." UNIATA_VER_STR
 
 #define REACTOS_FILETYPE                VFT_DRV
@@ -12,7 +12,7 @@
 #define REACTOS_STR_FILE_VERSION        VERSION_STR
 #define REACTOS_STR_INTERNAL_NAME       "uniata.sys"
 #define REACTOS_STR_ORIGINAL_FILENAME   "uniata.sys"
-#define REACTOS_STR_LEGAL_COPYRIGHT     "Copyright 1999-2008 AlterWare, Copyright 2007 ReactOS Team"
+#define REACTOS_STR_LEGAL_COPYRIGHT     "Copyright 1999-" UNIATA_VER_YEAR_STR " AlterWare, Copyright 2010 ReactOS Team"
 #define REACTOS_STR_PRODUCT_NAME        "UniATA Driver for ReactOS"
 #define REACTOS_STR_PRODUCT_VERSION     VERSION_STR
 
index e17f576..eeab727 100644 (file)
@@ -123,6 +123,9 @@ int __cdecl CrNtstrcmp (
         const char * dst
         );
 
+#define strlen CrNtstrlen
+#define strcmp CrNtstrcmp
+
 #endif //_DEBUG
 
 #define CROSSNT_DECL_API
index 6d231b4..b6d6395 100644 (file)
@@ -170,9 +170,9 @@ typedef union _CDB {
                 UCHAR Reserved : 4;
             } Fields;
         } Byte2;
-
+         
         UCHAR Reserved2[3];
-        UCHAR Start_TrackSes;
+        UCHAR Start_TrackSes;;
         UCHAR AllocationLength[2];
         UCHAR Control : 6;
         UCHAR Format : 2;
@@ -531,7 +531,7 @@ typedef union _CDB {
         } Byte2;
         UCHAR Reserved1 [2];
         UCHAR TrackNum;
-        UCHAR Reserved2 [6];
+        UCHAR Reserved2 [6];  
 
     } CLOSE_TRACK_SESSION, *PCLOSE_TRACK_SESSION;
 
@@ -1519,7 +1519,7 @@ typedef PREAD_TOC_FULL_TOC  PREAD_TOC_PMA;
 typedef struct _READ_TOC_ATIP {
     UCHAR Length[2];
     UCHAR Reserved[2];
-
+    
 #define ATIP_SpeedRef_Mask  0x07
 #define ATIP_SpeedRef_2X    0x01
 #define ATIP_WritingPower_Mask  0x07
@@ -1930,8 +1930,8 @@ typedef struct _EVENT_STAT_DEV_BUSY_BLOCK {
 
 // Define mode disc info block.
 
-typedef struct _DISC_INFO_BLOCK {        //
-    UCHAR DataLength [2];
+typedef struct _DISC_INFO_BLOCK {        // 
+    UCHAR DataLength [2];        
 
 #define DiscInfo_Disk_Mask          0x03
 #define DiscInfo_Disk_Empty         0x00
@@ -1994,7 +1994,7 @@ typedef struct _DISC_INFO_BLOCK {        //
 // Define track info block.
 
 typedef struct _TRACK_INFO_BLOCK {
-    UCHAR DataLength [2];
+    UCHAR DataLength [2];        
     UCHAR TrackNum;
     UCHAR SesNum;
     UCHAR Reserved0;
@@ -2264,7 +2264,7 @@ typedef struct _MODE_WRITE_PARAMS_PAGE {        // 0x05
     } Byte4;
 
     UCHAR LinkSize;
-    UCHAR Reserved3;
+    UCHAR Reserved3;    
 
     union {
         UCHAR Flags;
@@ -2370,7 +2370,7 @@ typedef struct _MODE_CD_PARAMS_PAGE {         // 0x0D
     UCHAR PageCode : 6;
     UCHAR Reserved : 1;
     UCHAR PageSavable : 1;
-
+    
     UCHAR PageLength;                       // 0x06
     UCHAR Reserved1;
 
@@ -2409,7 +2409,7 @@ typedef struct _MODE_CD_AUDIO_CONTROL_PAGE {         // 0x0E
     UCHAR PageCode : 6;
     UCHAR Reserved1: 1;
     UCHAR PageSavable : 1;
-
+    
     UCHAR PageLength;                       // 0x0E
 
 #define CdAudio_SOTC        0x02
@@ -2438,7 +2438,7 @@ typedef struct _MODE_POWER_CONDITION_PAGE {         // 0x1A
     UCHAR PageCode : 6;
     UCHAR Reserved1: 1;
     UCHAR PageSavable : 1;
-
+    
     UCHAR PageLength;                       // 0x0A
     UCHAR Reserved2;
 
@@ -2465,7 +2465,7 @@ typedef struct _MODE_FAIL_REPORT_PAGE {         // 0x1C
     UCHAR PageCode : 6;
     UCHAR Reserved1: 1;
     UCHAR PageSavable : 1;
-
+    
     UCHAR PageLength;                       // 0x0A
 
 #define FailReport_LogErr       0x01
@@ -2504,7 +2504,7 @@ typedef struct _MODE_TIMEOUT_AND_PROTECT_PAGE {         // 0x1D
     UCHAR PageCode : 6;
     UCHAR Reserved1: 1;
     UCHAR PageSavable : 1;
-
+    
     UCHAR PageLength;                       // 0x08
 
     UCHAR Reserved2[2];
@@ -2567,31 +2567,31 @@ typedef struct _MODE_CAPABILITIES_PAGE2 {   // 0x2A
 
     UCHAR PageLength;
 
-#define DevCap_read_cd_r          0x01 // reserved in 1.2
-#define DevCap_read_cd_rw         0x02 // reserved in 1.2
+#define DevCap_read_cd_r          0x01 // reserved in 1.2 
+#define DevCap_read_cd_rw         0x02 // reserved in 1.2 
 #define DevCap_method2            0x04
 #define DevCap_read_dvd_rom       0x08
 #define DevCap_read_dvd_r         0x10
 #define DevCap_read_dvd_ram       0x20
 
     UCHAR ReadCap;            // DevCap_*_read
-/*    UCHAR cd_r_read         : 1; // reserved in 1.2
-    UCHAR cd_rw_read        : 1; // reserved in 1.2
+/*    UCHAR cd_r_read         : 1; // reserved in 1.2 
+    UCHAR cd_rw_read        : 1; // reserved in 1.2 
     UCHAR method2           : 1;
     UCHAR dvd_rom           : 1;
     UCHAR dvd_r_read        : 1;
     UCHAR dvd_ram_read      : 1;
     UCHAR Reserved2            : 2;*/
 
-#define DevCap_write_cd_r         0x01 // reserved in 1.2
-#define DevCap_write_cd_rw        0x02 // reserved in 1.2
+#define DevCap_write_cd_r         0x01 // reserved in 1.2 
+#define DevCap_write_cd_rw        0x02 // reserved in 1.2 
 #define DevCap_test_write         0x04
 #define DevCap_write_dvd_r        0x10
 #define DevCap_write_dvd_ram      0x20
 
     UCHAR WriteCap;            // DevCap_*_write
-/*    UCHAR cd_r_write        : 1; // reserved in 1.2
-    UCHAR cd_rw_write        : 1; // reserved in 1.2
+/*    UCHAR cd_r_write        : 1; // reserved in 1.2 
+    UCHAR cd_rw_write        : 1; // reserved in 1.2 
     UCHAR test_write        : 1;
     UCHAR reserved3a        : 1;
     UCHAR dvd_r_write       : 1;
@@ -2656,16 +2656,16 @@ typedef struct _MODE_CAPABILITIES_PAGE2 {   // 0x2A
 
 #define DevCap_separate_volume    0x01
 #define DevCap_separate_mute      0x02
-#define DevCap_disc_present       0x04          // reserved in 1.2
-#define DevCap_sw_slot_select     0x08          // reserved in 1.2
-#define DevCap_change_side_cap    0x10
+#define DevCap_disc_present       0x04          // reserved in 1.2 
+#define DevCap_sw_slot_select     0x08          // reserved in 1.2 
+#define DevCap_change_side_cap    0x10 
 #define DevCap_rw_leadin_read     0x20
 
     UCHAR Capabilities3;
 /*    UCHAR separate_volume   : 1;
     UCHAR separate_mute     : 1;
-    UCHAR disc_present      : 1;  // reserved in 1.2
-    UCHAR sss               : 1;  // reserved in 1.2
+    UCHAR disc_present      : 1;  // reserved in 1.2 
+    UCHAR sss               : 1;  // reserved in 1.2 
     UCHAR Reserved7         : 4;*/
 
     UCHAR MaximumSpeedSupported[2];
index 0932284..9c3e46f 100644 (file)
@@ -56,7 +56,7 @@ typedef struct _PORT_CONFIGURATION_INFORMATION {
     // well as level, such as internal buses.
     ULONG BusInterruptVector;
     KINTERRUPT_MODE InterruptMode;     // Interrupt mode (level-sensitive or edge-triggered)
-
+    
     ULONG MaximumTransferLength;       // Max bytes that can be transferred in a single SRB
     ULONG NumberOfPhysicalBreaks;      // Number of contiguous blocks of physical memory
     ULONG DmaChannel;                          // DMA channel for devices using system DMA
@@ -84,8 +84,8 @@ typedef struct _PORT_CONFIGURATION_INFORMATION {
     BOOLEAN MultipleRequestPerLu;      // Supports multiple requests per logical unit.
     BOOLEAN ReceiveEvent;                      // Support receive event function.
     BOOLEAN RealModeInitialized;       // Indicates the real-mode driver has initialized the card.
-
-    BOOLEAN BufferAccessScsiPortControlled; // Indicate that the miniport will not touch
+    
+    BOOLEAN BufferAccessScsiPortControlled; // Indicate that the miniport will not touch 
                                                                        // the data buffers directly.
     UCHAR   MaximumNumberOfTargets;    // Indicator for wide scsi.
     UCHAR   ReservedUchars[2];         // Ensure quadword alignment.
@@ -110,7 +110,7 @@ typedef struct _PORT_CONFIGURATION_INFORMATION_NT {
 } PORT_CONFIGURATION_INFORMATION_NT, *PPORT_CONFIGURATION_INFORMATION_NT;
 
 typedef struct _PORT_CONFIGURATION_INFORMATION_2K {
-    // Used to determine whether the system and/or the miniport support
+    // Used to determine whether the system and/or the miniport support 
     // 64-bit physical addresses.  See SCSI_DMA64_* flags below.
     UCHAR  Dma64BitAddresses;
     // Indicates that the miniport can accept a SRB_FUNCTION_RESET_DEVICE
@@ -141,9 +141,9 @@ typedef struct _PORT_CONFIGURATION_INFORMATION_COMMON {
 //
 
 //
-// Set by scsiport on entering HwFindAdapter if the system can support 64-bit
-// physical addresses.  The miniport can use this information before calling
-// ScsiPortGetUncachedExtension to modify the DeviceExtensionSize,
+// Set by scsiport on entering HwFindAdapter if the system can support 64-bit 
+// physical addresses.  The miniport can use this information before calling 
+// ScsiPortGetUncachedExtension to modify the DeviceExtensionSize, 
 // SpecificLuExtensionSize & SrbExtensionSize fields to account for the extra
 // size of the scatter gather list.
 //
@@ -152,7 +152,7 @@ typedef struct _PORT_CONFIGURATION_INFORMATION_COMMON {
 
 //
 // Set by the miniport before calling ScsiPortGetUncachedExtension to indicate
-// that scsiport should provide it with 64-bit physical addresses.  If the
+// that scsiport should provide it with 64-bit physical addresses.  If the 
 // system does not support 64-bit PA's then this bit will be ignored.
 //
 
@@ -363,9 +363,9 @@ typedef struct _SCSI_WMI_REQUEST_BLOCK {
 #define SRB_STATUS_INTERNAL_ERROR           0x30
 
 //
-// Srb status values 0x38 through 0x3f are reserved for internal port driver
+// Srb status values 0x38 through 0x3f are reserved for internal port driver 
 // use.
-//
+// 
 
 
 
@@ -566,7 +566,7 @@ typedef struct _HW_INITIALIZATION_DATA {
     ULONG SrbExtensionSize;
     ULONG NumberOfAccessRanges;
     PVOID Reserved;
-
+    
     BOOLEAN MapBuffers;                                // Data buffers must be mapped into virtual address space.
     BOOLEAN NeedPhysicalAddresses;     // We need to tranlate virtual to physical addresses.
     BOOLEAN TaggedQueuing;                     // Supports tagged queuing
diff --git a/reactos/drivers/storage/ide/uniata/todo.txt b/reactos/drivers/storage/ide/uniata/todo.txt
new file mode 100644 (file)
index 0000000..1674c2f
--- /dev/null
@@ -0,0 +1,254 @@
+1.  use ScsiPortGetBusData() instead of HalGetBusData() to enumerate    ...
+    PCI devices                                                        (8b )
+2.  create 2 channels on non-primary HBA                               (9  )
+3.  add BusMaster detection to ISA & ISA/PCI FindController() routines  ...
+    I've decided to modify AtapiFindBusMasterController() for this      ...
+    purpose                                                            (9  )
+4.  beautify sources ;)
+5.  add LBA support                                                    (8  )
+6.  return modified Cylinders in IDENTYFY_DATA to handle HDDs > 8Gb     ...
+    properly                                                           (8  )
+7.  return good HDD size value for                                      ...
+    a) IdeVerify()                                                     (8  )
+    b) SCSIOP_READ_CAPACITY                                            (8  )
+8.  use READ_NATIVE_SIZE command to determine actual drive capacity    (8a )
+9.  send FLUSH command to device                                       (9  )
+10. check (IO_WDx - 0x08) ports in AtapiFindBusMasterController()      (+++)
+11. use SelectDrive() instead of ScsiPortWritePortXXX()                (9a )
+12. remove obsolete AtapiFindPCIController()                           (9a )
+13. make a separate routine AtapiInitController() for HBA               ...
+    initialization (move there some parts of code from                  ...
+    AtapiFindBusMasterController()                                     (---)
+14. add feature enabling code to drive (re)init routine IdeHardReset()  ...
+    AtapiHwInitialize() does all necessary staff                       (10+)
+15, use AtapiInitController() in AtapiHwInitialize()                   (---)
+16. remove obsolete FindBrokenController() and                          ...
+    AtapiFindNativeModeController()                                    (10 )
+17. move FindDevices() to id_probe.cpp                                 (10 )
+18. set HDD PIO modes if no DMA available                              (10 )
+19. implement AtaCommand()                                             (10 )
+20. implement AtaPioMode() & AtaPio2Mode()                             (10 )
+21. add some new ChipSets support from FBSD 4.5                        (10a)
+22. set Controller PIO timigs                                           ...
+    a) via                                                             (11 ) ??
+    b) intel                                                           (+++)
+    c) AcerLabs Aladdin IV/V                                           (23 )
+23. update Identify block                                              (11 )
+24. add LBA-48 support                                                 (11 )
+25. use AtapiCommand()/AtapiCommand48() instead of direct port I/O      ...
+    a) for Read/Write/Identify                                         (11 )
+    b) Set features, Smart, Set drive params                           (11c)
+26. port/implement AtapiDmaInit() for well-known controllers           (11 )
+27. Beautify IdeReadWrite()                                            (11c)
+28. port/implement DMA-specific parts of interrupt handlers            (12 )
+29. request queueing                                                   (16b)
+30. port/implement DMA-start routine                                   (12 )
+31. remove MODE_SENSE/SELECT 6<->10 translation. It'll improve          ...
+    performance.                                                       (11a)
+32. move InterruptService to DPC (via ScsiPortNotification())          (17 )
+33. implement ATA_WAIT_INTR branch in AtapiCommand()/AtapiCommand48()  (11b)
+34. fix bugs in Identify structure                                     (11b)
+35. use normal Lba detection in IssueIdentify()                        (11b)
+36. fix bug with default structure elements alignment                   ...
+    use pragma pack (1)                                                (11c)
+37. use ATA_WAIT_INTR in IdeReadWrite() for Write branch and            ...
+    ATA_IMMEDIATE for Read one                                         (11c)
+38. update Identify dtructure                                          (11c)
+39. fix some size detection bugs in IssueIdentify()                    (11c)
+40. don't forget setting ExpectingInterrupt flag before WriteBuffer()   ...
+    on PIO transfer                                                    (12g)
+41. try generic DMA for old devices instead of PIO default             (12g)
+42. clear 4 lower bits of AccessRange                                  (12g)
+43. reconstruct _Original_ ConfigInfo (not temporary) on Detect         ...
+    phase                                                              (13 )
+44. set 32-bit addressing for all bus types                            (13 )
+45. handle invalid address value (-1) in AtapiDmaSetup()               (13 )
+46. add some new ChipSets support from FBSD 4.6                        (13c)
+47. add 'offset' parameter to AtapiGetIoRange() to allow claiming       ...
+    different io-regions of the same PCI device by different            ...
+    DeviceObjects (representing different channels of this device      (13a)
+48. claim both BusMaster io-regions on SimplexOnly controllers         (+++)
+49. add ATAPI DMA support                                              (19 )
+50. read 'PSS ID Number: Q133706' in NT DDK & implement Registry-       ...
+    supplied params. Use a small hack instead: Argument2 is the         ...
+    pointer to UNICODE_STRING we need                                  (18a)
+51. implement Reinitialize functionality                               (+++)
+52. optimize DMA init (move similar parts of code to loops/functions    ...
+    a) VIA/AMD/nVidia                                                  (13c)
+    b) Promise TX2                                                     (13c)
+    c) Promise Ultra                                                   (23 )
+    d) ServerWorks                                                     (23 )
+    e) CMD 64x                                                         (+++)
+    f) SiS                                                             (+++)
+    g) AcerLabs Aladdin IV/V                                           (+++)
+    h) Intel                                                           (+++)
+    i) Sil                                                             (23 )
+    j) HPT                                                             (23 )
+53. use LogicalUnitExtension instead of xxx[Srb->TargetId]             (14 )
+54. use SrbExtension to manage queue                                   (16b)
+55. IdeReadWrite() should support non-zero initial offset in DataBuffer ...
+    to allow scatter/gather simulation, queueing & retries
+56. keep 'dma_tab' in SrbExtension                                     (16b)
+57. never set SpecificLuExtensionSize to 0                             (14a)
+58. never call ScsiPortGetUncachedExtension() twice for the same HBA,   ...
+    even if the 1st call failed. Use deviceExtension->HbaCtrlFlags &    ...
+    HBAFLAGS_DMA_DISABLED to indicate such case                        (16 )
+59. set deviceExtension->BaseIoAddressBM[1] properly for dual-channel   ...
+    HBAs (it was equal to BaseIoAddressBM[0])                          (16 )
+60. set Channel properly in AtapiInterrupt__() for dual-channel HBAs    ...
+    (lChannel was ignored)                                             (16 )
+61. initialize ConfigINfo members required by                           ...
+    ScsiPortGetUncachedExtension() _before_ call to AtapiDmaAlloc()    (16 )
+62. move SCSI-address-2-Channel/Device translation to macros. This      ...
+    makes code more readable & flexible.                               (16 )
+63. implement SCSI-bus - IDE-channel and                                ...
+    SCSI-TargetId - IDE-master/slave correspondance (using p.62)       (16 )
+64. set AutoRequestSense to TRUE                                       (16a)
+65. set inquiryData->CommandQueue to 1                                 (16a)
+66. fill SenseInfoBufer in                                              ...
+    a) IDE MapError()                                                  (16a)
+    b) IDE/ATAPI success                                               (20d)
+67. use AtaReq->ReqState to indicate request processing state          (16b)
+68. fill AtaReq->ReqState in all necessary places to reflect actual     ...
+    request state (for optimizer)                                      (18+)
+69. fix bug with unconditional returning FALSE in AtapiInterrupt()     (16c)
+70. copy pointer to original AtaReq from Srb to InternalSrb            (16c)
+71. check input Srb value for NULL in AtapiRemoveRequest()             (16c)
+72. return from IssueIdentify loop if no error occured. Previous        ...
+    versions have a bug: SUCCESS status was ignored & this caused       ...
+    obsolet retries                                                    (16c)
+73. clear CTRFLAGS_INTR_DISABLED flag in AtapiEnableInterrupts_Xxx()   (17a)
+74. use Sync Object to manage access to request queue                  (---)
+75. remove AtapiEnableInterrupts_Xxx()-related code duplicates from     ...
+    AtapiInterrupt__()                                                 (17a)
+76. check calls to AtapiResetController() & related routines.           ...
+    See p. 80, 81                                                      (+++)
+77. use ScsiPortNotification() with RequestTimerCall instead of         ...
+    CallDis(En)ableInterrupts to allow servicing 2 channels in          ...
+    parallel. See p.87                                                 (---)
+78. do not use DPC ISR for fast operations, like                        ...
+    a) DMA-completion                                                  (18 )
+    b) sending CDB to ATAPI devices                                    (18a)
+    c) short ATAPI transfers                                           (18a)
+79. call both AtapiEnableInterrupts_X() & AtapiCallBack_X() on DSC      ...
+    restrictive commands completion                                    (18 )
+80. invoke AtapiStartIo__() from ISR as callback to parform it's        ...
+    execution at lower IRQL                                            (19x)
+81. invoke AtapiResetController() from ISR as callback to parform it's  ...
+    execution at lower IRQL                                            (19x)
+82. do not use ScsiPortCompleteRequest() in AtapiResetController()      ...
+    Use standard completion way with setting SenseData instead         (18a)
+83. reset single channel on normal (non-simplex-only) controllers in    ...
+    AtapiResetController()                                             (18a)
+84. sort records in BMList on enumeration phase & simplify init loops   ...
+    in DriverEntry()                                                   (18a)
+85. fix bug with wrong numberChannels init for 2nd channel in           ...
+    AtapiResetController()                                             (18b)
+86. implement channel-sensetive AtapiHwInitialize__() and use in in     ...
+    AtapiResetController() & AtapiHwInitialize()                       (18+)
+87. Due to SCSI-port restrictions we should Enable/Disable interruptys  ...
+    for BOTH channels :((((. Implement this....                        (19 )
+88. Deprecate p.87. ;) It doesn't work. Solution: connect manually      ...
+    created DeviceObject to the same interrupt & check in its ISR if    ...
+    our device interrupted while original ISR/DPC processing            ...
+    another channel's interrupt.                                       (20 )
+90. add error handling on additional DevObj init                       (20a)
+91. deprecate p.80,81. We should acquire QueueSpinLock at DIRQL        (+/-)
+92. perform all possible request init on queueing stage even if we      ...
+    can't send it to device immediately (use CMD_ACTION_XXX)            ...
+    a) for IDE branch                                                  (20c)
+    b) for ATAPI branch                                                (21a)
+93. complete the following commands immediately:                        ...
+    SCSIOP_INQUIRY, SCSIOP_READ_CAPACITY, SCSIOP_REQUEST_SENSE         (20c)
+94. implement ABORT_COMMAND functionality                              (20d)
+95. reorder incoming requests in AtapiQueueRequest()                   (21c)
+96. make 2 modes for ResetController(): complete current & complete     ...
+    all for p.94.                                                      (20d)
+97. store queue size statistics in HW_CHANNEL                          (20d)
+98. remove obsolete DPC code from AtapiInterrupt__()                   (20e)
+99. store error rate in HW_CHANNEL                                     (20e)
+100.try falling back to PIO when DMA error occured                     (20e)
+101.use Dma & Pio error rates to distinguish between BadBlock &         ...
+    BadCable conditions, See also p.127, 128                           (+++)
+102.don't use HDD's algorithm of falling back to PIO for ATAPI         (21 )
+103.clear REQ_FLAG_DMA_OPERATION when falling back to PIO              (21 )
+104.set REQ_FLAG_REORDERABLE_CMD in IdeReadWrite()                     (21 )
+105.store bcount along with lba in ATA_REQ on CMD_ACTION_PREPARE stage (21 )
+106.do like p.105,104 in AtapiSendCommand for read/write ops           (21 )
+107.set operation type flag (Read/Write) in AtaReq on                   ...
+    CMD_ACTION_PREPARE stage                                           (21b)
+108.send comamnds to queue _after_ CMD_ACTION_PREPARE stage            (21a)
+109.fix bug (incorrect queue_size check) in p.108                      (21b)
+110.handle SRB_FLAGS_DISABLE_AUTOSENSE
+111.handle Srb->QueueAction                                            (21d)
+112.check SRB_STATUS_AUTOSENSE_VALID usage policy                      (+++)
+113.add support for hardware queueing/overlapped commands
+114.handle immediate commands properly: don't initiate bus reset        ...
+    while formatting CDRW                                              (+++)
+115.add hardware IDE RAID support
+116.fix bug with data type missmatch in AtapiDmaInit(),                 ...
+    some VIA branches. This bug caused array boundary cross, leading    ...
+    to system crash                                                    (22 )
+117.default udmamode to 0 if there are no well-known devices found      ...
+    in AtapiDmaInit(), VIA branch.                                     (22 )
+118.do not check RevID in AtapiFindDev if RevID == -1                  (22 )
+119.use best settings for newer RevIDs
+120.fix signed/unsigned missmatch (i vs udmamode) in AtapiDmaInit(),    ...
+    VIA branch                                                         (22 )
+121.fix bug with incorrect UDMA init in VIA branch. use UDMA0+i         ...
+    instead of UDMA0+udmamode                                          (22a)
+122.fall back to WDMA mode before PIO                                  (22a)
+123.use transfer speed slowdown algorithm when high error rate          ...
+    detected                                                           (22a)
+124.don't forget updating AtaReq->retry on R/W error (non-DMA)         (22a)
+125.fill AtaReq with ZEROs on TopLevel condition                       (22a)
+126.fix bug in IdeVerify() with sending SectorCount to device before    ...
+    call to AtaCommand48() and using 0 SectorCount in that call        (22a)
+127.store Error/Recover rate statistics in LunExtension                (22a)
+128.use p.127 for smart slowdown algorithm                             (22b)
+129.use lChannel  instead of phChannel for indexing in find-channel     ...
+    loop in AtapiFindBusMasterController()                             (22b)
+130.programm controller for lower speed in Ide/AtapiSendCommand(), not  ...
+    in AtapiInterrupt__()                                              (22b)
+131.use AtapiDmaReinit() routine for p.131                             (22b)
+132.implement per-device queueing                                      (23 )
+134.add Sil, ICH4, Some HPT, PromiseTX2(133) support from 4.7          (23 )
+135.fix wrong bit-shift bug in lba48 branch                            (23 )
+136.update and sort BusMasterAdapters[]                                (23a)
+137.fix bugs in AtapiTimerDpc() that caused incorrect handling of       ...
+    DSC restrictive commands                                            ...
+    a) call ScsiPortNotification(RequestTimerCall, ...) when we had     ...
+       a 2nd request on entry only                                     (23c)
+    b) check HwScsiTimer1 first to decide whether we have to go to      ...
+       GetNextDpc                                                      (23c)
+    c) wrong condition check 'time <= DpcTime1' instead of              ...
+       'time >= DpcTime1'                                              (23c)
+    d) remove request from queue _before_ call to HwScsiTimer()        (23c)
+138.add support for Acard controllers                                  (25 )
+139.use some additional code for HP/Promise Dma Star/Stop              (25 )
+140.assign queueing priority for each device
+141.assign BusMaster io-range to 1st channel only.                     (26e)
+142.do not change bus type to PCI for legacy ISA-PCI controllers under  ...
+    NT4                                                                (28 )
+143.implement Device/Vendor/Rev. filtering via registry keys           (30+)
+144.implement transfer mode control IOCTLs                             (28 )
+145.set max. transfer length > 64k.
+146.implement fix for miss-aligned user buffer
+147.set chip-specific init/operation flags only once during             ...
+    initialization and use them in future. Do not perform multiple      ...
+    bus scans and other detections.                                    (29a)
+148.fix bug with miss-functioning Enable/Disable interrupt for         (+++)
+    secondary channel                                                  (28 )
+149.add serial-ATA support                                             (29a)
+150.add support for new controllers (SiS, Promise)                     (29a)
+151.fix detection/init algorithms in order to avoid usage of            ...
+    non-generic code for unknown chips                                 (29a)
+152.add support for >2 channels                                        (29a)
+153.improve Intr-detection loop. Start each time from next channel      ...
+    for load-balance                                                   (29a)
+154.add support for machines with >4G physical memory                  (38 )
+155.add FreeBSD software RAID support
+156.use http://www.winimage.com/readfi15.zip for performance checks
+157.use IOCTL_SCSI_MINIPORT_IDENTIFY in atactl.exe to determine         ...
+    PIO/DMA when no uniata.sys is installed                            (+++)
+158.
index 8c55047..5cfcf46 100644 (file)
@@ -1,6 +1,6 @@
-#define UNIATA_VER_STR         "39j"
-#define UNIATA_VER_DOT         0.39.10.0
-#define UNIATA_VER_DOT_COMMA   0,39,10,0
-#define UNIATA_VER_DOT_STR     "0.39.10.0"
-#define UNIATA_VER_YEAR        2008
-#define UNIATA_VER_YEAR_STR    "2008"
+#define UNIATA_VER_STR         "40a1"
+#define UNIATA_VER_DOT         0.40.1.1
+#define UNIATA_VER_DOT_COMMA   0,40,1,1
+#define UNIATA_VER_DOT_STR     "0.40.1.1"
+#define UNIATA_VER_YEAR        2010
+#define UNIATA_VER_YEAR_STR    "2010"