return Value;
}
+FORCEINLINE
+ARM_LOCKDOWN_REGISTER
+KeArmLockdownRegisterGet(VOID)
+{
+ ARM_LOCKDOWN_REGISTER Value;
+ __asm__ __volatile__ ("mrc p15, 0, %0, c10, c0, 0" : "=r"(Value.AsUlong) : : "cc");
+ return Value;
+}
+
FORCEINLINE
ARM_CACHE_REGISTER
__asm__ __volatile__ ("mcr p15, 0, %0, c3, c0, 0" : : "r"(DomainRegister.AsUlong) : "cc");
}
+FORCEINLINE
+VOID
+KeArmLockdownRegisterSet(IN ARM_LOCKDOWN_REGISTER LockdownRegister)
+{
+ __asm__ __volatile__ ("mcr p15, 0, %0, c10, c0, 0" : : "r"(LockdownRegister.AsUlong) : "cc");
+}
+
+FORCEINLINE
+VOID
+KeArmFlushTlb(VOID)
+{
+ __asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 0" : : "r"(0) : "cc");
+}
+
+FORCEINLINE
+VOID
+KeArmInvalidateTlbEntry(IN PVOID Address)
+{
+ __asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 1" : : "r"(Address) : "cc");
+}
+
+
#endif
+//
+// CPSR Values
+//
.equ CPSR_IRQ_DISABLE, 0x80
.equ CPSR_FIQ_DISABLE, 0x40
.equ CPSR_THUMB_ENABLE, 0x20
+//
+// C1 Register Values
+//
.equ C1_MMU_CONTROL, 0x01
.equ C1_ALIGNMENT_CONTROL, 0x02
.equ C1_DCACHE_CONTROL, 0x04
.equ C1_ICACHE_CONTROL, 0x1000
.equ C1_VECTOR_CONTROL, 0x2000
+
+//
+// Loader Parameter Block Offsets
+//
+.equ LpbKernelStack, 0x18
+
+//
+// PCR
+//
+.equ KiPcr, 0xFFFFF000
+
+//
+// Lockdown TLB entries
+//
+.equ PCR_ENTRY 0
+.equ PDR_ENTRY 2
\ No newline at end of file
--- /dev/null
+/*
+ * PROJECT: ReactOS Kernel
+ * LICENSE: GPL - See COPYING in the top level directory
+ * FILE: ntoskrnl/ke/arm/kiinit.c
+ * PURPOSE: Implements the kernel entry point for ARM machines
+ * PROGRAMMERS: ReactOS Portable Systems Group
+ */
+
+/* INCLUDES *******************************************************************/
+
+#include <ntoskrnl.h>
+#define NDEBUG
+#include <debug.h>
+
+/* GLOBALS ********************************************************************/
+
+BOOLEAN KeIsArmV6;
+ULONG KeFixedTbEntries;
+ULONG KeNumberProcessIds;
+ULONG KeNumberTbEntries;
+
+#define __ARMV6__ KeIsArmV6
+
+/* FUNCTIONS ******************************************************************/
+
+VOID
+KiFlushSingleTb(IN BOOLEAN Invalid,
+ IN PVOID Virtual)
+{
+ //
+ // Just invalidate it
+ //
+ KeArmInvalidateTlbEntry(Virtual);
+}
+
+VOID
+KeFillFixedEntryTb(IN ARM_PTE Pte,
+ IN PVOID Virtual,
+ IN ULONG Index)
+{
+ ARM_LOCKDOWN_REGISTER LockdownRegister;
+ ULONG OldVictimCount;
+ ULONG Temp;
+ UNREFERENCED_PARAMETER(Pte);
+ UNREFERENCED_PARAMETER(Index);
+
+ //
+ // On ARM, we can't set the index ourselves, so make sure that we are not
+ // locking down more than 8 entries.
+ //
+ KeFixedTbEntries++;
+ ASSERT(KeFixedTbEntries <= 8);
+
+ //
+ // Flush the address
+ //
+ KiFlushSingleTb(TRUE, Virtual);
+
+ //
+ // Read lockdown register and set the preserve bit
+ //
+ LockdownRegister = KeArmLockdownRegisterGet();
+ LockdownRegister.Preserve = TRUE;
+ OldVictimCount = LockdownRegister.Victim;
+ KeArmLockdownRegisterSet(LockdownRegister);
+
+ //
+ // Now force a miss
+ //
+ Temp = *(PULONG)Virtual;
+
+ //
+ // Read lockdown register and clear the preserve bit
+ //
+ LockdownRegister = KeArmLockdownRegisterGet();
+ LockdownRegister.Preserve = FALSE;
+ ASSERT(LockdownRegister.Victim == OldVictimCount + 1);
+ KeArmLockdownRegisterSet(LockdownRegister);
+}
+
+VOID
+KeFlushTb(VOID)
+{
+ //
+ // Flush the entire TLB
+ //
+ KeArmFlushTlb();
+}
+
+VOID
+KiInitializeSystem(IN ULONG Magic,
+ IN PLOADER_PARAMETER_BLOCK LoaderBlock)
+{
+ //
+ // Detect ARM version (Architecture 6 is the ARMv5TE-J, go figure!)
+ //
+ KeIsArmV6 = KeArmIdCodeRegisterGet().Architecture == 7;
+
+ //
+ // Set the number of TLB entries and ASIDs
+ //
+ KeNumberTbEntries = 64;
+ if (__ARMV6__)
+ {
+ //
+ // 256 ASIDs on v6/v7
+ //
+ KeNumberProcessIds = 256;
+ }
+ else
+ {
+ //
+ // The TLB is VIVT on v4/v5
+ //
+ KeNumberProcessIds = 0;
+ }
+
+ //
+ // Flush the TLB
+ //
+ KeFlushTb();
+
+ //
+ //
+ //
+
+ while (TRUE);
+}