[NTOSKRNL]

- Add KiGetSecondLevelDCacheSize (for all the available architectures) and MiGetPdeOffset macros.
- Remove conflicting PDE_SIZE definitions (both aren't used anywhere).
- Fix ValidKernelPde, PointerPte and PointerPde types and correct their use (mminit.c).
- Thanks to the work that was done over the recent commits (in the header branch) and this one, the kernel now builds (but doesn't link yet) for ARM.

svn path=/branches/header-work/; revision=47258

diff --git a/ntoskrnl/include/internal/amd64/ke.h b/ntoskrnl/include/internal/amd64/ke.h
index 2e43edc..f661b20 100644 (file)
--- a/ntoskrnl/include/internal/amd64/ke.h
+++ b/ntoskrnl/include/internal/amd64/ke.h
@@ -116,6 +116,12 @@ extern ULONG KeI386CpuStep;
 #define KeGetContextSwitches(Prcb)  \
     (Prcb->KeContextSwitches)
 
+//
+// Macro to get the second level cache size field name which differs between
+// CISC and RISC architectures, as the former has unified I/D cache
+//
+#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelCacheSize
+
 #define KeGetExceptionFrame(Thread) \
     (PKEXCEPTION_FRAME)((ULONG_PTR)KeGetTrapFrame(Thread) - \
                         sizeof(KEXCEPTION_FRAME))

diff --git a/ntoskrnl/include/internal/amd64/mm.h b/ntoskrnl/include/internal/amd64/mm.h
index 6f0b2fd..515f729 100644 (file)
--- a/ntoskrnl/include/internal/amd64/mm.h
+++ b/ntoskrnl/include/internal/amd64/mm.h
@@ -112,6 +112,8 @@ MiIsPdeForAddressValid(PVOID Address)
 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
 #define ADDR_TO_PTE_OFFSET(v)  ((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE)
 
+#define MiGetPdeOffset ADDR_TO_PDE_OFFSET
+
 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)

diff --git a/ntoskrnl/include/internal/arm/ke.h b/ntoskrnl/include/internal/arm/ke.h
index 80fee0a..b5b8fe7 100644 (file)
--- a/ntoskrnl/include/internal/arm/ke.h
+++ b/ntoskrnl/include/internal/arm/ke.h
@@ -55,6 +55,12 @@
 #define KeGetContextSwitches(Prcb)  \
     CONTAINING_RECORD(Prcb, KIPCR, PrcbData)->ContextSwitches
 
+//
+// Macro to get the second level cache size field name which differs between
+// CISC and RISC architectures, as the former has unified I/D cache
+//
+#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelDcacheSize
+
 //
 // Returns the Interrupt State from a Trap Frame.
 // ON = TRUE, OFF = FALSE

diff --git a/ntoskrnl/include/internal/arm/mm.h b/ntoskrnl/include/internal/arm/mm.h
index 67eae35..03bb7bf 100644 (file)
--- a/ntoskrnl/include/internal/arm/mm.h
+++ b/ntoskrnl/include/internal/arm/mm.h
@@ -1,10 +1,6 @@
 #pragma once
 
-//
-// Number of bits corresponding to the area that a PDE entry represents (1MB)
-//
 #define PDE_SHIFT 20
-#define PDE_SIZE  (1 << PDE_SHIFT)
 
 //
 // Number of bits corresponding to the area that a coarse page table entry represents (4KB)

diff --git a/ntoskrnl/include/internal/i386/ke.h b/ntoskrnl/include/internal/i386/ke.h
index 701688e..8b50570 100644 (file)
--- a/ntoskrnl/include/internal/i386/ke.h
+++ b/ntoskrnl/include/internal/i386/ke.h
@@ -59,6 +59,12 @@
 #define KeGetContextSwitches(Prcb)  \
     CONTAINING_RECORD(Prcb, KIPCR, PrcbData)->ContextSwitches
 
+//
+// Macro to get the second level cache size field name which differs between
+// CISC and RISC architectures, as the former has unified I/D cache
+//
+#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelCacheSize
+
 //
 // Returns the Interrupt State from a Trap Frame.
 // ON = TRUE, OFF = FALSE

diff --git a/ntoskrnl/include/internal/i386/mm.h b/ntoskrnl/include/internal/i386/mm.h
index 7e768bb..3decd2c 100644 (file)
--- a/ntoskrnl/include/internal/i386/mm.h
+++ b/ntoskrnl/include/internal/i386/mm.h
@@ -36,6 +36,8 @@ PULONG MmGetPageDirectory(VOID);
 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
 #define ADDR_TO_PTE_OFFSET(v)  ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
 
+#define MiGetPdeOffset ADDR_TO_PDE_OFFSET
+
 /* Easy accessing PFN in PTE */
 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 

diff --git a/ntoskrnl/include/internal/powerpc/ke.h b/ntoskrnl/include/internal/powerpc/ke.h
index 87f48fd..ec19a3f 100644 (file)
--- a/ntoskrnl/include/internal/powerpc/ke.h
+++ b/ntoskrnl/include/internal/powerpc/ke.h
@@ -41,6 +41,12 @@ extern ULONG KePPCCacheAlignment;
 //#define KD_BREAKPOINT_SIZE
 //#define KD_BREAKPOINT_VALUE
 
+//
+// Macro to get the second level cache size field name which differs between
+// CISC and RISC architectures, as the former has unified I/D cache
+//
+#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelDcacheSize
+
 //
 // Macros for getting and setting special purpose registers in portable code
 //

diff --git a/ntoskrnl/mm/ARM3/miarm.h b/ntoskrnl/mm/ARM3/miarm.h
index 1ced65d..9808d16 100644 (file)
--- a/ntoskrnl/mm/ARM3/miarm.h
+++ b/ntoskrnl/mm/ARM3/miarm.h
@@ -42,8 +42,7 @@
 #define _1KB (1024)
 #define _1MB (1024 * _1KB)
 
-/* Size of a PDE directory, and size of a page table */
-#define PDE_SIZE (PDE_COUNT * sizeof(MMPDE))
+/* Size of a page table */
 #define PT_SIZE  (PTE_COUNT * sizeof(MMPTE))
 
 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
@@ -169,7 +168,7 @@ typedef struct _MMCOLOR_TABLES
 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 
 extern MMPTE HyperTemplatePte;
-extern MMPTE ValidKernelPde;
+extern MMPDE ValidKernelPde;
 extern MMPTE ValidKernelPte;
 
 extern ULONG MmSizeOfNonPagedPoolInBytes;

diff --git a/ntoskrnl/mm/ARM3/mminit.c b/ntoskrnl/mm/ARM3/mminit.c
index 89d082e..3e58951 100644 (file)
--- a/ntoskrnl/mm/ARM3/mminit.c
+++ b/ntoskrnl/mm/ARM3/mminit.c
@@ -314,13 +314,13 @@ MiSyncARM3WithROS(IN PVOID AddressStart,
     //
     // Puerile piece of junk-grade carbonized horseshit puss sold to the lowest bidder
     //
-    ULONG Pde = ADDR_TO_PDE_OFFSET(AddressStart);
-    while (Pde <= ADDR_TO_PDE_OFFSET(AddressEnd))
+    ULONG Pde = MiGetPdeOffset(AddressStart);
+    while (Pde <= MiGetPdeOffset(AddressEnd))
     {
         //
         // This both odious and heinous
         //
-        extern ULONG MmGlobalKernelPageDirectory[1024];
+        extern ULONG MmGlobalKernelPageDirectory[];
         MmGlobalKernelPageDirectory[Pde] = ((PULONG)PDE_BASE)[Pde];
         Pde++;
     }
@@ -360,10 +360,10 @@ MiComputeColorInformation(VOID)
     if (!MmSecondaryColors)
     {
         /* Get L2 cache information */
-        L2Associativity = KeGetPcr()->SecondLevelCacheAssociativity;
+        L2Associativity = KiGetSecondLevelDCacheSize();
         
         /* The number of colors is the number of cache bytes by set/way */
-        MmSecondaryColors = KeGetPcr()->SecondLevelCacheSize;
+        MmSecondaryColors = KiGetSecondLevelDCacheSize();
         if (L2Associativity) MmSecondaryColors /= L2Associativity;
     }
     
@@ -681,7 +681,7 @@ MiBuildPfnDatabaseFromPages(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
                 /* Yes we do, set it up */
                 Pfn1 = MI_PFN_TO_PFNENTRY(PageFrameIndex);
                 Pfn1->u4.PteFrame = StartupPdIndex;
-                Pfn1->PteAddress = PointerPde;
+                Pfn1->PteAddress = (PMMPTE)PointerPde;
                 Pfn1->u2.ShareCount++;
                 Pfn1->u3.e2.ReferenceCount = 1;
                 Pfn1->u3.e1.PageLocation = ActiveAndValid;
@@ -764,7 +764,7 @@ MiBuildPfnDatabaseZeroPage(VOID)
         /* Make it a bogus page to catch errors */
         PointerPde = MiAddressToPde(0xFFFFFFFF);
         Pfn1->u4.PteFrame = PFN_FROM_PTE(PointerPde);
-        Pfn1->PteAddress = PointerPde;
+        Pfn1->PteAddress = (PMMPTE)PointerPde;
         Pfn1->u2.ShareCount++;
         Pfn1->u3.e2.ReferenceCount = 0xFFF0;
         Pfn1->u3.e1.PageLocation = ActiveAndValid;
@@ -1404,8 +1404,10 @@ VOID
 NTAPI
 MiBuildPagedPool(VOID)
 {
-    PMMPTE PointerPte, PointerPde;
+    PMMPTE PointerPte;
+    PMMPDE PointerPde;
     MMPTE TempPte = ValidKernelPte;
+    MMPDE TempPde = ValidKernelPde;
     PFN_NUMBER PageFrameIndex;
     KIRQL OldIrql;
     ULONG Size, BitMapSize;
@@ -1506,10 +1508,10 @@ MiBuildPagedPool(VOID)
     // Allocate a page and map the first paged pool PDE
     //
     PageFrameIndex = MmAllocPage(MC_NPPOOL);
-    TempPte.u.Hard.PageFrameNumber = PageFrameIndex;
+    TempPde.u.Hard.PageFrameNumber = PageFrameIndex;
     ASSERT(PointerPde->u.Hard.Valid == 0);
-    ASSERT(TempPte.u.Hard.Valid == 1);
-    *PointerPde = TempPte;
+    ASSERT(TempPde.u.Hard.Valid == 1);
+    *PointerPde = TempPde;
 
     //
     // Release the PFN database lock
@@ -1521,7 +1523,7 @@ MiBuildPagedPool(VOID)
     // will be allocated to handle paged pool growth. This is where they'll have
     // to start.
     //
-    MmPagedPoolInfo.NextPdeForPagedPoolExpansion = PointerPde + 1;
+    MmPagedPoolInfo.NextPdeForPagedPoolExpansion = (PMMPTE)(PointerPde + 1);
 
     //
     // We keep track of each page via a bit, so check how big the bitmap will