{
BOOLEAN Jump = FALSE;
CHAR Offset = 0;
+ BOOLEAN Size = State->SegmentRegs[FAST486_REG_CS].Size;
/* Make sure this is the right instruction */
ASSERT((Opcode & 0xF0) == 0x70);
+ TOGGLE_OPSIZE(Size);
+
/* Fetch the offset */
if (!Fast486FetchByte(State, (PUCHAR)&Offset))
{
{
/* Move the instruction pointer */
State->InstPtr.Long += Offset;
+
+ if (!Size)
+ {
+ /* Clear the top half of EIP */
+ State->InstPtr.Long &= 0xFFFF;
+ }
}
/* Return success */
FAST486_OPCODE_HANDLER(Fast486OpcodeShortJump)
{
CHAR Offset = 0;
+ BOOLEAN Size = State->SegmentRegs[FAST486_REG_CS].Size;
+
+ TOGGLE_OPSIZE(Size);
/* Make sure this is the right instruction */
ASSERT(Opcode == 0xEB);
/* Move the instruction pointer */
State->InstPtr.Long += Offset;
+ if (!Size)
+ {
+ /* Clear the top half of EIP */
+ State->InstPtr.Long &= 0xFFFF;
+ }
+
return TRUE;
}
}
/* Move the instruction pointer */
- State->InstPtr.LowWord += Offset;
+ State->InstPtr.Long += Offset;
+
+ /* Clear the top half of EIP */
+ State->InstPtr.Long &= 0xFFFF;
}
return TRUE;
return FALSE;
}
- /* Load new (E)IP */
- if (Size) State->InstPtr.Long = Offset;
- else State->InstPtr.LowWord = LOWORD(Offset);
+ /* Load new EIP */
+ State->InstPtr.Long = Offset;
return TRUE;
}
/* Set the IP to the address */
State->InstPtr.LowWord = Value;
+
+ /* Clear the top half of EIP */
+ State->InstPtr.Long &= 0xFFFF;
}
else if (ModRegRm.Register == 3)
{
/* Set the IP to the address */
State->InstPtr.LowWord = Value;
+ /* Clear the top half of EIP */
+ State->InstPtr.Long &= 0xFFFF;
}
else if (ModRegRm.Register == 4)
{
/* Set the IP to the address */
State->InstPtr.LowWord = Value;
+
+ /* Clear the top half of EIP */
+ State->InstPtr.Long &= 0xFFFF;
}
else if (ModRegRm.Register == 6)
{