We now define _disable and _enable for ARM.
We shouldn't define KeRaiseIrqlToSynchLevel for each architecture, since the prototype is portable itself.
It was a mistake to guard against x86 only system calls -- the system calls should be the same on all archs, just return STATUS_NOT_IMPLEMENTED if they don't make sense. Undo the guards.
We now define KeGetPcr() as portable -- it's PCR itself that is a per-arch define.
We now support ARM in RtlWalkFrameChain.
We now support ARM in PspCreateThread.
We now define KeArchHaltProcessor for ARM by using Wait-For-Interrupt Mode.
We now define KeArmInitThreadWithContext for ARM.
KiRestore/SaveProcessorControlState are portable prototypes, we now define them as such.
Bochs KD code should use the portable WRITE/READ_PORT_UCHAR defines, we now do so.
We now support ARM in SharedUserData->ImageNumberLow/High during ExpInitializeExecutive.
NtQuerySytemInformation for SystemProcessorInformation has now been fixed to use the portable KeProcesssorXxx variables instead of reading from the non-portable PRCB values.
We now support NtFlushInstructionCache for ARM by flushing the I-Cache.
svn path=/trunk/; revision=32197
KeRaiseIrqlToDpcLevel(
VOID);
-NTHALAPI
-KIRQL
-DDKAPI
-KeRaiseIrqlToSynchLevel(
- VOID);
-
#define KeLowerIrql(a) KfLowerIrql(a)
#define KeRaiseIrql(a,b) *(b) = KfRaiseIrql(a)
KeRaiseIrqlToDpcLevel(
VOID);
+#endif
+
NTKERNELAPI
KIRQL
DDKAPI
KeRaiseIrqlToSynchLevel(
VOID);
-#endif
-
+
/** Memory manager routines **/
NTKERNELAPI
#define PRCB_BUILD_DEBUG 1
#define PRCB_BUILD_UNIPROCESSOR 2
+//
+// No LDTs on ARM
+//
+#define LDT_ENTRY ULONG
+
//
// HAL Variables
//
//
#define K0IPCR ((ULONG_PTR)(KIP0PCRADDRESS))
#define PCR ((volatile KPCR * const)K0IPCR)
-#if !defined(CONFIG_SMP) && !defined(NT_BUILD)
-#define KeGetPcr() PCR
-#else
+#if defined(CONFIG_SMP) || defined(NT_BUILD)
+#undef KeGetPcr()
#define KeGetPcr() ((volatile KPCR * const)__readfsdword(0x1C))
#endif
IN KPROFILE_SOURCE ClockSource
);
-#ifdef _M_IX86
NTSYSCALLAPI
NTSTATUS
NTAPI
IN ULONG Selector2,
IN LDT_ENTRY LdtEntry2
);
-#endif
NTSYSCALLAPI
NTSTATUS
IN KPROFILE_SOURCE ClockSource
);
-#ifdef _M_IX86
NTSYSAPI
NTSTATUS
NTAPI
IN ULONG Selector2,
IN LDT_ENTRY LdtEntry2
);
-#endif
NTSYSAPI
NTSTATUS
#define KINTERRUPT_DISPATCH_CODES 106
#endif
+//
+// Get KPCR
+//
+#define KeGetPcr() PCR
+
#ifdef NTOS_MODE_USER
//
return _InterlockedExchangeAdd16(lpAddend, 1) + 1;
}
+static __inline__ __attribute__((always_inline)) void _disable(void)
+{
+ __asm__ __volatile__
+ (
+ "mrs r1, cpsr;"
+ "orr r1, r1, #0x80;"
+ "msr cpsr, r1;"
+ );
+}
+
+static __inline__ __attribute__((always_inline)) void _enable(void)
+{
+ __asm__ __volatile__
+ (
+ "mrs r1, cpsr;"
+ "bic r1, r1, #0x80;"
+ "msr cpsr, r1;"
+ );
+}
+
#endif
/* EOF */
//
// NT-ARM is not documented
//
+#define KIRQL ULONG // Hack!
#include <armddk.h>
#else
//
// IRQL Support on ARM is similar to MIPS/ALPHA
//
-NTKERNELAPI
KIRQL
-DDKAPI
KeSwapIrql(
IN KIRQL NewIrql
);
-NTKERNELAPI
KIRQL
-NTAPI
KeRaiseIrqlToDpcLevel(
VOID
);
#elif defined(_MIPS_)
SharedUserData->ImageNumberLow = IMAGE_FILE_MACHINE_R4000;
SharedUserData->ImageNumberHigh = IMAGE_FILE_MACHINE_R4000;
+#elif defined(_ARM_)
+ SharedUserData->ImageNumberLow = IMAGE_FILE_MACHINE_ARM;
+ SharedUserData->ImageNumberHigh = IMAGE_FILE_MACHINE_ARM;
#else
#error "Unsupported ReactOS Target"
#endif
return (STATUS_INFO_LENGTH_MISMATCH);
}
Prcb = KeGetCurrentPrcb();
- Spi->ProcessorArchitecture = 0; /* Intel Processor */
- Spi->ProcessorLevel = Prcb->CpuType;
- Spi->ProcessorRevision = Prcb->CpuStep;
+ Spi->ProcessorArchitecture = KeProcessorArchitecture;
+ Spi->ProcessorLevel = KeProcessorLevel;
+ Spi->ProcessorRevision = KeProcessorRevision;
Spi->Reserved = 0;
- Spi->ProcessorFeatureBits = Prcb->FeatureBits;
+ Spi->ProcessorFeatureBits = KeFeatureBits;
DPRINT("Arch %d Level %d Rev 0x%x\n", Spi->ProcessorArchitecture,
Spi->ProcessorLevel, Spi->ProcessorRevision);
#elif defined(_M_MIPS)
DPRINT1("NtFlushInstructionCache() is not implemented\n");
for (;;);
+#elif defined(_M_ARM)
+ __asm__ __volatile__("mov r1, #0; mcr p15, 0, r1, c7, c5, 0");
#else
#error Unknown architecture
#endif
#elif defined(_M_MIPS)\r
#include "../mips/intrin_i.h"\r
#elif defined(_M_ARM)\r
-//\r
-// Not sure we'll need ARM internal intrinsics\r
-//\r
+#include "../arm/intrin_i.h"\r
#else\r
#error "Unknown processor"\r
#endif\r
--- /dev/null
+#ifndef _INTRIN_INTERNAL_
+#define _INTRIN_INTERNAL_
+
+static __inline__ __attribute__((always_inline)) void KeArchHaltProcessor(void)
+{
+ //
+ // Enter Wait-For-Interrupt Mode
+ //
+ __asm__ __volatile__
+ (
+ "mov r1, #0;"
+ "mcr p15, 0, r1, c7, c0, 4;"
+ );
+}
+
+#endif
+
+/* EOF */
+#ifndef __NTOSKRNL_INCLUDE_INTERNAL_ARM_KE_H
+#define __NTOSKRNL_INCLUDE_INTERNAL_ARM_KE_H
+#if __GNUC__ >=3
+#pragma GCC system_header
+#endif
+
+VOID
+NTAPI
+KeArmInitThreadWithContext(
+ IN PKTHREAD Thread,
+ IN PKSYSTEM_ROUTINE SystemRoutine,
+ IN PKSTART_ROUTINE StartRoutine,
+ IN PVOID StartContext,
+ IN PCONTEXT Context
+);
+
+#define KeArchInitThreadWithContext KeArmInitThreadWithContext
+
+#endif
\ No newline at end of file
IN PKGDTENTRY Gdt
);
-VOID
-NTAPI
-KiRestoreProcessorControlState(
- IN PKPROCESSOR_STATE ProcessorState
-);
-
-VOID
-NTAPI
-KiSaveProcessorControlState(
- OUT PKPROCESSOR_STATE ProcessorState
-);
-
VOID
FASTCALL
KiIdleLoop(VOID);
IN OUT PKSPIN_LOCK_QUEUE LockQueue
);
+VOID
+NTAPI
+KiRestoreProcessorControlState(
+ IN PKPROCESSOR_STATE ProcessorState
+);
+
+VOID
+NTAPI
+KiSaveProcessorControlState(
+ OUT PKPROCESSOR_STATE ProcessorState
+);
+
#include "ke_x.h"
#endif /* __NTOSKRNL_INCLUDE_INTERNAL_KE_H */
#include <internal/debug.h>
/* bochs debug output */
-#define BOCHS_LOGGER_PORT (0xe9)
+#define BOCHS_LOGGER_PORT ((PVOID)0xe9)
/* FUNCTIONS *****************************************************************/
{
if (*Message == '\n')
{
- __outbyte(BOCHS_LOGGER_PORT, '\r');
+ WRITE_PORT_UCHAR(BOCHS_LOGGER_PORT, '\r');
}
- __outbyte(BOCHS_LOGGER_PORT, *Message);
+ WRITE_PORT_UCHAR(BOCHS_LOGGER_PORT, *Message);
Message++;
}
}
if (BootPhase == 0)
{
- Value = __inbyte(BOCHS_LOGGER_PORT);
- if (Value != BOCHS_LOGGER_PORT)
+ Value = READ_PORT_UCHAR(BOCHS_LOGGER_PORT);
+ if (Value != (ULONG)BOCHS_LOGGER_PORT)
{
KdpDebugMode.Bochs = FALSE;
return;
*/
MiInitPageDirectoryMap();
- BaseAddress = (PVOID)KIP0PCRADDRESS;
+ BaseAddress = (PVOID)PCR;
MmCreateMemoryArea(MmGetKernelAddressSpace(),
MEMORY_AREA_SYSTEM,
&BaseAddress,
Thread->StartAddress = (PVOID)ThreadContext->Eip;
Thread->Win32StartAddress = (PVOID)ThreadContext->Eax;
#elif defined(_M_PPC)
- Thread->StartAddress = (PVOID)ThreadContext->Dr0;
- Thread->Win32StartAddress = (PVOID)ThreadContext->Gpr3;
+ Thread->StartAddress = (PVOID)ThreadContext->Dr0;
+ Thread->Win32StartAddress = (PVOID)ThreadContext->Gpr3;
#elif defined(_M_MIPS)
- for (;;);
+ Thread->StartAddress = (PVOID)ThreadContext->Psr;
+ Thread->Win32StartAddress = (PVOID)ThreadContext->IntA0;
+#elif defined(_M_ARM)
+ Thread->StartAddress = (PVOID)ThreadContext->Pc;
+ Thread->Win32StartAddress = (PVOID)ThreadContext->R0;
#else
#error Unknown architecture
#endif
__asm__("move $sp, %0" : "=r" (Stack) : );
#elif defined(_M_PPC)
__asm__("mr %0,1" : "=r" (Stack) : );
+#elif defined(_M_ARM)
+ __asm__("mov sp, %0" : "=r"(Stack) : );
#else
#error Unknown architecture
#endif