From 2a91ad3419fe0e0001d481eddd1ebe0522866b59 Mon Sep 17 00:00:00 2001 From: Sir Richard Date: Wed, 24 Nov 2010 15:21:45 +0000 Subject: [PATCH] [NTOS]: Fix incorrect assumptions that a PDE == PTE which have crept up throughout new ARM3 code. [NTOS]: Fix a couple more unportable directly "Hard" PTE field accesses, instead of using portable MI macros. [NTOS]: Cleanup some of the pool code that had really messed up PDE vs PTE. [NTOS]: Define the number of page directoty levels for ARM. [NTOS]: Comment out some ARM3 code that won't be needed now that most of the x86 code is in C. Fixes all but one build error. svn path=/trunk/; revision=49774 --- reactos/ntoskrnl/include/internal/arm/mm.h | 12 +++++++- reactos/ntoskrnl/include/internal/i386/mm.h | 13 +------- reactos/ntoskrnl/include/internal/mm.h | 2 +- reactos/ntoskrnl/ke/arm/trapc.c | 6 ++++ reactos/ntoskrnl/mm/ARM3/arm/init.c | 6 ++-- reactos/ntoskrnl/mm/ARM3/miarm.h | 33 +++++++++++++++++++-- reactos/ntoskrnl/mm/ARM3/mminit.c | 26 ++++++++-------- reactos/ntoskrnl/mm/ARM3/pagfault.c | 8 ++--- reactos/ntoskrnl/mm/ARM3/pool.c | 33 ++++++++++----------- reactos/ntoskrnl/mm/ARM3/procsup.c | 6 ++-- reactos/ntoskrnl/mm/ARM3/section.c | 6 ++-- reactos/ntoskrnl/mm/amd64/init.c | 4 +-- 12 files changed, 93 insertions(+), 62 deletions(-) diff --git a/reactos/ntoskrnl/include/internal/arm/mm.h b/reactos/ntoskrnl/include/internal/arm/mm.h index 83b0d480382..f70f5c46f21 100644 --- a/reactos/ntoskrnl/include/internal/arm/mm.h +++ b/reactos/ntoskrnl/include/internal/arm/mm.h @@ -1,5 +1,7 @@ #pragma once +#define _MI_PAGING_LEVELS 2 + #define PDE_SHIFT 20 // @@ -116,6 +118,7 @@ PULONG MmGetPageDirectory(VOID); #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.ReadOnly == 0) #define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE #define MI_IS_PAGE_DIRTY(x) TRUE +#define MI_IS_PAGE_LARGE(x) FALSE /* Easy accessing PFN in PTE */ #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber) @@ -131,6 +134,12 @@ PULONG MmGetPageDirectory(VOID); MI_HYPERSPACE_PTES * PAGE_SIZE) #define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \ PAGE_SIZE) +#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \ + PAGE_SIZE) +#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + \ + PAGE_SIZE) +#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + \ + PAGE_SIZE) /* Retrives the PDE entry for the given VA */ #define MiGetPdeAddress(x) ((PMMPDE)(PDE_BASE + (((ULONG)(x) >> 20) << 2))) @@ -142,7 +151,8 @@ PULONG MmGetPageDirectory(VOID); /* Retrives the PDE offset for the given VA */ #define MiGetPdeOffset(x) (((ULONG)(x)) >> 20) - +//#define MiGetPteOffset(x) (((ULONG)(x)) >> 12) + /* Convert a PTE into a corresponding address */ #define MiPteToAddress(x) ((PVOID)((ULONG)(x) << 10)) #define MiPdeToAddress(x) ((PVOID)((ULONG)(x) << 18)) diff --git a/reactos/ntoskrnl/include/internal/i386/mm.h b/reactos/ntoskrnl/include/internal/i386/mm.h index f201e454ce5..e8cfd55ae77 100644 --- a/reactos/ntoskrnl/include/internal/i386/mm.h +++ b/reactos/ntoskrnl/include/internal/i386/mm.h @@ -55,6 +55,7 @@ PULONG MmGetPageDirectory(VOID); #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1) #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1) #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0) +#define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.Large == 1) #if !defined(CONFIG_SMP) #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1) #else @@ -80,18 +81,6 @@ PULONG MmGetPageDirectory(VOID); #define TEB_BASE 0x7FFDE000 -#define MI_HYPERSPACE_PTES (256 - 1) -#define MI_ZERO_PTES (32) -#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE -#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \ - MI_HYPERSPACE_PTES * PAGE_SIZE) -#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \ - PAGE_SIZE) -#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + \ - PAGE_SIZE) -#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + \ - PAGE_SIZE) - /* On x86, these two are the same */ #define MMPDE MMPTE #define PMMPDE PMMPTE diff --git a/reactos/ntoskrnl/include/internal/mm.h b/reactos/ntoskrnl/include/internal/mm.h index 3c194f5684d..02fa7e9d6d6 100644 --- a/reactos/ntoskrnl/include/internal/mm.h +++ b/reactos/ntoskrnl/include/internal/mm.h @@ -486,7 +486,7 @@ typedef struct _MM_PAGED_POOL_INFO PRTL_BITMAP EndOfPagedPoolBitmap; PMMPTE FirstPteForPagedPool; PMMPTE LastPteForPagedPool; - PMMPTE NextPdeForPagedPoolExpansion; + PMMPDE NextPdeForPagedPoolExpansion; ULONG PagedPoolHint; SIZE_T PagedPoolCommit; SIZE_T AllocatedPagedPool; diff --git a/reactos/ntoskrnl/ke/arm/trapc.c b/reactos/ntoskrnl/ke/arm/trapc.c index edfedf42820..d2ff8c426e4 100644 --- a/reactos/ntoskrnl/ke/arm/trapc.c +++ b/reactos/ntoskrnl/ke/arm/trapc.c @@ -15,6 +15,7 @@ /* FUNCTIONS ******************************************************************/ +#if 0 VOID KiIdleLoop(VOID) { @@ -89,6 +90,7 @@ KiIdleLoop(VOID) } } } +#endif VOID NTAPI @@ -116,6 +118,7 @@ KiSwapProcess(IN PKPROCESS NewProcess, while (TRUE); } +#if 0 BOOLEAN KiSwapContextInternal(IN PKTHREAD OldThread, IN PKTHREAD NewThread) @@ -220,6 +223,7 @@ KiSwapContextInternal(IN PKTHREAD OldThread, // return FALSE; } +#endif VOID KiApcInterrupt(VOID) @@ -262,6 +266,7 @@ KiApcInterrupt(VOID) KiDeliverApc(PreviousMode, &ExceptionFrame, TrapFrame); } +#if 0 VOID KiDispatchInterrupt(VOID) { @@ -343,6 +348,7 @@ KiDispatchInterrupt(VOID) KiSwapContext(OldThread, NewThread); } } +#endif VOID KiInterruptHandler(IN PKTRAP_FRAME TrapFrame, diff --git a/reactos/ntoskrnl/mm/ARM3/arm/init.c b/reactos/ntoskrnl/mm/ARM3/arm/init.c index 091d0cb7b5e..b7bfd841220 100644 --- a/reactos/ntoskrnl/mm/ARM3/arm/init.c +++ b/reactos/ntoskrnl/mm/ARM3/arm/init.c @@ -42,7 +42,7 @@ ULONG MmSessionImageSize; PVOID MiSystemViewStart; ULONG MmSystemViewSize; PFN_NUMBER MmSystemPageDirectory[PD_COUNT]; -PMMPTE MmSystemPagePtes; +PMMPDE MmSystemPagePtes; ULONG MmNumberOfSystemPtes; ULONG MxPfnAllocation; RTL_BITMAP MiPfnBitMap; @@ -61,7 +61,7 @@ PVOID MmHyperSpaceEnd; /* PRIVATE FUNCTIONS **********************************************************/ -NTSTATUS +BOOLEAN NTAPI MmArmInitSystem(IN ULONG Phase, IN PLOADER_PARAMETER_BLOCK LoaderBlock) @@ -71,7 +71,7 @@ MmArmInitSystem(IN ULONG Phase, // DPRINT1("NEVER TELL ME THE ODDS!\n"); while (TRUE); - return STATUS_SUCCESS; + return TRUE; } /* EOF */ diff --git a/reactos/ntoskrnl/mm/ARM3/miarm.h b/reactos/ntoskrnl/mm/ARM3/miarm.h index df5f178c37b..07e2224dc3d 100644 --- a/reactos/ntoskrnl/mm/ARM3/miarm.h +++ b/reactos/ntoskrnl/mm/ARM3/miarm.h @@ -235,7 +235,7 @@ extern const ULONG MmProtectToValue[32]; #define MI_GET_NEXT_COLOR(x) (MI_GET_PAGE_COLOR(++MmSystemPageColor)) #define MI_GET_NEXT_PROCESS_COLOR(x) (MI_GET_PAGE_COLOR(++(x)->NextPageColor)) -#ifdef _M_IX86 +#ifndef _M_AMD64 // // Decodes a Prototype PTE into the underlying PTE // @@ -462,7 +462,7 @@ extern PMMPTE MiSessionImagePteEnd; extern PMMPTE MiSessionBasePte; extern PMMPTE MiSessionLastPte; extern SIZE_T MmSizeOfPagedPoolInBytes; -extern PMMPTE MmSystemPagePtes; +extern PMMPDE MmSystemPagePtes; extern PVOID MmSystemCacheStart; extern PVOID MmSystemCacheEnd; extern MMSUPPORT MmSystemCacheWs; @@ -607,7 +607,7 @@ MI_MAKE_HARDWARE_PTE_USER(IN PMMPTE NewPte, NewPte->u.Long |= MmProtectToPteMask[ProtectionMask]; } -#ifdef _M_IX86 +#ifndef _M_AMD64 // // Builds a Prototype PTE for the address of the PTE // @@ -677,6 +677,33 @@ MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte, *PointerPte = InvalidPte; } +// +// Writes a valid PDE +// +VOID +FORCEINLINE +MI_WRITE_VALID_PDE(IN PMMPDE PointerPde, + IN MMPDE TempPde) +{ + /* Write the valid PDE */ + ASSERT(PointerPde->u.Hard.Valid == 0); + ASSERT(TempPde.u.Hard.Valid == 1); + *PointerPde = TempPde; +} + +// +// Writes an invalid PDE +// +VOID +FORCEINLINE +MI_WRITE_INVALID_PDE(IN PMMPDE PointerPde, + IN MMPDE InvalidPde) +{ + /* Write the invalid PDE */ + ASSERT(InvalidPde.u.Hard.Valid == 0); + *PointerPde = InvalidPde; +} + // // Checks if the thread already owns a working set // diff --git a/reactos/ntoskrnl/mm/ARM3/mminit.c b/reactos/ntoskrnl/mm/ARM3/mminit.c index 6a36dd3acc8..b977a65152a 100644 --- a/reactos/ntoskrnl/mm/ARM3/mminit.c +++ b/reactos/ntoskrnl/mm/ARM3/mminit.c @@ -161,7 +161,7 @@ SIZE_T MmSystemViewSize; // address. // PFN_NUMBER MmSystemPageDirectory[PD_COUNT]; -PMMPTE MmSystemPagePtes; +PMMPDE MmSystemPagePtes; #endif // @@ -679,7 +679,7 @@ MiBuildPfnDatabaseFromPages(IN PLOADER_PARAMETER_BLOCK LoaderBlock) /* Yes we do, set it up */ Pfn1 = MiGetPfnEntry(PageFrameIndex); Pfn1->u4.PteFrame = StartupPdIndex; - Pfn1->PteAddress = PointerPde; + Pfn1->PteAddress = (PMMPTE)PointerPde; Pfn1->u2.ShareCount++; Pfn1->u3.e2.ReferenceCount = 1; Pfn1->u3.e1.PageLocation = ActiveAndValid; @@ -771,7 +771,7 @@ MiBuildPfnDatabaseZeroPage(VOID) /* Make it a bogus page to catch errors */ PointerPde = MiAddressToPde(0xFFFFFFFF); Pfn1->u4.PteFrame = PFN_FROM_PTE(PointerPde); - Pfn1->PteAddress = PointerPde; + Pfn1->PteAddress = (PMMPTE)PointerPde; Pfn1->u2.ShareCount++; Pfn1->u3.e2.ReferenceCount = 0xFFF0; Pfn1->u3.e1.PageLocation = ActiveAndValid; @@ -1192,7 +1192,7 @@ INIT_FUNCTION MiAddHalIoMappings(VOID) { PVOID BaseAddress; - PMMPTE PointerPde; + PMMPDE PointerPde; PMMPTE PointerPte; ULONG i, j, PdeCount; PFN_NUMBER PageFrameIndex; @@ -1203,12 +1203,12 @@ MiAddHalIoMappings(VOID) /* Check how many PDEs the heap has */ PointerPde = MiAddressToPde(BaseAddress); - PdeCount = PDE_COUNT - ADDR_TO_PDE_OFFSET(BaseAddress); + PdeCount = PDE_COUNT - MiGetPdeOffset(BaseAddress); for (i = 0; i < PdeCount; i++) { /* Does the HAL own this mapping? */ if ((PointerPde->u.Hard.Valid == 1) && - (PointerPde->u.Hard.LargePage == 0)) + (MI_IS_PAGE_LARGE(PointerPde) == FALSE)) { /* Get the PTE for it and scan each page */ PointerPte = MiAddressToPte(BaseAddress); @@ -1556,8 +1556,10 @@ NTAPI INIT_FUNCTION MiBuildPagedPool(VOID) { - PMMPTE PointerPte, PointerPde; + PMMPTE PointerPte; + PMMPDE PointerPde; MMPTE TempPte = ValidKernelPte; + MMPDE TempPde = ValidKernelPde; PFN_NUMBER PageFrameIndex; KIRQL OldIrql; ULONG Size, BitMapSize; @@ -1648,7 +1650,7 @@ MiBuildPagedPool(VOID) #endif RtlZeroMemory(PointerPde, - (1 + MiAddressToPde(MmPagedPoolEnd) - PointerPde) * sizeof(MMPTE)); + (1 + MiAddressToPde(MmPagedPoolEnd) - PointerPde) * sizeof(MMPDE)); // // Next, get the first and last PTE @@ -1666,8 +1668,8 @@ MiBuildPagedPool(VOID) MI_SET_USAGE(MI_USAGE_PAGED_POOL); MI_SET_PROCESS2("Kernel"); PageFrameIndex = MiRemoveZeroPage(0); - TempPte.u.Hard.PageFrameNumber = PageFrameIndex; - MI_WRITE_VALID_PTE(PointerPde, TempPte); + TempPde.u.Hard.PageFrameNumber = PageFrameIndex; + MI_WRITE_VALID_PDE(PointerPde, TempPde); #if (_MI_PAGING_LEVELS >= 3) /* Use the PPE of MmPagedPoolStart that was setup above */ // Bla = PFN_FROM_PTE(PpeAddress(MmPagedPool...)); @@ -1678,8 +1680,8 @@ MiBuildPagedPool(VOID) /* Initialize the PFN entry for it */ MiInitializePfnForOtherProcess(PageFrameIndex, - PointerPde, - MmSystemPageDirectory[(PointerPde - (PMMPTE)PDE_BASE) / PDE_COUNT]); + (PMMPTE)PointerPde, + MmSystemPageDirectory[(PointerPde - (PMMPDE)PDE_BASE) / PDE_COUNT]); #endif // diff --git a/reactos/ntoskrnl/mm/ARM3/pagfault.c b/reactos/ntoskrnl/mm/ARM3/pagfault.c index 41cce6dcfc7..20264a1faf0 100644 --- a/reactos/ntoskrnl/mm/ARM3/pagfault.c +++ b/reactos/ntoskrnl/mm/ARM3/pagfault.c @@ -325,7 +325,7 @@ MiResolveDemandZeroFault(IN PVOID Address, } /* Set it dirty if it's a writable page */ - if (TempPte.u.Hard.Write) TempPte.u.Hard.Dirty = TRUE; + if (MI_IS_PAGE_WRITEABLE(&TempPte)) MI_MAKE_DIRTY_PAGE(&TempPte); /* Write it */ MI_WRITE_VALID_PTE(PointerPte, TempPte); @@ -899,7 +899,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction, ASSERT(ProtectionCode != MM_NOACCESS); /* Make the PDE demand-zero */ - MI_WRITE_INVALID_PTE(PointerPde, DemandZeroPde); + MI_WRITE_INVALID_PDE(PointerPde, DemandZeroPde); /* And go dispatch the fault on the PDE. This should handle the demand-zero */ #if MI_TRACE_PFNS @@ -907,7 +907,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction, #endif Status = MiDispatchFault(TRUE, PointerPte, - PointerPde, + (PMMPTE)PointerPde, NULL, FALSE, PsGetCurrentProcess(), @@ -1058,7 +1058,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction, } /* Write the dirty bit for writeable pages */ - if (TempPte.u.Hard.Write) TempPte.u.Hard.Dirty = TRUE; + if (MI_IS_PAGE_WRITEABLE(&TempPte)) MI_MAKE_DIRTY_PAGE(&TempPte); /* And now write down the PTE, making the address valid */ MI_WRITE_VALID_PTE(PointerPte, TempPte); diff --git a/reactos/ntoskrnl/mm/ARM3/pool.c b/reactos/ntoskrnl/mm/ARM3/pool.c index a808ff5d98d..1efdbc513a1 100644 --- a/reactos/ntoskrnl/mm/ARM3/pool.c +++ b/reactos/ntoskrnl/mm/ARM3/pool.c @@ -375,7 +375,7 @@ NTAPI MiAllocatePoolPages(IN POOL_TYPE PoolType, IN SIZE_T SizeInBytes) { - PFN_NUMBER SizeInPages, PageFrameNumber; + PFN_NUMBER SizeInPages, PageFrameNumber, PageTableCount; ULONG i; KIRQL OldIrql; PLIST_ENTRY NextEntry, NextHead, LastHead; @@ -422,7 +422,7 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType, // Check if there is enougn paged pool expansion space left // if (MmPagedPoolInfo.NextPdeForPagedPoolExpansion > - MiAddressToPte(MmPagedPoolInfo.LastPteForPagedPool)) + (PMMPDE)MiAddressToPte(MmPagedPoolInfo.LastPteForPagedPool)) { // // Out of memory! @@ -436,23 +436,23 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType, // Check if we'll have to expand past the last PTE we have available // if (((i - 1) + MmPagedPoolInfo.NextPdeForPagedPoolExpansion) > - MiAddressToPte(MmPagedPoolInfo.LastPteForPagedPool)) + (PMMPDE)MiAddressToPte(MmPagedPoolInfo.LastPteForPagedPool)) { // // We can only support this much then // - SizeInPages = MiAddressToPte(MmPagedPoolInfo.LastPteForPagedPool) - - MmPagedPoolInfo.NextPdeForPagedPoolExpansion + - 1; - ASSERT(SizeInPages < i); - i = SizeInPages; + PageTableCount = (PMMPDE)MiAddressToPte(MmPagedPoolInfo.LastPteForPagedPool) - + MmPagedPoolInfo.NextPdeForPagedPoolExpansion + + 1; + ASSERT(PageTableCount < i); + i = PageTableCount; } else { // // Otherwise, there is plenty of space left for this expansion // - SizeInPages = i; + PageTableCount = i; } // @@ -464,7 +464,7 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType, // Get the first PTE in expansion space // PointerPde = MmPagedPoolInfo.NextPdeForPagedPoolExpansion; - BaseVa = MiPteToAddress(PointerPde); + BaseVa = MiPdeToAddress(PointerPde); BaseVaStart = BaseVa; // @@ -494,11 +494,11 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType, /* Initialize the PFN */ MiInitializePfnForOtherProcess(PageFrameNumber, - PointerPde, + (PMMPTE)PointerPde, MmSystemPageDirectory[(PointerPde - MiAddressToPde(NULL)) / PDE_COUNT]); /* Write the actual PDE now */ - MI_WRITE_VALID_PTE(PointerPde, TempPde); + MI_WRITE_VALID_PDE(PointerPde, TempPde); #endif // // Move on to the next expansion address @@ -517,26 +517,25 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType, // These pages are now available, clear their availablity bits // EndAllocation = (MmPagedPoolInfo.NextPdeForPagedPoolExpansion - - MiAddressToPte(MmPagedPoolInfo.FirstPteForPagedPool)) * + (PMMPDE)MiAddressToPte(MmPagedPoolInfo.FirstPteForPagedPool)) * PTE_COUNT; RtlClearBits(MmPagedPoolInfo.PagedPoolAllocationMap, EndAllocation, - SizeInPages * PTE_COUNT); + PageTableCount * PTE_COUNT); // // Update the next expansion location // - MmPagedPoolInfo.NextPdeForPagedPoolExpansion += SizeInPages; + MmPagedPoolInfo.NextPdeForPagedPoolExpansion += PageTableCount; // // Zero out the newly available memory // - RtlZeroMemory(BaseVaStart, SizeInPages * PAGE_SIZE); + RtlZeroMemory(BaseVaStart, PageTableCount * PAGE_SIZE); // // Now try consuming the pages again // - SizeInPages = BYTES_TO_PAGES(SizeInBytes); i = RtlFindClearBitsAndSet(MmPagedPoolInfo.PagedPoolAllocationMap, SizeInPages, 0); diff --git a/reactos/ntoskrnl/mm/ARM3/procsup.c b/reactos/ntoskrnl/mm/ARM3/procsup.c index aec5af6e413..afedcc21859 100644 --- a/reactos/ntoskrnl/mm/ARM3/procsup.c +++ b/reactos/ntoskrnl/mm/ARM3/procsup.c @@ -971,7 +971,7 @@ MmInitializeProcessAddressSpace(IN PEPROCESS Process, /* Do the same for hyperspace */ PointerPde = MiAddressToPde(HYPER_SPACE); PageFrameNumber = PFN_FROM_PTE(PointerPde); - MiInitializePfn(PageFrameNumber, PointerPde, TRUE); + MiInitializePfn(PageFrameNumber, (PMMPTE)PointerPde, TRUE); /* Setup the PFN for the PTE for the working set */ PointerPte = MiAddressToPte(MI_WORKING_SET_LIST); @@ -1195,7 +1195,7 @@ MmCreateProcessAddressSpace(IN ULONG MinWs, HyperIndex); /* Set it dirty and map it */ - PdePte.u.Hard.Dirty = TRUE; + MI_MAKE_DIRTY_PAGE(&PdePte); MI_WRITE_VALID_PTE(PointerPte, PdePte); /* Now get hyperspace's page table */ @@ -1228,7 +1228,7 @@ MmCreateProcessAddressSpace(IN ULONG MinWs, PdeIndex); /* Set it dirty and map it */ - PdePte.u.Hard.Dirty = TRUE; + MI_MAKE_DIRTY_PAGE(&PdePte); MI_WRITE_VALID_PTE(PointerPte, PdePte); /* Now get the page directory (which we'll double map, so call it a page table */ diff --git a/reactos/ntoskrnl/mm/ARM3/section.c b/reactos/ntoskrnl/mm/ARM3/section.c index 872c10e27a2..a51bdabba70 100644 --- a/reactos/ntoskrnl/mm/ARM3/section.c +++ b/reactos/ntoskrnl/mm/ARM3/section.c @@ -347,17 +347,17 @@ MiFillSystemPageDirectory(IN PVOID Base, /* Initialize its PFN entry, with the parent system page directory page table */ MiInitializePfnForOtherProcess(PageFrameIndex, - PointerPde, + (PMMPTE)PointerPde, MmSystemPageDirectory[(PointerPde - MiAddressToPde(NULL)) / PDE_COUNT]); /* Make the system PDE entry valid */ - MI_WRITE_VALID_PTE(SystemMapPde, TempPde); + MI_WRITE_VALID_PDE(SystemMapPde, TempPde); /* The system PDE entry might be the PDE itself, so check for this */ if (PointerPde->u.Hard.Valid == 0) { /* It's different, so make the real PDE valid too */ - MI_WRITE_VALID_PTE(PointerPde, TempPde); + MI_WRITE_VALID_PDE(PointerPde, TempPde); } } diff --git a/reactos/ntoskrnl/mm/amd64/init.c b/reactos/ntoskrnl/mm/amd64/init.c index a7aed95b36d..3211b99440d 100644 --- a/reactos/ntoskrnl/mm/amd64/init.c +++ b/reactos/ntoskrnl/mm/amd64/init.c @@ -752,9 +752,7 @@ MiBuildPagedPool_x(VOID) /* Save the first and last paged pool PTE */ MmPagedPoolInfo.FirstPteForPagedPool = MiAddressToPte(MmPagedPoolStart); MmPagedPoolInfo.LastPteForPagedPool = MiAddressToPte(MmPagedPoolEnd); - - MmPagedPoolInfo.NextPdeForPagedPoolExpansion = - MiAddressToPde(MmPagedPoolStart) + 1; + MmPagedPoolInfo.NextPdeForPagedPoolExpansion = MiAddressToPde(MmPagedPoolStart) + 1; // We keep track of each page via a bit, so check how big the bitmap will // have to be (make sure to align our page count such that it fits nicely -- 2.17.1