From b9761e9b019e7457bdecf7e677f87b562471df0c Mon Sep 17 00:00:00 2001 From: =?utf8?q?J=C3=A9r=C3=B4me=20Gardou?= Date: Tue, 13 Jul 2010 18:56:03 +0000 Subject: [PATCH] Amine lost his bet, part 2 of x svn path=/branches/reactos-yarotows/; revision=48028 --- include/reactos/drivers/acpi/acpi.h | 222 ++++++++++++++++++++++++++++ include/reactos/drivers/pci/pci.h | 125 ++++++++++++++++ 2 files changed, 347 insertions(+) create mode 100644 include/reactos/drivers/acpi/acpi.h create mode 100644 include/reactos/drivers/pci/pci.h diff --git a/include/reactos/drivers/acpi/acpi.h b/include/reactos/drivers/acpi/acpi.h new file mode 100644 index 00000000000..c9289b8402e --- /dev/null +++ b/include/reactos/drivers/acpi/acpi.h @@ -0,0 +1,222 @@ +/* + * PROJECT: ReactOS PCI Bus Driver + * LICENSE: BSD - See COPYING.ARM in the top level directory + * FILE: include/reactos/drivers/acpi/acpi.h + * PURPOSE: ACPI Tables and NT Registry Data + * PROGRAMMERS: ReactOS Portable Systems Group + */ + +// +// ACPI BIOS Registry Component Configuration Data +// +typedef struct _ACPI_E820_ENTRY +{ + PHYSICAL_ADDRESS Base; + LARGE_INTEGER Length; + ULONGLONG Type; +} ACPI_E820_ENTRY, *PACPI_E820_ENTRY; + +typedef struct _ACPI_BIOS_MULTI_NODE +{ + PHYSICAL_ADDRESS RsdtAddress; + ULONGLONG Count; + ACPI_E820_ENTRY E820Entry[1]; +} ACPI_BIOS_MULTI_NODE, *PACPI_BIOS_MULTI_NODE; + +// +// ACPI Signatures +// +#define RSDP_SIGNATURE 0x2052545020445352 // "RSD PTR " +#define FACS_SIGNATURE 0x53434146 // "FACS" +#define FADT_SIGNATURE 0x50434146 // "FACP" +#define RSDT_SIGNATURE 0x54445352 // "RSDT" +#define APIC_SIGNATURE 0x43495041 // "APIC" +#define DSDT_SIGNATURE 0x54445344 // "DSDT" +#define SSDT_SIGNATURE 0x54445353 // "SSDT" +#define PSDT_SIGNATURE 0x54445350 // "PSDT" +#define SBST_SIGNATURE 0x54534253 // "SBST" +#define DBGP_SIGNATURE 0x50474244 // "DBGP" +#define XSDT_SIGNATURE 'TDSX' +#define BOOT_SIGNATURE 'TOOB' +#define SRAT_SIGNATURE 'TARS' +#define WDRT_SIGNATURE 'TRDW' + +// +// FADT Flags +// +#define ACPI_TMR_VAL_EXT 0x100 + +// +// ACPI Generic Register Address +// +typedef struct _GEN_ADDR +{ + UCHAR AddressSpaceID; + UCHAR BitWidth; + UCHAR BitOffset; + UCHAR Reserved; + PHYSICAL_ADDRESS Address; +} GEN_ADDR, *PGEN_ADDR; + +// +// ACPI BIOS Structures (packed) +// +#include +typedef struct _RSDP +{ + ULONGLONG Signature; + UCHAR Checksum; + UCHAR OEMID[6]; + UCHAR Reserved[1]; + ULONG RsdtAddress; +} RSDP; +typedef RSDP *PRSDP; + +typedef struct _DESCRIPTION_HEADER +{ + ULONG Signature; + ULONG Length; + UCHAR Revision; + UCHAR Checksum; + UCHAR OEMID[6]; + UCHAR OEMTableID[8]; + ULONG OEMRevision; + UCHAR CreatorID[4]; + ULONG CreatorRev; +} DESCRIPTION_HEADER; +typedef DESCRIPTION_HEADER *PDESCRIPTION_HEADER; + +typedef struct _FACS +{ + ULONG Signature; + ULONG Length; + ULONG HardwareSignature; + ULONG pFirmwareWakingVector; + ULONG GlobalLock; + ULONG Flags; + PHYSICAL_ADDRESS x_FirmwareWakingVector; + UCHAR version; + UCHAR Reserved[32]; +} FACS; +typedef FACS *PFACS; + +typedef struct _FADT +{ + DESCRIPTION_HEADER Header; + ULONG facs; + ULONG dsdt; + UCHAR int_model; + UCHAR pm_profile; + USHORT sci_int_vector; + ULONG smi_cmd_io_port; + UCHAR acpi_on_value; + UCHAR acpi_off_value; + UCHAR s4bios_req; + UCHAR pstate_control; + ULONG pm1a_evt_blk_io_port; + ULONG pm1b_evt_blk_io_port; + ULONG pm1a_ctrl_blk_io_port; + ULONG pm1b_ctrl_blk_io_port; + ULONG pm2_ctrl_blk_io_port; + ULONG pm_tmr_blk_io_port; + ULONG gp0_blk_io_port; + ULONG gp1_blk_io_port; + UCHAR pm1_evt_len; + UCHAR pm1_ctrl_len; + UCHAR pm2_ctrl_len; + UCHAR pm_tmr_len; + UCHAR gp0_blk_len; + UCHAR gp1_blk_len; + UCHAR gp1_base; + UCHAR cstate_control; + USHORT lvl2_latency; + USHORT lvl3_latency; + USHORT flush_size; + USHORT flush_stride; + UCHAR duty_offset; + UCHAR duty_width; + UCHAR day_alarm_index; + UCHAR month_alarm_index; + UCHAR century_alarm_index; + USHORT boot_arch; + UCHAR reserved3[1]; + ULONG flags; + GEN_ADDR reset_reg; + UCHAR reset_val; + UCHAR reserved4[3]; + PHYSICAL_ADDRESS x_firmware_ctrl; + PHYSICAL_ADDRESS x_dsdt; + GEN_ADDR x_pm1a_evt_blk; + GEN_ADDR x_pm1b_evt_blk; + GEN_ADDR x_pm1a_ctrl_blk; + GEN_ADDR x_pm1b_ctrl_blk; + GEN_ADDR x_pm2_ctrl_blk; + GEN_ADDR x_pm_tmr_blk; + GEN_ADDR x_gp0_blk; + GEN_ADDR x_gp1_blk; +} FADT; +typedef FADT *PFADT; + +typedef struct _DSDT +{ + DESCRIPTION_HEADER Header; + UCHAR DiffDefBlock[ANYSIZE_ARRAY]; +} DSDT; +typedef DSDT *PDSDT; + +typedef struct _RSDT +{ + DESCRIPTION_HEADER Header; + ULONG Tables[ANYSIZE_ARRAY]; +} RSDT; +typedef RSDT *PRSDT; + +typedef struct _XSDT +{ + DESCRIPTION_HEADER Header; + PHYSICAL_ADDRESS Tables[ANYSIZE_ARRAY]; +} XSDT; +typedef XSDT *PXSDT; +#include + +// +// Microsoft-specific (pretty much) ACPI Tables, normal MS ABI packing +// +typedef struct _DEBUG_PORT_TABLE +{ + DESCRIPTION_HEADER Header; + UCHAR InterfaceType; + UCHAR Reserved[3]; + GEN_ADDR BaseAddress; +} DEBUG_PORT_TABLE, *PDEBUG_PORT_TABLE; + +typedef struct _WATCHDOG_TABLE +{ + DESCRIPTION_HEADER Header; + GEN_ADDR ControlRegister; + GEN_ADDR CountRegister; + USHORT PciDeviceId; + USHORT PciVendorId; + UCHAR PciBus; + UCHAR PciDevice; + UCHAR PciFunction; + UCHAR PciSegment; + USHORT MaxCount; + UCHAR Units; +} WATCHDOG_TABLE, *PWATCHDOG_TABLE; + +typedef struct _BOOT_TABLE +{ + DESCRIPTION_HEADER Header; + UCHAR CMOSIndex; + UCHAR Reserved[3]; +} BOOT_TABLE, *PBOOT_TABLE; + +typedef struct _ACPI_SRAT +{ + DESCRIPTION_HEADER Header; + UCHAR TableRevision; + ULONG Reserved[2]; +} ACPI_SRAT, *PACPI_SRAT; + +/* EOF */ diff --git a/include/reactos/drivers/pci/pci.h b/include/reactos/drivers/pci/pci.h new file mode 100644 index 00000000000..5833675b3cf --- /dev/null +++ b/include/reactos/drivers/pci/pci.h @@ -0,0 +1,125 @@ +/* + * PROJECT: ReactOS PCI Bus Driver + * LICENSE: BSD - See COPYING.ARM in the top level directory + * FILE: include/reactos/drivers/pci/pci.h + * PURPOSE: Internal, Shared, PCI Definitions + * PROGRAMMERS: ReactOS Portable Systems Group + */ + +// +// PCI Hack Flags +// +#define PCI_HACK_LOCK_RESOURCES 0x0000000000000004LL +#define PCI_HACK_NO_ENUM_AT_ALL 0x0000000000000008LL +#define PCI_HACK_ENUM_NO_RESOURCE 0x0000000000000010LL +#define PCI_HACK_AVOID_D1D2_FOR_SLD 0x0000000000000020LL +#define PCI_HACK_NEVER_DISCONNECT 0x0000000000000040LL +#define PCI_HACK_DONT_DISABLE 0x0000000000000080LL +#define PCI_HACK_MULTIFUNCTION 0x0000000000000100LL +#define PCI_HACK_UNUSED_200 0x0000000000000200LL +#define PCI_HACK_IGNORE_NON_STICKY_ISA 0x0000000000000400LL +#define PCI_HACK_UNUSED_800 0x0000000000000800LL +#define PCI_HACK_DOUBLE_DECKER 0x0000000000001000LL +#define PCI_HACK_ONE_CHILD 0x0000000000002000LL +#define PCI_HACK_PRESERVE_COMMAND 0x0000000000004000LL +#define PCI_HACK_DEFAULT_CARDBUS_WINDOWS 0x0000000000008000LL +#define PCI_HACK_CB_SHARE_CMD_BITS 0x0000000000010000LL +#define PCI_HACK_IGNORE_ROOT_TOPOLOGY 0x0000000000020000LL +#define PCI_HACK_SUBTRACTIVE_DECODE 0x0000000000040000LL +#define PCI_HACK_NO_EXPRESS_CAP 0x0000000000080000LL +#define PCI_HACK_NO_ASPM_FOR_EXPRESS_LINK 0x0000000000100000LL +#define PCI_HACK_CLEAR_INT_DISABLE_FOR_MSI 0x0000000000200000LL +#define PCI_HACK_NO_SUBSYSTEM 0x0000000000400000LL +#define PCI_HACK_COMMAND_REWRITE 0x0000000000800000LL +#define PCI_HACK_AVOID_HARDWARE_ISA_BIT 0x0000000001000000LL +#define PCI_HACK_FORCE_BRIDGE_WINDOW_ALIGNMENT 0x0000000002000000LL +#define PCI_HACK_NOT_MSI_HT_CONVERTER 0x0000000004000000LL +#define PCI_HACK_PCI_HACK_SBR_ON_LINK_STATE_CHANGE 0x0000000008000000LL +#define PCI_HACK_PCI_HACK_LINK_DISABLE_ON_SLOT_PWRDN 0x0000000010000000LL +#define PCI_HACK_NO_PM_CAPS 0x0000000020000000LL +#define PCI_HACK_DONT_DISABLE_DECODES 0x0000000040000000LL +#define PCI_HACK_NO_SUBSYSTEM_AFTER_D3 0x0000000080000000LL +#define PCI_HACK_VIDEO_LEGACY_DECODE 0x0000000100000000LL +#define PCI_HACK_FAKE_CLASS_CODE 0x0000000200000000LL +#define PCI_HACK_UNUSED_40000000 0x0000000400000000LL +#define PCI_HACK_UNUSED_80000000 0x0000000800000000LL +#define PCI_HACK_FAIL_QUERY_REMOVE 0x0000001000000000LL +#define PCI_HACK_CRITICAL_DEVICE 0x0000002000000000LL +#define PCI_HACK_UNUSED_4000000000 0x0000004000000000LL +#define PCI_HACK_BROKEN_SUBTRACTIVE_DECODE 0x0000008000000000LL +#define PCI_HACK_NO_REVISION_AFTER_D3 0x0000010000000000LL +#define PCI_HACK_ENABLE_MSI_MAPPING 0x0000020000000000LL +#define PCI_HACK_DISABLE_PM_DOWNSTREAM_PCI_BRIDGE 0x0000040000000000LL + +// +// Bit encodes for PCI_COMMON_CONFIG.u.type1.BridgeControl +// +#define PCI_ENABLE_BRIDGE_PARITY_ERROR 0x0001 +#define PCI_ENABLE_BRIDGE_SERR 0x0002 +#define PCI_ENABLE_BRIDGE_ISA 0x0004 +#define PCI_ENABLE_BRIDGE_VGA 0x0008 +#define PCI_ENABLE_BRIDGE_MASTER_ABORT_SERR 0x0020 +#define PCI_ASSERT_BRIDGE_RESET 0x0040 +#define PCI_ENABLE_BRIDGE_VGA_16BIT 0x0010 + +// +// PCI IRQ Routing Table in BIOS/Registry (Signature: PIR$) +// +#include +typedef struct _PIN_INFO +{ + UCHAR Link; + USHORT InterruptMap; +} PIN_INFO, *PPIN_INFO; + +typedef struct _SLOT_INFO +{ + UCHAR BusNumber; + UCHAR DeviceNumber; + PIN_INFO PinInfo[4]; + UCHAR SlotNumber; + UCHAR Reserved; +} SLOT_INFO, *PSLOT_INFO; + +typedef struct _PCI_IRQ_ROUTING_TABLE +{ + ULONG Signature; + USHORT Version; + USHORT TableSize; + UCHAR RouterBus; + UCHAR RouterDevFunc; + USHORT ExclusiveIRQs; + ULONG CompatibleRouter; + ULONG MiniportData; + UCHAR Reserved[11]; + UCHAR Checksum; + SLOT_INFO Slot[ANYSIZE_ARRAY]; +} PCI_IRQ_ROUTING_TABLE, *PPCI_IRQ_ROUTING_TABLE; +#include + +// +// PCI Registry Information +// +typedef struct _PCI_REGISTRY_INFO +{ + UCHAR MajorRevision; + UCHAR MinorRevision; + UCHAR NoBuses; // Number Of Buses + UCHAR HardwareMechanism; +} PCI_REGISTRY_INFO, *PPCI_REGISTRY_INFO; + +// +// PCI Card Descriptor in Registry +// +typedef struct _PCI_CARD_DESCRIPTOR +{ + ULONG Flags; + USHORT VendorID; + USHORT DeviceID; + USHORT RevisionID; + USHORT SubsystemVendorID; + USHORT SubsystemID; + USHORT Reserved; +} PCI_CARD_DESCRIPTOR, *PPCI_CARD_DESCRIPTOR; + +/* EOF */ -- 2.17.1